rockchip_i2s.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * sound/soc/rockchip/rockchip_i2s.h
  4. *
  5. * ALSA SoC Audio Layer - Rockchip I2S Controller driver
  6. *
  7. * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
  8. * Author: Jianqun xu <jay.xu@rock-chips.com>
  9. */
  10. #ifndef _ROCKCHIP_IIS_H
  11. #define _ROCKCHIP_IIS_H
  12. /*
  13. * TXCR
  14. * transmit operation control register
  15. */
  16. #define I2S_TXCR_RCNT_SHIFT 17
  17. #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
  18. #define I2S_TXCR_CSR_SHIFT 15
  19. #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
  20. #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
  21. #define I2S_TXCR_HWT BIT(14)
  22. #define I2S_TXCR_SJM_SHIFT 12
  23. #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
  24. #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
  25. #define I2S_TXCR_FBM_SHIFT 11
  26. #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
  27. #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
  28. #define I2S_TXCR_IBM_SHIFT 9
  29. #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
  30. #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
  31. #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
  32. #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
  33. #define I2S_TXCR_PBM_SHIFT 7
  34. #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
  35. #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
  36. #define I2S_TXCR_TFS_SHIFT 5
  37. #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
  38. #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
  39. #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
  40. #define I2S_TXCR_VDW_SHIFT 0
  41. #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
  42. #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
  43. /*
  44. * RXCR
  45. * receive operation control register
  46. */
  47. #define I2S_RXCR_CSR_SHIFT 15
  48. #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT)
  49. #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
  50. #define I2S_RXCR_HWT BIT(14)
  51. #define I2S_RXCR_SJM_SHIFT 12
  52. #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
  53. #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
  54. #define I2S_RXCR_FBM_SHIFT 11
  55. #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
  56. #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
  57. #define I2S_RXCR_IBM_SHIFT 9
  58. #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
  59. #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
  60. #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
  61. #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
  62. #define I2S_RXCR_PBM_SHIFT 7
  63. #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
  64. #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
  65. #define I2S_RXCR_TFS_SHIFT 5
  66. #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
  67. #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
  68. #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
  69. #define I2S_RXCR_VDW_SHIFT 0
  70. #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
  71. #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
  72. /*
  73. * CKR
  74. * clock generation register
  75. */
  76. #define I2S_CKR_TRCM_SHIFT 28
  77. #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT)
  78. #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT)
  79. #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT)
  80. #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT)
  81. #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT)
  82. #define I2S_CKR_MSS_SHIFT 27
  83. #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
  84. #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
  85. #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
  86. #define I2S_CKR_CKP_SHIFT 26
  87. #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
  88. #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
  89. #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
  90. #define I2S_CKR_RLP_SHIFT 25
  91. #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
  92. #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
  93. #define I2S_CKR_TLP_SHIFT 24
  94. #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
  95. #define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
  96. #define I2S_CKR_MDIV_SHIFT 16
  97. #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
  98. #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
  99. #define I2S_CKR_RSD_SHIFT 8
  100. #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
  101. #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
  102. #define I2S_CKR_TSD_SHIFT 0
  103. #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
  104. #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
  105. /*
  106. * FIFOLR
  107. * FIFO level register
  108. */
  109. #define I2S_FIFOLR_RFL_SHIFT 24
  110. #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
  111. #define I2S_FIFOLR_TFL3_SHIFT 18
  112. #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
  113. #define I2S_FIFOLR_TFL2_SHIFT 12
  114. #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
  115. #define I2S_FIFOLR_TFL1_SHIFT 6
  116. #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
  117. #define I2S_FIFOLR_TFL0_SHIFT 0
  118. #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
  119. /*
  120. * DMACR
  121. * DMA control register
  122. */
  123. #define I2S_DMACR_RDE_SHIFT 24
  124. #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
  125. #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
  126. #define I2S_DMACR_RDL_SHIFT 16
  127. #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
  128. #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
  129. #define I2S_DMACR_TDE_SHIFT 8
  130. #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
  131. #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
  132. #define I2S_DMACR_TDL_SHIFT 0
  133. #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
  134. #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
  135. /*
  136. * INTCR
  137. * interrupt control register
  138. */
  139. #define I2S_INTCR_RFT_SHIFT 20
  140. #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
  141. #define I2S_INTCR_RXOIC BIT(18)
  142. #define I2S_INTCR_RXOIE_SHIFT 17
  143. #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
  144. #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
  145. #define I2S_INTCR_RXFIE_SHIFT 16
  146. #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
  147. #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
  148. #define I2S_INTCR_TFT_SHIFT 4
  149. #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
  150. #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
  151. #define I2S_INTCR_TXUIC BIT(2)
  152. #define I2S_INTCR_TXUIE_SHIFT 1
  153. #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
  154. #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
  155. /*
  156. * INTSR
  157. * interrupt status register
  158. */
  159. #define I2S_INTSR_TXEIE_SHIFT 0
  160. #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
  161. #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
  162. #define I2S_INTSR_RXOI_SHIFT 17
  163. #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
  164. #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
  165. #define I2S_INTSR_RXFI_SHIFT 16
  166. #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
  167. #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
  168. #define I2S_INTSR_TXUI_SHIFT 1
  169. #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
  170. #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
  171. #define I2S_INTSR_TXEI_SHIFT 0
  172. #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
  173. #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
  174. /*
  175. * XFER
  176. * Transfer start register
  177. */
  178. #define I2S_XFER_RXS_SHIFT 1
  179. #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
  180. #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
  181. #define I2S_XFER_TXS_SHIFT 0
  182. #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
  183. #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
  184. /*
  185. * CLR
  186. * clear SCLK domain logic register
  187. */
  188. #define I2S_CLR_RXC BIT(1)
  189. #define I2S_CLR_TXC BIT(0)
  190. /*
  191. * TXDR
  192. * Transimt FIFO data register, write only.
  193. */
  194. #define I2S_TXDR_MASK (0xff)
  195. /*
  196. * RXDR
  197. * Receive FIFO data register, write only.
  198. */
  199. #define I2S_RXDR_MASK (0xff)
  200. /* Clock divider id */
  201. enum {
  202. ROCKCHIP_DIV_MCLK = 0,
  203. ROCKCHIP_DIV_BCLK,
  204. };
  205. /* channel select */
  206. #define I2S_CSR_SHIFT 15
  207. #define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
  208. #define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
  209. #define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
  210. #define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
  211. /* I2S REGS */
  212. #define I2S_TXCR (0x0000)
  213. #define I2S_RXCR (0x0004)
  214. #define I2S_CKR (0x0008)
  215. #define I2S_FIFOLR (0x000c)
  216. #define I2S_DMACR (0x0010)
  217. #define I2S_INTCR (0x0014)
  218. #define I2S_INTSR (0x0018)
  219. #define I2S_XFER (0x001c)
  220. #define I2S_CLR (0x0020)
  221. #define I2S_TXDR (0x0024)
  222. #define I2S_RXDR (0x0028)
  223. /* io direction cfg register */
  224. #define I2S_IO_DIRECTION_MASK (7)
  225. #define I2S_IO_8CH_OUT_2CH_IN (0)
  226. #define I2S_IO_6CH_OUT_4CH_IN (4)
  227. #define I2S_IO_4CH_OUT_6CH_IN (6)
  228. #define I2S_IO_2CH_OUT_8CH_IN (7)
  229. #endif /* _ROCKCHIP_IIS_H */