axg-toddr.c 11 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. /* This driver implements the frontend capture DAI of AXG based SoCs */
  6. #include <linux/clk.h>
  7. #include <linux/regmap.h>
  8. #include <linux/module.h>
  9. #include <linux/of_platform.h>
  10. #include <sound/pcm_params.h>
  11. #include <sound/soc.h>
  12. #include <sound/soc-dai.h>
  13. #include "axg-fifo.h"
  14. #define CTRL0_TODDR_SEL_RESAMPLE BIT(30)
  15. #define CTRL0_TODDR_EXT_SIGNED BIT(29)
  16. #define CTRL0_TODDR_PP_MODE BIT(28)
  17. #define CTRL0_TODDR_SYNC_CH BIT(27)
  18. #define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
  19. #define CTRL0_TODDR_TYPE(x) ((x) << 13)
  20. #define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
  21. #define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
  22. #define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
  23. #define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
  24. #define CTRL1_TODDR_FORCE_FINISH BIT(25)
  25. #define CTRL1_SEL_SHIFT 28
  26. #define TODDR_MSB_POS 31
  27. static int axg_toddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
  28. struct snd_soc_dai *dai)
  29. {
  30. return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_CAPTURE);
  31. }
  32. static int g12a_toddr_dai_prepare(struct snd_pcm_substream *substream,
  33. struct snd_soc_dai *dai)
  34. {
  35. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  36. /* Reset the write pointer to the FIFO_INIT_ADDR */
  37. regmap_update_bits(fifo->map, FIFO_CTRL1,
  38. CTRL1_TODDR_FORCE_FINISH, 0);
  39. regmap_update_bits(fifo->map, FIFO_CTRL1,
  40. CTRL1_TODDR_FORCE_FINISH, CTRL1_TODDR_FORCE_FINISH);
  41. regmap_update_bits(fifo->map, FIFO_CTRL1,
  42. CTRL1_TODDR_FORCE_FINISH, 0);
  43. return 0;
  44. }
  45. static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream,
  46. struct snd_pcm_hw_params *params,
  47. struct snd_soc_dai *dai)
  48. {
  49. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  50. unsigned int type, width;
  51. switch (params_physical_width(params)) {
  52. case 8:
  53. type = 0; /* 8 samples of 8 bits */
  54. break;
  55. case 16:
  56. type = 2; /* 4 samples of 16 bits - right justified */
  57. break;
  58. case 32:
  59. type = 4; /* 2 samples of 32 bits - right justified */
  60. break;
  61. default:
  62. return -EINVAL;
  63. }
  64. width = params_width(params);
  65. regmap_update_bits(fifo->map, FIFO_CTRL0,
  66. CTRL0_TODDR_TYPE_MASK |
  67. CTRL0_TODDR_MSB_POS_MASK |
  68. CTRL0_TODDR_LSB_POS_MASK,
  69. CTRL0_TODDR_TYPE(type) |
  70. CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
  71. CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
  72. return 0;
  73. }
  74. static int axg_toddr_dai_startup(struct snd_pcm_substream *substream,
  75. struct snd_soc_dai *dai)
  76. {
  77. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  78. int ret;
  79. /* Enable pclk to access registers and clock the fifo ip */
  80. ret = clk_prepare_enable(fifo->pclk);
  81. if (ret)
  82. return ret;
  83. /* Select orginal data - resampling not supported ATM */
  84. regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SEL_RESAMPLE, 0);
  85. /* Only signed format are supported ATM */
  86. regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_EXT_SIGNED,
  87. CTRL0_TODDR_EXT_SIGNED);
  88. /* Apply single buffer mode to the interface */
  89. regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0);
  90. return 0;
  91. }
  92. static void axg_toddr_dai_shutdown(struct snd_pcm_substream *substream,
  93. struct snd_soc_dai *dai)
  94. {
  95. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  96. clk_disable_unprepare(fifo->pclk);
  97. }
  98. static const struct snd_soc_dai_ops axg_toddr_ops = {
  99. .hw_params = axg_toddr_dai_hw_params,
  100. .startup = axg_toddr_dai_startup,
  101. .shutdown = axg_toddr_dai_shutdown,
  102. };
  103. static struct snd_soc_dai_driver axg_toddr_dai_drv = {
  104. .name = "TODDR",
  105. .capture = {
  106. .stream_name = "Capture",
  107. .channels_min = 1,
  108. .channels_max = AXG_FIFO_CH_MAX,
  109. .rates = AXG_FIFO_RATES,
  110. .formats = AXG_FIFO_FORMATS,
  111. },
  112. .ops = &axg_toddr_ops,
  113. .pcm_new = axg_toddr_pcm_new,
  114. };
  115. static const char * const axg_toddr_sel_texts[] = {
  116. "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7"
  117. };
  118. static SOC_ENUM_SINGLE_DECL(axg_toddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
  119. axg_toddr_sel_texts);
  120. static const struct snd_kcontrol_new axg_toddr_in_mux =
  121. SOC_DAPM_ENUM("Input Source", axg_toddr_sel_enum);
  122. static const struct snd_soc_dapm_widget axg_toddr_dapm_widgets[] = {
  123. SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_toddr_in_mux),
  124. SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
  125. SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  126. SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  127. SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  128. SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
  129. SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
  130. SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
  131. SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
  132. };
  133. static const struct snd_soc_dapm_route axg_toddr_dapm_routes[] = {
  134. { "Capture", NULL, "SRC SEL" },
  135. { "SRC SEL", "IN 0", "IN 0" },
  136. { "SRC SEL", "IN 1", "IN 1" },
  137. { "SRC SEL", "IN 2", "IN 2" },
  138. { "SRC SEL", "IN 3", "IN 3" },
  139. { "SRC SEL", "IN 4", "IN 4" },
  140. { "SRC SEL", "IN 5", "IN 5" },
  141. { "SRC SEL", "IN 6", "IN 6" },
  142. { "SRC SEL", "IN 7", "IN 7" },
  143. };
  144. static const struct snd_soc_component_driver axg_toddr_component_drv = {
  145. .dapm_widgets = axg_toddr_dapm_widgets,
  146. .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
  147. .dapm_routes = axg_toddr_dapm_routes,
  148. .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
  149. .open = axg_fifo_pcm_open,
  150. .close = axg_fifo_pcm_close,
  151. .hw_params = axg_fifo_pcm_hw_params,
  152. .hw_free = axg_fifo_pcm_hw_free,
  153. .pointer = axg_fifo_pcm_pointer,
  154. .trigger = axg_fifo_pcm_trigger,
  155. };
  156. static const struct axg_fifo_match_data axg_toddr_match_data = {
  157. .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
  158. .component_drv = &axg_toddr_component_drv,
  159. .dai_drv = &axg_toddr_dai_drv
  160. };
  161. static int g12a_toddr_dai_startup(struct snd_pcm_substream *substream,
  162. struct snd_soc_dai *dai)
  163. {
  164. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  165. int ret;
  166. ret = axg_toddr_dai_startup(substream, dai);
  167. if (ret)
  168. return ret;
  169. /*
  170. * Make sure the first channel ends up in the at beginning of the output
  171. * As weird as it looks, without this the first channel may be misplaced
  172. * in memory, with a random shift of 2 channels.
  173. */
  174. regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SYNC_CH,
  175. CTRL0_TODDR_SYNC_CH);
  176. return 0;
  177. }
  178. static const struct snd_soc_dai_ops g12a_toddr_ops = {
  179. .prepare = g12a_toddr_dai_prepare,
  180. .hw_params = axg_toddr_dai_hw_params,
  181. .startup = g12a_toddr_dai_startup,
  182. .shutdown = axg_toddr_dai_shutdown,
  183. };
  184. static struct snd_soc_dai_driver g12a_toddr_dai_drv = {
  185. .name = "TODDR",
  186. .capture = {
  187. .stream_name = "Capture",
  188. .channels_min = 1,
  189. .channels_max = AXG_FIFO_CH_MAX,
  190. .rates = AXG_FIFO_RATES,
  191. .formats = AXG_FIFO_FORMATS,
  192. },
  193. .ops = &g12a_toddr_ops,
  194. .pcm_new = axg_toddr_pcm_new,
  195. };
  196. static const struct snd_soc_component_driver g12a_toddr_component_drv = {
  197. .dapm_widgets = axg_toddr_dapm_widgets,
  198. .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
  199. .dapm_routes = axg_toddr_dapm_routes,
  200. .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
  201. .open = axg_fifo_pcm_open,
  202. .close = axg_fifo_pcm_close,
  203. .hw_params = g12a_fifo_pcm_hw_params,
  204. .hw_free = axg_fifo_pcm_hw_free,
  205. .pointer = axg_fifo_pcm_pointer,
  206. .trigger = axg_fifo_pcm_trigger,
  207. };
  208. static const struct axg_fifo_match_data g12a_toddr_match_data = {
  209. .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
  210. .component_drv = &g12a_toddr_component_drv,
  211. .dai_drv = &g12a_toddr_dai_drv
  212. };
  213. static const char * const sm1_toddr_sel_texts[] = {
  214. "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7",
  215. "IN 8", "IN 9", "IN 10", "IN 11", "IN 12", "IN 13", "IN 14", "IN 15"
  216. };
  217. static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT,
  218. sm1_toddr_sel_texts);
  219. static const struct snd_kcontrol_new sm1_toddr_in_mux =
  220. SOC_DAPM_ENUM("Input Source", sm1_toddr_sel_enum);
  221. static const struct snd_soc_dapm_widget sm1_toddr_dapm_widgets[] = {
  222. SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &sm1_toddr_in_mux),
  223. SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
  224. SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  225. SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  226. SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  227. SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
  228. SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
  229. SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
  230. SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
  231. SND_SOC_DAPM_AIF_IN("IN 8", NULL, 0, SND_SOC_NOPM, 0, 0),
  232. SND_SOC_DAPM_AIF_IN("IN 9", NULL, 0, SND_SOC_NOPM, 0, 0),
  233. SND_SOC_DAPM_AIF_IN("IN 10", NULL, 0, SND_SOC_NOPM, 0, 0),
  234. SND_SOC_DAPM_AIF_IN("IN 11", NULL, 0, SND_SOC_NOPM, 0, 0),
  235. SND_SOC_DAPM_AIF_IN("IN 12", NULL, 0, SND_SOC_NOPM, 0, 0),
  236. SND_SOC_DAPM_AIF_IN("IN 13", NULL, 0, SND_SOC_NOPM, 0, 0),
  237. SND_SOC_DAPM_AIF_IN("IN 14", NULL, 0, SND_SOC_NOPM, 0, 0),
  238. SND_SOC_DAPM_AIF_IN("IN 15", NULL, 0, SND_SOC_NOPM, 0, 0),
  239. };
  240. static const struct snd_soc_dapm_route sm1_toddr_dapm_routes[] = {
  241. { "Capture", NULL, "SRC SEL" },
  242. { "SRC SEL", "IN 0", "IN 0" },
  243. { "SRC SEL", "IN 1", "IN 1" },
  244. { "SRC SEL", "IN 2", "IN 2" },
  245. { "SRC SEL", "IN 3", "IN 3" },
  246. { "SRC SEL", "IN 4", "IN 4" },
  247. { "SRC SEL", "IN 5", "IN 5" },
  248. { "SRC SEL", "IN 6", "IN 6" },
  249. { "SRC SEL", "IN 7", "IN 7" },
  250. { "SRC SEL", "IN 8", "IN 8" },
  251. { "SRC SEL", "IN 9", "IN 9" },
  252. { "SRC SEL", "IN 10", "IN 10" },
  253. { "SRC SEL", "IN 11", "IN 11" },
  254. { "SRC SEL", "IN 12", "IN 12" },
  255. { "SRC SEL", "IN 13", "IN 13" },
  256. { "SRC SEL", "IN 14", "IN 14" },
  257. { "SRC SEL", "IN 15", "IN 15" },
  258. };
  259. static const struct snd_soc_component_driver sm1_toddr_component_drv = {
  260. .dapm_widgets = sm1_toddr_dapm_widgets,
  261. .num_dapm_widgets = ARRAY_SIZE(sm1_toddr_dapm_widgets),
  262. .dapm_routes = sm1_toddr_dapm_routes,
  263. .num_dapm_routes = ARRAY_SIZE(sm1_toddr_dapm_routes),
  264. .open = axg_fifo_pcm_open,
  265. .close = axg_fifo_pcm_close,
  266. .hw_params = g12a_fifo_pcm_hw_params,
  267. .hw_free = axg_fifo_pcm_hw_free,
  268. .pointer = axg_fifo_pcm_pointer,
  269. .trigger = axg_fifo_pcm_trigger,
  270. };
  271. static const struct axg_fifo_match_data sm1_toddr_match_data = {
  272. .field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23),
  273. .component_drv = &sm1_toddr_component_drv,
  274. .dai_drv = &g12a_toddr_dai_drv
  275. };
  276. static const struct of_device_id axg_toddr_of_match[] = {
  277. {
  278. .compatible = "amlogic,axg-toddr",
  279. .data = &axg_toddr_match_data,
  280. }, {
  281. .compatible = "amlogic,g12a-toddr",
  282. .data = &g12a_toddr_match_data,
  283. }, {
  284. .compatible = "amlogic,sm1-toddr",
  285. .data = &sm1_toddr_match_data,
  286. }, {}
  287. };
  288. MODULE_DEVICE_TABLE(of, axg_toddr_of_match);
  289. static struct platform_driver axg_toddr_pdrv = {
  290. .probe = axg_fifo_probe,
  291. .driver = {
  292. .name = "axg-toddr",
  293. .of_match_table = axg_toddr_of_match,
  294. },
  295. };
  296. module_platform_driver(axg_toddr_pdrv);
  297. MODULE_DESCRIPTION("Amlogic AXG capture fifo driver");
  298. MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
  299. MODULE_LICENSE("GPL v2");