axg-tdm-interface.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. #include <linux/clk.h>
  6. #include <linux/module.h>
  7. #include <linux/of_platform.h>
  8. #include <sound/pcm_params.h>
  9. #include <sound/soc.h>
  10. #include <sound/soc-dai.h>
  11. #include "axg-tdm.h"
  12. enum {
  13. TDM_IFACE_PAD,
  14. TDM_IFACE_LOOPBACK,
  15. };
  16. static unsigned int axg_tdm_slots_total(u32 *mask)
  17. {
  18. unsigned int slots = 0;
  19. int i;
  20. if (!mask)
  21. return 0;
  22. /* Count the total number of slots provided by all 4 lanes */
  23. for (i = 0; i < AXG_TDM_NUM_LANES; i++)
  24. slots += hweight32(mask[i]);
  25. return slots;
  26. }
  27. int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
  28. u32 *rx_mask, unsigned int slots,
  29. unsigned int slot_width)
  30. {
  31. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  32. struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
  33. dai->playback_dma_data;
  34. struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
  35. dai->capture_dma_data;
  36. unsigned int tx_slots, rx_slots;
  37. unsigned int fmt = 0;
  38. tx_slots = axg_tdm_slots_total(tx_mask);
  39. rx_slots = axg_tdm_slots_total(rx_mask);
  40. /* We should at least have a slot for a valid interface */
  41. if (!tx_slots && !rx_slots) {
  42. dev_err(dai->dev, "interface has no slot\n");
  43. return -EINVAL;
  44. }
  45. iface->slots = slots;
  46. switch (slot_width) {
  47. case 0:
  48. slot_width = 32;
  49. fallthrough;
  50. case 32:
  51. fmt |= SNDRV_PCM_FMTBIT_S32_LE;
  52. fallthrough;
  53. case 24:
  54. fmt |= SNDRV_PCM_FMTBIT_S24_LE;
  55. fmt |= SNDRV_PCM_FMTBIT_S20_LE;
  56. fallthrough;
  57. case 16:
  58. fmt |= SNDRV_PCM_FMTBIT_S16_LE;
  59. fallthrough;
  60. case 8:
  61. fmt |= SNDRV_PCM_FMTBIT_S8;
  62. break;
  63. default:
  64. dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
  65. return -EINVAL;
  66. }
  67. iface->slot_width = slot_width;
  68. /* Amend the dai driver and let dpcm merge do its job */
  69. if (tx) {
  70. tx->mask = tx_mask;
  71. dai->driver->playback.channels_max = tx_slots;
  72. dai->driver->playback.formats = fmt;
  73. }
  74. if (rx) {
  75. rx->mask = rx_mask;
  76. dai->driver->capture.channels_max = rx_slots;
  77. dai->driver->capture.formats = fmt;
  78. }
  79. return 0;
  80. }
  81. EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
  82. static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  83. unsigned int freq, int dir)
  84. {
  85. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  86. int ret = -ENOTSUPP;
  87. if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
  88. if (!iface->mclk) {
  89. dev_warn(dai->dev, "master clock not provided\n");
  90. } else {
  91. ret = clk_set_rate(iface->mclk, freq);
  92. if (!ret)
  93. iface->mclk_rate = freq;
  94. }
  95. }
  96. return ret;
  97. }
  98. static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  99. {
  100. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  101. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  102. case SND_SOC_DAIFMT_CBS_CFS:
  103. if (!iface->mclk) {
  104. dev_err(dai->dev, "cpu clock master: mclk missing\n");
  105. return -ENODEV;
  106. }
  107. break;
  108. case SND_SOC_DAIFMT_CBM_CFM:
  109. break;
  110. case SND_SOC_DAIFMT_CBS_CFM:
  111. case SND_SOC_DAIFMT_CBM_CFS:
  112. dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
  113. fallthrough;
  114. default:
  115. return -EINVAL;
  116. }
  117. iface->fmt = fmt;
  118. return 0;
  119. }
  120. static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
  121. struct snd_soc_dai *dai)
  122. {
  123. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  124. struct axg_tdm_stream *ts =
  125. snd_soc_dai_get_dma_data(dai, substream);
  126. int ret;
  127. if (!axg_tdm_slots_total(ts->mask)) {
  128. dev_err(dai->dev, "interface has not slots\n");
  129. return -EINVAL;
  130. }
  131. /* Apply component wide rate symmetry */
  132. if (snd_soc_component_active(dai->component)) {
  133. ret = snd_pcm_hw_constraint_single(substream->runtime,
  134. SNDRV_PCM_HW_PARAM_RATE,
  135. iface->rate);
  136. if (ret < 0) {
  137. dev_err(dai->dev,
  138. "can't set iface rate constraint\n");
  139. return ret;
  140. }
  141. }
  142. return 0;
  143. }
  144. static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
  145. struct snd_pcm_hw_params *params,
  146. struct snd_soc_dai *dai)
  147. {
  148. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  149. struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
  150. unsigned int channels = params_channels(params);
  151. unsigned int width = params_width(params);
  152. /* Save rate and sample_bits for component symmetry */
  153. iface->rate = params_rate(params);
  154. /* Make sure this interface can cope with the stream */
  155. if (axg_tdm_slots_total(ts->mask) < channels) {
  156. dev_err(dai->dev, "not enough slots for channels\n");
  157. return -EINVAL;
  158. }
  159. if (iface->slot_width < width) {
  160. dev_err(dai->dev, "incompatible slots width for stream\n");
  161. return -EINVAL;
  162. }
  163. /* Save the parameter for tdmout/tdmin widgets */
  164. ts->physical_width = params_physical_width(params);
  165. ts->width = params_width(params);
  166. ts->channels = params_channels(params);
  167. return 0;
  168. }
  169. static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
  170. struct snd_pcm_hw_params *params)
  171. {
  172. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  173. unsigned int ratio_num;
  174. int ret;
  175. ret = clk_set_rate(iface->lrclk, params_rate(params));
  176. if (ret) {
  177. dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
  178. return ret;
  179. }
  180. switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  181. case SND_SOC_DAIFMT_I2S:
  182. case SND_SOC_DAIFMT_LEFT_J:
  183. case SND_SOC_DAIFMT_RIGHT_J:
  184. /* 50% duty cycle ratio */
  185. ratio_num = 1;
  186. break;
  187. case SND_SOC_DAIFMT_DSP_A:
  188. case SND_SOC_DAIFMT_DSP_B:
  189. /*
  190. * A zero duty cycle ratio will result in setting the mininum
  191. * ratio possible which, for this clock, is 1 cycle of the
  192. * parent bclk clock high and the rest low, This is exactly
  193. * what we want here.
  194. */
  195. ratio_num = 0;
  196. break;
  197. default:
  198. return -EINVAL;
  199. }
  200. ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
  201. if (ret) {
  202. dev_err(dai->dev,
  203. "setting sample clock duty cycle failed: %d\n", ret);
  204. return ret;
  205. }
  206. /* Set sample clock inversion */
  207. ret = clk_set_phase(iface->lrclk,
  208. axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
  209. if (ret) {
  210. dev_err(dai->dev,
  211. "setting sample clock phase failed: %d\n", ret);
  212. return ret;
  213. }
  214. return 0;
  215. }
  216. static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
  217. struct snd_pcm_hw_params *params)
  218. {
  219. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  220. unsigned long srate;
  221. int ret;
  222. srate = iface->slots * iface->slot_width * params_rate(params);
  223. if (!iface->mclk_rate) {
  224. /* If no specific mclk is requested, default to bit clock * 4 */
  225. clk_set_rate(iface->mclk, 4 * srate);
  226. } else {
  227. /* Check if we can actually get the bit clock from mclk */
  228. if (iface->mclk_rate % srate) {
  229. dev_err(dai->dev,
  230. "can't derive sclk %lu from mclk %lu\n",
  231. srate, iface->mclk_rate);
  232. return -EINVAL;
  233. }
  234. }
  235. ret = clk_set_rate(iface->sclk, srate);
  236. if (ret) {
  237. dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
  238. return ret;
  239. }
  240. /* Set the bit clock inversion */
  241. ret = clk_set_phase(iface->sclk,
  242. axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
  243. if (ret) {
  244. dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
  245. return ret;
  246. }
  247. return ret;
  248. }
  249. static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
  250. struct snd_pcm_hw_params *params,
  251. struct snd_soc_dai *dai)
  252. {
  253. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  254. int ret;
  255. switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  256. case SND_SOC_DAIFMT_I2S:
  257. case SND_SOC_DAIFMT_LEFT_J:
  258. case SND_SOC_DAIFMT_RIGHT_J:
  259. if (iface->slots > 2) {
  260. dev_err(dai->dev, "bad slot number for format: %d\n",
  261. iface->slots);
  262. return -EINVAL;
  263. }
  264. break;
  265. case SND_SOC_DAIFMT_DSP_A:
  266. case SND_SOC_DAIFMT_DSP_B:
  267. break;
  268. default:
  269. dev_err(dai->dev, "unsupported dai format\n");
  270. return -EINVAL;
  271. }
  272. ret = axg_tdm_iface_set_stream(substream, params, dai);
  273. if (ret)
  274. return ret;
  275. if ((iface->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
  276. SND_SOC_DAIFMT_CBS_CFS) {
  277. ret = axg_tdm_iface_set_sclk(dai, params);
  278. if (ret)
  279. return ret;
  280. ret = axg_tdm_iface_set_lrclk(dai, params);
  281. if (ret)
  282. return ret;
  283. }
  284. return 0;
  285. }
  286. static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
  287. struct snd_soc_dai *dai)
  288. {
  289. struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
  290. /* Stop all attached formatters */
  291. axg_tdm_stream_stop(ts);
  292. return 0;
  293. }
  294. static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
  295. struct snd_soc_dai *dai)
  296. {
  297. struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
  298. /* Force all attached formatters to update */
  299. return axg_tdm_stream_reset(ts);
  300. }
  301. static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
  302. {
  303. if (dai->capture_dma_data)
  304. axg_tdm_stream_free(dai->capture_dma_data);
  305. if (dai->playback_dma_data)
  306. axg_tdm_stream_free(dai->playback_dma_data);
  307. return 0;
  308. }
  309. static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
  310. {
  311. struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
  312. if (dai->capture_widget) {
  313. dai->capture_dma_data = axg_tdm_stream_alloc(iface);
  314. if (!dai->capture_dma_data)
  315. return -ENOMEM;
  316. }
  317. if (dai->playback_widget) {
  318. dai->playback_dma_data = axg_tdm_stream_alloc(iface);
  319. if (!dai->playback_dma_data) {
  320. axg_tdm_iface_remove_dai(dai);
  321. return -ENOMEM;
  322. }
  323. }
  324. return 0;
  325. }
  326. static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
  327. .set_sysclk = axg_tdm_iface_set_sysclk,
  328. .set_fmt = axg_tdm_iface_set_fmt,
  329. .startup = axg_tdm_iface_startup,
  330. .hw_params = axg_tdm_iface_hw_params,
  331. .prepare = axg_tdm_iface_prepare,
  332. .hw_free = axg_tdm_iface_hw_free,
  333. };
  334. /* TDM Backend DAIs */
  335. static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
  336. [TDM_IFACE_PAD] = {
  337. .name = "TDM Pad",
  338. .playback = {
  339. .stream_name = "Playback",
  340. .channels_min = 1,
  341. .channels_max = AXG_TDM_CHANNEL_MAX,
  342. .rates = AXG_TDM_RATES,
  343. .formats = AXG_TDM_FORMATS,
  344. },
  345. .capture = {
  346. .stream_name = "Capture",
  347. .channels_min = 1,
  348. .channels_max = AXG_TDM_CHANNEL_MAX,
  349. .rates = AXG_TDM_RATES,
  350. .formats = AXG_TDM_FORMATS,
  351. },
  352. .id = TDM_IFACE_PAD,
  353. .ops = &axg_tdm_iface_ops,
  354. .probe = axg_tdm_iface_probe_dai,
  355. .remove = axg_tdm_iface_remove_dai,
  356. },
  357. [TDM_IFACE_LOOPBACK] = {
  358. .name = "TDM Loopback",
  359. .capture = {
  360. .stream_name = "Loopback",
  361. .channels_min = 1,
  362. .channels_max = AXG_TDM_CHANNEL_MAX,
  363. .rates = AXG_TDM_RATES,
  364. .formats = AXG_TDM_FORMATS,
  365. },
  366. .id = TDM_IFACE_LOOPBACK,
  367. .ops = &axg_tdm_iface_ops,
  368. .probe = axg_tdm_iface_probe_dai,
  369. .remove = axg_tdm_iface_remove_dai,
  370. },
  371. };
  372. static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
  373. enum snd_soc_bias_level level)
  374. {
  375. struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
  376. enum snd_soc_bias_level now =
  377. snd_soc_component_get_bias_level(component);
  378. int ret = 0;
  379. switch (level) {
  380. case SND_SOC_BIAS_PREPARE:
  381. if (now == SND_SOC_BIAS_STANDBY)
  382. ret = clk_prepare_enable(iface->mclk);
  383. break;
  384. case SND_SOC_BIAS_STANDBY:
  385. if (now == SND_SOC_BIAS_PREPARE)
  386. clk_disable_unprepare(iface->mclk);
  387. break;
  388. case SND_SOC_BIAS_OFF:
  389. case SND_SOC_BIAS_ON:
  390. break;
  391. }
  392. return ret;
  393. }
  394. static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
  395. SND_SOC_DAPM_SIGGEN("Playback Signal"),
  396. };
  397. static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
  398. { "Loopback", NULL, "Playback Signal" },
  399. };
  400. static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
  401. .dapm_widgets = axg_tdm_iface_dapm_widgets,
  402. .num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
  403. .dapm_routes = axg_tdm_iface_dapm_routes,
  404. .num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
  405. .set_bias_level = axg_tdm_iface_set_bias_level,
  406. };
  407. static const struct of_device_id axg_tdm_iface_of_match[] = {
  408. { .compatible = "amlogic,axg-tdm-iface", },
  409. {}
  410. };
  411. MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
  412. static int axg_tdm_iface_probe(struct platform_device *pdev)
  413. {
  414. struct device *dev = &pdev->dev;
  415. struct snd_soc_dai_driver *dai_drv;
  416. struct axg_tdm_iface *iface;
  417. int ret, i;
  418. iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
  419. if (!iface)
  420. return -ENOMEM;
  421. platform_set_drvdata(pdev, iface);
  422. /*
  423. * Duplicate dai driver: depending on the slot masks configuration
  424. * We'll change the number of channel provided by DAI stream, so dpcm
  425. * channel merge can be done properly
  426. */
  427. dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
  428. sizeof(*dai_drv), GFP_KERNEL);
  429. if (!dai_drv)
  430. return -ENOMEM;
  431. for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
  432. memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
  433. sizeof(*dai_drv));
  434. /* Bit clock provided on the pad */
  435. iface->sclk = devm_clk_get(dev, "sclk");
  436. if (IS_ERR(iface->sclk)) {
  437. ret = PTR_ERR(iface->sclk);
  438. if (ret != -EPROBE_DEFER)
  439. dev_err(dev, "failed to get sclk: %d\n", ret);
  440. return ret;
  441. }
  442. /* Sample clock provided on the pad */
  443. iface->lrclk = devm_clk_get(dev, "lrclk");
  444. if (IS_ERR(iface->lrclk)) {
  445. ret = PTR_ERR(iface->lrclk);
  446. if (ret != -EPROBE_DEFER)
  447. dev_err(dev, "failed to get lrclk: %d\n", ret);
  448. return ret;
  449. }
  450. /*
  451. * mclk maybe be missing when the cpu dai is in slave mode and
  452. * the codec does not require it to provide a master clock.
  453. * At this point, ignore the error if mclk is missing. We'll
  454. * throw an error if the cpu dai is master and mclk is missing
  455. */
  456. iface->mclk = devm_clk_get(dev, "mclk");
  457. if (IS_ERR(iface->mclk)) {
  458. ret = PTR_ERR(iface->mclk);
  459. if (ret == -ENOENT) {
  460. iface->mclk = NULL;
  461. } else {
  462. if (ret != -EPROBE_DEFER)
  463. dev_err(dev, "failed to get mclk: %d\n", ret);
  464. return ret;
  465. }
  466. }
  467. return devm_snd_soc_register_component(dev,
  468. &axg_tdm_iface_component_drv, dai_drv,
  469. ARRAY_SIZE(axg_tdm_iface_dai_drv));
  470. }
  471. static struct platform_driver axg_tdm_iface_pdrv = {
  472. .probe = axg_tdm_iface_probe,
  473. .driver = {
  474. .name = "axg-tdm-iface",
  475. .of_match_table = axg_tdm_iface_of_match,
  476. },
  477. };
  478. module_platform_driver(axg_tdm_iface_pdrv);
  479. MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
  480. MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
  481. MODULE_LICENSE("GPL v2");