axg-spdifin.c 13 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. #include <linux/bitfield.h>
  6. #include <linux/clk.h>
  7. #include <linux/module.h>
  8. #include <linux/of_platform.h>
  9. #include <linux/regmap.h>
  10. #include <sound/soc.h>
  11. #include <sound/soc-dai.h>
  12. #include <sound/pcm_params.h>
  13. #define SPDIFIN_CTRL0 0x00
  14. #define SPDIFIN_CTRL0_EN BIT(31)
  15. #define SPDIFIN_CTRL0_RST_OUT BIT(29)
  16. #define SPDIFIN_CTRL0_RST_IN BIT(28)
  17. #define SPDIFIN_CTRL0_WIDTH_SEL BIT(24)
  18. #define SPDIFIN_CTRL0_STATUS_CH_SHIFT 11
  19. #define SPDIFIN_CTRL0_STATUS_SEL GENMASK(10, 8)
  20. #define SPDIFIN_CTRL0_SRC_SEL GENMASK(5, 4)
  21. #define SPDIFIN_CTRL0_CHK_VALID BIT(3)
  22. #define SPDIFIN_CTRL1 0x04
  23. #define SPDIFIN_CTRL1_BASE_TIMER GENMASK(19, 0)
  24. #define SPDIFIN_CTRL1_IRQ_MASK GENMASK(27, 20)
  25. #define SPDIFIN_CTRL2 0x08
  26. #define SPDIFIN_THRES_PER_REG 3
  27. #define SPDIFIN_THRES_WIDTH 10
  28. #define SPDIFIN_CTRL3 0x0c
  29. #define SPDIFIN_CTRL4 0x10
  30. #define SPDIFIN_TIMER_PER_REG 4
  31. #define SPDIFIN_TIMER_WIDTH 8
  32. #define SPDIFIN_CTRL5 0x14
  33. #define SPDIFIN_CTRL6 0x18
  34. #define SPDIFIN_STAT0 0x1c
  35. #define SPDIFIN_STAT0_MODE GENMASK(30, 28)
  36. #define SPDIFIN_STAT0_MAXW GENMASK(17, 8)
  37. #define SPDIFIN_STAT0_IRQ GENMASK(7, 0)
  38. #define SPDIFIN_IRQ_MODE_CHANGED BIT(2)
  39. #define SPDIFIN_STAT1 0x20
  40. #define SPDIFIN_STAT2 0x24
  41. #define SPDIFIN_MUTE_VAL 0x28
  42. #define SPDIFIN_MODE_NUM 7
  43. struct axg_spdifin_cfg {
  44. const unsigned int *mode_rates;
  45. unsigned int ref_rate;
  46. };
  47. struct axg_spdifin {
  48. const struct axg_spdifin_cfg *conf;
  49. struct regmap *map;
  50. struct clk *refclk;
  51. struct clk *pclk;
  52. };
  53. /*
  54. * TODO:
  55. * It would have been nice to check the actual rate against the sample rate
  56. * requested in hw_params(). Unfortunately, I was not able to make the mode
  57. * detection and IRQ work reliably:
  58. *
  59. * 1. IRQs are generated on mode change only, so there is no notification
  60. * on transition between no signal and mode 0 (32kHz).
  61. * 2. Mode detection very often has glitches, and may detects the
  62. * lowest or the highest mode before zeroing in on the actual mode.
  63. *
  64. * This makes calling snd_pcm_stop() difficult to get right. Even notifying
  65. * the kcontrol would be very unreliable at this point.
  66. * Let's keep things simple until the magic spell that makes this work is
  67. * found.
  68. */
  69. static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
  70. {
  71. unsigned int stat, mode, rate = 0;
  72. regmap_read(priv->map, SPDIFIN_STAT0, &stat);
  73. mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
  74. /*
  75. * If max width is zero, we are not capturing anything.
  76. * Also Sometimes, when the capture is on but there is no data,
  77. * mode is SPDIFIN_MODE_NUM, but not always ...
  78. */
  79. if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
  80. mode < SPDIFIN_MODE_NUM)
  81. rate = priv->conf->mode_rates[mode];
  82. return rate;
  83. }
  84. static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
  85. struct snd_soc_dai *dai)
  86. {
  87. struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
  88. /* Apply both reset */
  89. regmap_update_bits(priv->map, SPDIFIN_CTRL0,
  90. SPDIFIN_CTRL0_RST_OUT |
  91. SPDIFIN_CTRL0_RST_IN,
  92. 0);
  93. /* Clear out reset before in reset */
  94. regmap_update_bits(priv->map, SPDIFIN_CTRL0,
  95. SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
  96. regmap_update_bits(priv->map, SPDIFIN_CTRL0,
  97. SPDIFIN_CTRL0_RST_IN, SPDIFIN_CTRL0_RST_IN);
  98. return 0;
  99. }
  100. static int axg_spdifin_startup(struct snd_pcm_substream *substream,
  101. struct snd_soc_dai *dai)
  102. {
  103. struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
  104. int ret;
  105. ret = clk_prepare_enable(priv->refclk);
  106. if (ret) {
  107. dev_err(dai->dev,
  108. "failed to enable spdifin reference clock\n");
  109. return ret;
  110. }
  111. regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
  112. SPDIFIN_CTRL0_EN);
  113. return 0;
  114. }
  115. static void axg_spdifin_shutdown(struct snd_pcm_substream *substream,
  116. struct snd_soc_dai *dai)
  117. {
  118. struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
  119. regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
  120. clk_disable_unprepare(priv->refclk);
  121. }
  122. static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
  123. unsigned int val,
  124. unsigned int num_per_reg,
  125. unsigned int base_reg,
  126. unsigned int width)
  127. {
  128. uint64_t offset = mode;
  129. unsigned int reg, shift, rem;
  130. rem = do_div(offset, num_per_reg);
  131. reg = offset * regmap_get_reg_stride(map) + base_reg;
  132. shift = width * (num_per_reg - 1 - rem);
  133. regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
  134. val << shift);
  135. }
  136. static void axg_spdifin_write_timer(struct regmap *map, int mode,
  137. unsigned int val)
  138. {
  139. axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG,
  140. SPDIFIN_CTRL4, SPDIFIN_TIMER_WIDTH);
  141. }
  142. static void axg_spdifin_write_threshold(struct regmap *map, int mode,
  143. unsigned int val)
  144. {
  145. axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG,
  146. SPDIFIN_CTRL2, SPDIFIN_THRES_WIDTH);
  147. }
  148. static unsigned int axg_spdifin_mode_timer(struct axg_spdifin *priv,
  149. int mode,
  150. unsigned int rate)
  151. {
  152. /*
  153. * Number of period of the reference clock during a period of the
  154. * input signal reference clock
  155. */
  156. return rate / (128 * priv->conf->mode_rates[mode]);
  157. }
  158. static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
  159. struct axg_spdifin *priv)
  160. {
  161. unsigned int rate, t_next;
  162. int ret, i = SPDIFIN_MODE_NUM - 1;
  163. /* Set spdif input reference clock */
  164. ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
  165. if (ret) {
  166. dev_err(dai->dev, "reference clock rate set failed\n");
  167. return ret;
  168. }
  169. /*
  170. * The rate actually set might be slightly different, get
  171. * the actual rate for the following mode calculation
  172. */
  173. rate = clk_get_rate(priv->refclk);
  174. /* HW will update mode every 1ms */
  175. regmap_update_bits(priv->map, SPDIFIN_CTRL1,
  176. SPDIFIN_CTRL1_BASE_TIMER,
  177. FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
  178. /* Threshold based on the minimum width between two edges */
  179. regmap_update_bits(priv->map, SPDIFIN_CTRL0,
  180. SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
  181. /* Calculate the last timer which has no threshold */
  182. t_next = axg_spdifin_mode_timer(priv, i, rate);
  183. axg_spdifin_write_timer(priv->map, i, t_next);
  184. do {
  185. unsigned int t;
  186. i -= 1;
  187. /* Calculate the timer */
  188. t = axg_spdifin_mode_timer(priv, i, rate);
  189. /* Set the timer value */
  190. axg_spdifin_write_timer(priv->map, i, t);
  191. /* Set the threshold value */
  192. axg_spdifin_write_threshold(priv->map, i, t + t_next);
  193. /* Save the current timer for the next threshold calculation */
  194. t_next = t;
  195. } while (i > 0);
  196. return 0;
  197. }
  198. static int axg_spdifin_dai_probe(struct snd_soc_dai *dai)
  199. {
  200. struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
  201. int ret;
  202. ret = clk_prepare_enable(priv->pclk);
  203. if (ret) {
  204. dev_err(dai->dev, "failed to enable pclk\n");
  205. return ret;
  206. }
  207. ret = axg_spdifin_sample_mode_config(dai, priv);
  208. if (ret) {
  209. dev_err(dai->dev, "mode configuration failed\n");
  210. clk_disable_unprepare(priv->pclk);
  211. return ret;
  212. }
  213. return 0;
  214. }
  215. static int axg_spdifin_dai_remove(struct snd_soc_dai *dai)
  216. {
  217. struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
  218. clk_disable_unprepare(priv->pclk);
  219. return 0;
  220. }
  221. static const struct snd_soc_dai_ops axg_spdifin_ops = {
  222. .prepare = axg_spdifin_prepare,
  223. .startup = axg_spdifin_startup,
  224. .shutdown = axg_spdifin_shutdown,
  225. };
  226. static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
  227. struct snd_ctl_elem_info *uinfo)
  228. {
  229. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  230. uinfo->count = 1;
  231. return 0;
  232. }
  233. static int axg_spdifin_get_status_mask(struct snd_kcontrol *kcontrol,
  234. struct snd_ctl_elem_value *ucontrol)
  235. {
  236. int i;
  237. for (i = 0; i < 24; i++)
  238. ucontrol->value.iec958.status[i] = 0xff;
  239. return 0;
  240. }
  241. static int axg_spdifin_get_status(struct snd_kcontrol *kcontrol,
  242. struct snd_ctl_elem_value *ucontrol)
  243. {
  244. struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
  245. struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
  246. int i, j;
  247. for (i = 0; i < 6; i++) {
  248. unsigned int val;
  249. regmap_update_bits(priv->map, SPDIFIN_CTRL0,
  250. SPDIFIN_CTRL0_STATUS_SEL,
  251. FIELD_PREP(SPDIFIN_CTRL0_STATUS_SEL, i));
  252. regmap_read(priv->map, SPDIFIN_STAT1, &val);
  253. for (j = 0; j < 4; j++) {
  254. unsigned int offset = i * 4 + j;
  255. ucontrol->value.iec958.status[offset] =
  256. (val >> (j * 8)) & 0xff;
  257. }
  258. }
  259. return 0;
  260. }
  261. #define AXG_SPDIFIN_IEC958_MASK \
  262. { \
  263. .access = SNDRV_CTL_ELEM_ACCESS_READ, \
  264. .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
  265. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), \
  266. .info = axg_spdifin_iec958_info, \
  267. .get = axg_spdifin_get_status_mask, \
  268. }
  269. #define AXG_SPDIFIN_IEC958_STATUS \
  270. { \
  271. .access = (SNDRV_CTL_ELEM_ACCESS_READ | \
  272. SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
  273. .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
  274. .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE), \
  275. .info = axg_spdifin_iec958_info, \
  276. .get = axg_spdifin_get_status, \
  277. }
  278. static const char * const spdifin_chsts_src_texts[] = {
  279. "A", "B",
  280. };
  281. static SOC_ENUM_SINGLE_DECL(axg_spdifin_chsts_src_enum, SPDIFIN_CTRL0,
  282. SPDIFIN_CTRL0_STATUS_CH_SHIFT,
  283. spdifin_chsts_src_texts);
  284. static int axg_spdifin_rate_lock_info(struct snd_kcontrol *kcontrol,
  285. struct snd_ctl_elem_info *uinfo)
  286. {
  287. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  288. uinfo->count = 1;
  289. uinfo->value.integer.min = 0;
  290. uinfo->value.integer.max = 192000;
  291. return 0;
  292. }
  293. static int axg_spdifin_rate_lock_get(struct snd_kcontrol *kcontrol,
  294. struct snd_ctl_elem_value *ucontrol)
  295. {
  296. struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
  297. struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
  298. ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);
  299. return 0;
  300. }
  301. #define AXG_SPDIFIN_LOCK_RATE(xname) \
  302. { \
  303. .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
  304. .access = (SNDRV_CTL_ELEM_ACCESS_READ | \
  305. SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
  306. .get = axg_spdifin_rate_lock_get, \
  307. .info = axg_spdifin_rate_lock_info, \
  308. .name = xname, \
  309. }
  310. static const struct snd_kcontrol_new axg_spdifin_controls[] = {
  311. AXG_SPDIFIN_LOCK_RATE("Capture Rate Lock"),
  312. SOC_DOUBLE("Capture Switch", SPDIFIN_CTRL0, 7, 6, 1, 1),
  313. SOC_ENUM(SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Src",
  314. axg_spdifin_chsts_src_enum),
  315. AXG_SPDIFIN_IEC958_MASK,
  316. AXG_SPDIFIN_IEC958_STATUS,
  317. };
  318. static const struct snd_soc_component_driver axg_spdifin_component_drv = {
  319. .controls = axg_spdifin_controls,
  320. .num_controls = ARRAY_SIZE(axg_spdifin_controls),
  321. };
  322. static const struct regmap_config axg_spdifin_regmap_cfg = {
  323. .reg_bits = 32,
  324. .val_bits = 32,
  325. .reg_stride = 4,
  326. .max_register = SPDIFIN_MUTE_VAL,
  327. };
  328. static const unsigned int axg_spdifin_mode_rates[SPDIFIN_MODE_NUM] = {
  329. 32000, 44100, 48000, 88200, 96000, 176400, 192000,
  330. };
  331. static const struct axg_spdifin_cfg axg_cfg = {
  332. .mode_rates = axg_spdifin_mode_rates,
  333. .ref_rate = 333333333,
  334. };
  335. static const struct of_device_id axg_spdifin_of_match[] = {
  336. {
  337. .compatible = "amlogic,axg-spdifin",
  338. .data = &axg_cfg,
  339. }, {}
  340. };
  341. MODULE_DEVICE_TABLE(of, axg_spdifin_of_match);
  342. static struct snd_soc_dai_driver *
  343. axg_spdifin_get_dai_drv(struct device *dev, struct axg_spdifin *priv)
  344. {
  345. struct snd_soc_dai_driver *drv;
  346. int i;
  347. drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
  348. if (!drv)
  349. return ERR_PTR(-ENOMEM);
  350. drv->name = "SPDIF Input";
  351. drv->ops = &axg_spdifin_ops;
  352. drv->probe = axg_spdifin_dai_probe;
  353. drv->remove = axg_spdifin_dai_remove;
  354. drv->capture.stream_name = "Capture";
  355. drv->capture.channels_min = 1;
  356. drv->capture.channels_max = 2;
  357. drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
  358. for (i = 0; i < SPDIFIN_MODE_NUM; i++) {
  359. unsigned int rb =
  360. snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);
  361. if (rb == SNDRV_PCM_RATE_KNOT)
  362. return ERR_PTR(-EINVAL);
  363. drv->capture.rates |= rb;
  364. }
  365. return drv;
  366. }
  367. static int axg_spdifin_probe(struct platform_device *pdev)
  368. {
  369. struct device *dev = &pdev->dev;
  370. struct axg_spdifin *priv;
  371. struct snd_soc_dai_driver *dai_drv;
  372. void __iomem *regs;
  373. int ret;
  374. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  375. if (!priv)
  376. return -ENOMEM;
  377. platform_set_drvdata(pdev, priv);
  378. priv->conf = of_device_get_match_data(dev);
  379. if (!priv->conf) {
  380. dev_err(dev, "failed to match device\n");
  381. return -ENODEV;
  382. }
  383. regs = devm_platform_ioremap_resource(pdev, 0);
  384. if (IS_ERR(regs))
  385. return PTR_ERR(regs);
  386. priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);
  387. if (IS_ERR(priv->map)) {
  388. dev_err(dev, "failed to init regmap: %ld\n",
  389. PTR_ERR(priv->map));
  390. return PTR_ERR(priv->map);
  391. }
  392. priv->pclk = devm_clk_get(dev, "pclk");
  393. if (IS_ERR(priv->pclk)) {
  394. ret = PTR_ERR(priv->pclk);
  395. if (ret != -EPROBE_DEFER)
  396. dev_err(dev, "failed to get pclk: %d\n", ret);
  397. return ret;
  398. }
  399. priv->refclk = devm_clk_get(dev, "refclk");
  400. if (IS_ERR(priv->refclk)) {
  401. ret = PTR_ERR(priv->refclk);
  402. if (ret != -EPROBE_DEFER)
  403. dev_err(dev, "failed to get mclk: %d\n", ret);
  404. return ret;
  405. }
  406. dai_drv = axg_spdifin_get_dai_drv(dev, priv);
  407. if (IS_ERR(dai_drv)) {
  408. dev_err(dev, "failed to get dai driver: %ld\n",
  409. PTR_ERR(dai_drv));
  410. return PTR_ERR(dai_drv);
  411. }
  412. return devm_snd_soc_register_component(dev, &axg_spdifin_component_drv,
  413. dai_drv, 1);
  414. }
  415. static struct platform_driver axg_spdifin_pdrv = {
  416. .probe = axg_spdifin_probe,
  417. .driver = {
  418. .name = "axg-spdifin",
  419. .of_match_table = axg_spdifin_of_match,
  420. },
  421. };
  422. module_platform_driver(axg_spdifin_pdrv);
  423. MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");
  424. MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
  425. MODULE_LICENSE("GPL v2");