axg-frddr.c 13 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. /*
  6. * This driver implements the frontend playback DAI of AXG and G12A based SoCs
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/regmap.h>
  10. #include <linux/module.h>
  11. #include <linux/of_platform.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dai.h>
  14. #include "axg-fifo.h"
  15. #define CTRL0_FRDDR_PP_MODE BIT(30)
  16. #define CTRL0_SEL1_EN_SHIFT 3
  17. #define CTRL0_SEL2_SHIFT 4
  18. #define CTRL0_SEL2_EN_SHIFT 7
  19. #define CTRL0_SEL3_SHIFT 8
  20. #define CTRL0_SEL3_EN_SHIFT 11
  21. #define CTRL1_FRDDR_FORCE_FINISH BIT(12)
  22. #define CTRL2_SEL1_SHIFT 0
  23. #define CTRL2_SEL1_EN_SHIFT 4
  24. #define CTRL2_SEL2_SHIFT 8
  25. #define CTRL2_SEL2_EN_SHIFT 12
  26. #define CTRL2_SEL3_SHIFT 16
  27. #define CTRL2_SEL3_EN_SHIFT 20
  28. static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream,
  29. struct snd_soc_dai *dai)
  30. {
  31. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  32. /* Reset the read pointer to the FIFO_INIT_ADDR */
  33. regmap_update_bits(fifo->map, FIFO_CTRL1,
  34. CTRL1_FRDDR_FORCE_FINISH, 0);
  35. regmap_update_bits(fifo->map, FIFO_CTRL1,
  36. CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH);
  37. regmap_update_bits(fifo->map, FIFO_CTRL1,
  38. CTRL1_FRDDR_FORCE_FINISH, 0);
  39. return 0;
  40. }
  41. static int axg_frddr_dai_startup(struct snd_pcm_substream *substream,
  42. struct snd_soc_dai *dai)
  43. {
  44. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  45. unsigned int val;
  46. int ret;
  47. /* Enable pclk to access registers and clock the fifo ip */
  48. ret = clk_prepare_enable(fifo->pclk);
  49. if (ret)
  50. return ret;
  51. /* Apply single buffer mode to the interface */
  52. regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
  53. /* Use all fifo depth */
  54. val = (fifo->depth / AXG_FIFO_BURST) - 1;
  55. regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
  56. CTRL1_FRDDR_DEPTH(val));
  57. return 0;
  58. }
  59. static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream,
  60. struct snd_soc_dai *dai)
  61. {
  62. struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
  63. clk_disable_unprepare(fifo->pclk);
  64. }
  65. static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
  66. struct snd_soc_dai *dai)
  67. {
  68. return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK);
  69. }
  70. static const struct snd_soc_dai_ops axg_frddr_ops = {
  71. .startup = axg_frddr_dai_startup,
  72. .shutdown = axg_frddr_dai_shutdown,
  73. };
  74. static struct snd_soc_dai_driver axg_frddr_dai_drv = {
  75. .name = "FRDDR",
  76. .playback = {
  77. .stream_name = "Playback",
  78. .channels_min = 1,
  79. .channels_max = AXG_FIFO_CH_MAX,
  80. .rates = AXG_FIFO_RATES,
  81. .formats = AXG_FIFO_FORMATS,
  82. },
  83. .ops = &axg_frddr_ops,
  84. .pcm_new = axg_frddr_pcm_new,
  85. };
  86. static const char * const axg_frddr_sel_texts[] = {
  87. "OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4", "OUT 5", "OUT 6", "OUT 7",
  88. };
  89. static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
  90. axg_frddr_sel_texts);
  91. static const struct snd_kcontrol_new axg_frddr_out_demux =
  92. SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum);
  93. static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = {
  94. SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0,
  95. &axg_frddr_out_demux),
  96. SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
  97. SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  98. SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  99. SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  100. SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
  101. SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
  102. SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
  103. SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
  104. };
  105. static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = {
  106. { "SINK SEL", NULL, "Playback" },
  107. { "OUT 0", "OUT 0", "SINK SEL" },
  108. { "OUT 1", "OUT 1", "SINK SEL" },
  109. { "OUT 2", "OUT 2", "SINK SEL" },
  110. { "OUT 3", "OUT 3", "SINK SEL" },
  111. { "OUT 4", "OUT 4", "SINK SEL" },
  112. { "OUT 5", "OUT 5", "SINK SEL" },
  113. { "OUT 6", "OUT 6", "SINK SEL" },
  114. { "OUT 7", "OUT 7", "SINK SEL" },
  115. };
  116. static const struct snd_soc_component_driver axg_frddr_component_drv = {
  117. .dapm_widgets = axg_frddr_dapm_widgets,
  118. .num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets),
  119. .dapm_routes = axg_frddr_dapm_routes,
  120. .num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes),
  121. .open = axg_fifo_pcm_open,
  122. .close = axg_fifo_pcm_close,
  123. .hw_params = axg_fifo_pcm_hw_params,
  124. .hw_free = axg_fifo_pcm_hw_free,
  125. .pointer = axg_fifo_pcm_pointer,
  126. .trigger = axg_fifo_pcm_trigger,
  127. };
  128. static const struct axg_fifo_match_data axg_frddr_match_data = {
  129. .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
  130. .component_drv = &axg_frddr_component_drv,
  131. .dai_drv = &axg_frddr_dai_drv
  132. };
  133. static const struct snd_soc_dai_ops g12a_frddr_ops = {
  134. .prepare = g12a_frddr_dai_prepare,
  135. .startup = axg_frddr_dai_startup,
  136. .shutdown = axg_frddr_dai_shutdown,
  137. };
  138. static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
  139. .name = "FRDDR",
  140. .playback = {
  141. .stream_name = "Playback",
  142. .channels_min = 1,
  143. .channels_max = AXG_FIFO_CH_MAX,
  144. .rates = AXG_FIFO_RATES,
  145. .formats = AXG_FIFO_FORMATS,
  146. },
  147. .ops = &g12a_frddr_ops,
  148. .pcm_new = axg_frddr_pcm_new,
  149. };
  150. static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
  151. axg_frddr_sel_texts);
  152. static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT,
  153. axg_frddr_sel_texts);
  154. static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT,
  155. axg_frddr_sel_texts);
  156. static const struct snd_kcontrol_new g12a_frddr_out1_demux =
  157. SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum);
  158. static const struct snd_kcontrol_new g12a_frddr_out2_demux =
  159. SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum);
  160. static const struct snd_kcontrol_new g12a_frddr_out3_demux =
  161. SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum);
  162. static const struct snd_kcontrol_new g12a_frddr_out1_enable =
  163. SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
  164. CTRL0_SEL1_EN_SHIFT, 1, 0);
  165. static const struct snd_kcontrol_new g12a_frddr_out2_enable =
  166. SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
  167. CTRL0_SEL2_EN_SHIFT, 1, 0);
  168. static const struct snd_kcontrol_new g12a_frddr_out3_enable =
  169. SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
  170. CTRL0_SEL3_EN_SHIFT, 1, 0);
  171. static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = {
  172. SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  173. SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  174. SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  175. SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
  176. &g12a_frddr_out1_enable),
  177. SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
  178. &g12a_frddr_out2_enable),
  179. SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
  180. &g12a_frddr_out3_enable),
  181. SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
  182. &g12a_frddr_out1_demux),
  183. SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
  184. &g12a_frddr_out2_demux),
  185. SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
  186. &g12a_frddr_out3_demux),
  187. SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
  188. SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  189. SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  190. SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  191. SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
  192. SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
  193. SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
  194. SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
  195. };
  196. static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = {
  197. { "SRC 1", NULL, "Playback" },
  198. { "SRC 2", NULL, "Playback" },
  199. { "SRC 3", NULL, "Playback" },
  200. { "SRC 1 EN", "Switch", "SRC 1" },
  201. { "SRC 2 EN", "Switch", "SRC 2" },
  202. { "SRC 3 EN", "Switch", "SRC 3" },
  203. { "SINK 1 SEL", NULL, "SRC 1 EN" },
  204. { "SINK 2 SEL", NULL, "SRC 2 EN" },
  205. { "SINK 3 SEL", NULL, "SRC 3 EN" },
  206. { "OUT 0", "OUT 0", "SINK 1 SEL" },
  207. { "OUT 1", "OUT 1", "SINK 1 SEL" },
  208. { "OUT 2", "OUT 2", "SINK 1 SEL" },
  209. { "OUT 3", "OUT 3", "SINK 1 SEL" },
  210. { "OUT 4", "OUT 4", "SINK 1 SEL" },
  211. { "OUT 5", "OUT 5", "SINK 1 SEL" },
  212. { "OUT 6", "OUT 6", "SINK 1 SEL" },
  213. { "OUT 7", "OUT 7", "SINK 1 SEL" },
  214. { "OUT 0", "OUT 0", "SINK 2 SEL" },
  215. { "OUT 1", "OUT 1", "SINK 2 SEL" },
  216. { "OUT 2", "OUT 2", "SINK 2 SEL" },
  217. { "OUT 3", "OUT 3", "SINK 2 SEL" },
  218. { "OUT 4", "OUT 4", "SINK 2 SEL" },
  219. { "OUT 5", "OUT 5", "SINK 2 SEL" },
  220. { "OUT 6", "OUT 6", "SINK 2 SEL" },
  221. { "OUT 7", "OUT 7", "SINK 2 SEL" },
  222. { "OUT 0", "OUT 0", "SINK 3 SEL" },
  223. { "OUT 1", "OUT 1", "SINK 3 SEL" },
  224. { "OUT 2", "OUT 2", "SINK 3 SEL" },
  225. { "OUT 3", "OUT 3", "SINK 3 SEL" },
  226. { "OUT 4", "OUT 4", "SINK 3 SEL" },
  227. { "OUT 5", "OUT 5", "SINK 3 SEL" },
  228. { "OUT 6", "OUT 6", "SINK 3 SEL" },
  229. { "OUT 7", "OUT 7", "SINK 3 SEL" },
  230. };
  231. static const struct snd_soc_component_driver g12a_frddr_component_drv = {
  232. .dapm_widgets = g12a_frddr_dapm_widgets,
  233. .num_dapm_widgets = ARRAY_SIZE(g12a_frddr_dapm_widgets),
  234. .dapm_routes = g12a_frddr_dapm_routes,
  235. .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
  236. .open = axg_fifo_pcm_open,
  237. .close = axg_fifo_pcm_close,
  238. .hw_params = g12a_fifo_pcm_hw_params,
  239. .hw_free = axg_fifo_pcm_hw_free,
  240. .pointer = axg_fifo_pcm_pointer,
  241. .trigger = axg_fifo_pcm_trigger,
  242. };
  243. static const struct axg_fifo_match_data g12a_frddr_match_data = {
  244. .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
  245. .component_drv = &g12a_frddr_component_drv,
  246. .dai_drv = &g12a_frddr_dai_drv
  247. };
  248. /* On SM1, the output selection in on CTRL2 */
  249. static const struct snd_kcontrol_new sm1_frddr_out1_enable =
  250. SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
  251. CTRL2_SEL1_EN_SHIFT, 1, 0);
  252. static const struct snd_kcontrol_new sm1_frddr_out2_enable =
  253. SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
  254. CTRL2_SEL2_EN_SHIFT, 1, 0);
  255. static const struct snd_kcontrol_new sm1_frddr_out3_enable =
  256. SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
  257. CTRL2_SEL3_EN_SHIFT, 1, 0);
  258. static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel1_enum, FIFO_CTRL2, CTRL2_SEL1_SHIFT,
  259. axg_frddr_sel_texts);
  260. static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel2_enum, FIFO_CTRL2, CTRL2_SEL2_SHIFT,
  261. axg_frddr_sel_texts);
  262. static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel3_enum, FIFO_CTRL2, CTRL2_SEL3_SHIFT,
  263. axg_frddr_sel_texts);
  264. static const struct snd_kcontrol_new sm1_frddr_out1_demux =
  265. SOC_DAPM_ENUM("Output Src 1", sm1_frddr_sel1_enum);
  266. static const struct snd_kcontrol_new sm1_frddr_out2_demux =
  267. SOC_DAPM_ENUM("Output Src 2", sm1_frddr_sel2_enum);
  268. static const struct snd_kcontrol_new sm1_frddr_out3_demux =
  269. SOC_DAPM_ENUM("Output Src 3", sm1_frddr_sel3_enum);
  270. static const struct snd_soc_dapm_widget sm1_frddr_dapm_widgets[] = {
  271. SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  272. SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  273. SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  274. SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
  275. &sm1_frddr_out1_enable),
  276. SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
  277. &sm1_frddr_out2_enable),
  278. SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
  279. &sm1_frddr_out3_enable),
  280. SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
  281. &sm1_frddr_out1_demux),
  282. SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
  283. &sm1_frddr_out2_demux),
  284. SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
  285. &sm1_frddr_out3_demux),
  286. SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
  287. SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
  288. SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
  289. SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
  290. SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
  291. SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
  292. SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
  293. SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
  294. };
  295. static const struct snd_soc_component_driver sm1_frddr_component_drv = {
  296. .dapm_widgets = sm1_frddr_dapm_widgets,
  297. .num_dapm_widgets = ARRAY_SIZE(sm1_frddr_dapm_widgets),
  298. .dapm_routes = g12a_frddr_dapm_routes,
  299. .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
  300. .open = axg_fifo_pcm_open,
  301. .close = axg_fifo_pcm_close,
  302. .hw_params = g12a_fifo_pcm_hw_params,
  303. .hw_free = axg_fifo_pcm_hw_free,
  304. .pointer = axg_fifo_pcm_pointer,
  305. .trigger = axg_fifo_pcm_trigger,
  306. };
  307. static const struct axg_fifo_match_data sm1_frddr_match_data = {
  308. .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
  309. .component_drv = &sm1_frddr_component_drv,
  310. .dai_drv = &g12a_frddr_dai_drv
  311. };
  312. static const struct of_device_id axg_frddr_of_match[] = {
  313. {
  314. .compatible = "amlogic,axg-frddr",
  315. .data = &axg_frddr_match_data,
  316. }, {
  317. .compatible = "amlogic,g12a-frddr",
  318. .data = &g12a_frddr_match_data,
  319. }, {
  320. .compatible = "amlogic,sm1-frddr",
  321. .data = &sm1_frddr_match_data,
  322. }, {}
  323. };
  324. MODULE_DEVICE_TABLE(of, axg_frddr_of_match);
  325. static struct platform_driver axg_frddr_pdrv = {
  326. .probe = axg_fifo_probe,
  327. .driver = {
  328. .name = "axg-frddr",
  329. .of_match_table = axg_frddr_of_match,
  330. },
  331. };
  332. module_platform_driver(axg_frddr_pdrv);
  333. MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");
  334. MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
  335. MODULE_LICENSE("GPL v2");