axg-fifo.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899
  1. /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
  2. /*
  3. * Copyright (c) 2018 BayLibre, SAS.
  4. * Author: Jerome Brunet <jbrunet@baylibre.com>
  5. */
  6. #ifndef _MESON_AXG_FIFO_H
  7. #define _MESON_AXG_FIFO_H
  8. struct clk;
  9. struct platform_device;
  10. struct reg_field;
  11. struct regmap;
  12. struct regmap_field;
  13. struct reset_control;
  14. struct snd_soc_component_driver;
  15. struct snd_soc_dai;
  16. struct snd_soc_dai_driver;
  17. struct snd_soc_pcm_runtime;
  18. #define AXG_FIFO_CH_MAX 128
  19. #define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \
  20. SNDRV_PCM_RATE_8000_192000)
  21. #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
  22. SNDRV_PCM_FMTBIT_S16_LE | \
  23. SNDRV_PCM_FMTBIT_S20_LE | \
  24. SNDRV_PCM_FMTBIT_S24_LE | \
  25. SNDRV_PCM_FMTBIT_S32_LE | \
  26. SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
  27. #define AXG_FIFO_BURST 8
  28. #define FIFO_INT_ADDR_FINISH BIT(0)
  29. #define FIFO_INT_ADDR_INT BIT(1)
  30. #define FIFO_INT_COUNT_REPEAT BIT(2)
  31. #define FIFO_INT_COUNT_ONCE BIT(3)
  32. #define FIFO_INT_FIFO_ZERO BIT(4)
  33. #define FIFO_INT_FIFO_DEPTH BIT(5)
  34. #define FIFO_INT_MASK GENMASK(7, 0)
  35. #define FIFO_CTRL0 0x00
  36. #define CTRL0_DMA_EN BIT(31)
  37. #define CTRL0_INT_EN(x) ((x) << 16)
  38. #define CTRL0_SEL_MASK GENMASK(2, 0)
  39. #define CTRL0_SEL_SHIFT 0
  40. #define FIFO_CTRL1 0x04
  41. #define CTRL1_INT_CLR(x) ((x) << 0)
  42. #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
  43. #define CTRL1_STATUS2_SEL(x) ((x) << 8)
  44. #define STATUS2_SEL_DDR_READ 0
  45. #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
  46. #define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
  47. #define FIFO_START_ADDR 0x08
  48. #define FIFO_FINISH_ADDR 0x0c
  49. #define FIFO_INT_ADDR 0x10
  50. #define FIFO_STATUS1 0x14
  51. #define STATUS1_INT_STS(x) ((x) << 0)
  52. #define FIFO_STATUS2 0x18
  53. #define FIFO_INIT_ADDR 0x24
  54. #define FIFO_CTRL2 0x28
  55. struct axg_fifo {
  56. struct regmap *map;
  57. struct clk *pclk;
  58. struct reset_control *arb;
  59. struct regmap_field *field_threshold;
  60. unsigned int depth;
  61. int irq;
  62. };
  63. struct axg_fifo_match_data {
  64. const struct snd_soc_component_driver *component_drv;
  65. struct snd_soc_dai_driver *dai_drv;
  66. struct reg_field field_threshold;
  67. };
  68. int axg_fifo_pcm_open(struct snd_soc_component *component,
  69. struct snd_pcm_substream *ss);
  70. int axg_fifo_pcm_close(struct snd_soc_component *component,
  71. struct snd_pcm_substream *ss);
  72. int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
  73. struct snd_pcm_substream *ss,
  74. struct snd_pcm_hw_params *params);
  75. int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
  76. struct snd_pcm_substream *ss,
  77. struct snd_pcm_hw_params *params);
  78. int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
  79. struct snd_pcm_substream *ss);
  80. snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
  81. struct snd_pcm_substream *ss);
  82. int axg_fifo_pcm_trigger(struct snd_soc_component *component,
  83. struct snd_pcm_substream *ss, int cmd);
  84. int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
  85. int axg_fifo_probe(struct platform_device *pdev);
  86. #endif /* _MESON_AXG_FIFO_H */