axg-fifo.c 10.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. //
  3. // Copyright (c) 2018 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. #include <linux/clk.h>
  6. #include <linux/of_irq.h>
  7. #include <linux/of_platform.h>
  8. #include <linux/module.h>
  9. #include <linux/regmap.h>
  10. #include <linux/reset.h>
  11. #include <sound/pcm_params.h>
  12. #include <sound/soc.h>
  13. #include <sound/soc-dai.h>
  14. #include "axg-fifo.h"
  15. /*
  16. * This file implements the platform operations common to the playback and
  17. * capture frontend DAI. The logic behind this two types of fifo is very
  18. * similar but some difference exist.
  19. * These differences are handled in the respective DAI drivers
  20. */
  21. static struct snd_pcm_hardware axg_fifo_hw = {
  22. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  23. SNDRV_PCM_INFO_MMAP |
  24. SNDRV_PCM_INFO_MMAP_VALID |
  25. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  26. SNDRV_PCM_INFO_PAUSE),
  27. .formats = AXG_FIFO_FORMATS,
  28. .rate_min = 5512,
  29. .rate_max = 192000,
  30. .channels_min = 1,
  31. .channels_max = AXG_FIFO_CH_MAX,
  32. .period_bytes_min = AXG_FIFO_BURST,
  33. .period_bytes_max = UINT_MAX,
  34. .periods_min = 2,
  35. .periods_max = UINT_MAX,
  36. /* No real justification for this */
  37. .buffer_bytes_max = 1 * 1024 * 1024,
  38. };
  39. static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss)
  40. {
  41. struct snd_soc_pcm_runtime *rtd = ss->private_data;
  42. return asoc_rtd_to_cpu(rtd, 0);
  43. }
  44. static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
  45. {
  46. struct snd_soc_dai *dai = axg_fifo_dai(ss);
  47. return snd_soc_dai_get_drvdata(dai);
  48. }
  49. static struct device *axg_fifo_dev(struct snd_pcm_substream *ss)
  50. {
  51. struct snd_soc_dai *dai = axg_fifo_dai(ss);
  52. return dai->dev;
  53. }
  54. static void __dma_enable(struct axg_fifo *fifo, bool enable)
  55. {
  56. regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
  57. enable ? CTRL0_DMA_EN : 0);
  58. }
  59. int axg_fifo_pcm_trigger(struct snd_soc_component *component,
  60. struct snd_pcm_substream *ss, int cmd)
  61. {
  62. struct axg_fifo *fifo = axg_fifo_data(ss);
  63. switch (cmd) {
  64. case SNDRV_PCM_TRIGGER_START:
  65. case SNDRV_PCM_TRIGGER_RESUME:
  66. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  67. __dma_enable(fifo, true);
  68. break;
  69. case SNDRV_PCM_TRIGGER_SUSPEND:
  70. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  71. case SNDRV_PCM_TRIGGER_STOP:
  72. __dma_enable(fifo, false);
  73. break;
  74. default:
  75. return -EINVAL;
  76. }
  77. return 0;
  78. }
  79. EXPORT_SYMBOL_GPL(axg_fifo_pcm_trigger);
  80. snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
  81. struct snd_pcm_substream *ss)
  82. {
  83. struct axg_fifo *fifo = axg_fifo_data(ss);
  84. struct snd_pcm_runtime *runtime = ss->runtime;
  85. unsigned int addr;
  86. regmap_read(fifo->map, FIFO_STATUS2, &addr);
  87. return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
  88. }
  89. EXPORT_SYMBOL_GPL(axg_fifo_pcm_pointer);
  90. int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
  91. struct snd_pcm_substream *ss,
  92. struct snd_pcm_hw_params *params)
  93. {
  94. struct snd_pcm_runtime *runtime = ss->runtime;
  95. struct axg_fifo *fifo = axg_fifo_data(ss);
  96. unsigned int burst_num, period, threshold;
  97. dma_addr_t end_ptr;
  98. period = params_period_bytes(params);
  99. /* Setup dma memory pointers */
  100. end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
  101. regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
  102. regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
  103. /* Setup interrupt periodicity */
  104. burst_num = period / AXG_FIFO_BURST;
  105. regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
  106. /*
  107. * Start the fifo request on the smallest of the following:
  108. * - Half the fifo size
  109. * - Half the period size
  110. */
  111. threshold = min(period / 2, fifo->depth / 2);
  112. /*
  113. * With the threshold in bytes, register value is:
  114. * V = (threshold / burst) - 1
  115. */
  116. threshold /= AXG_FIFO_BURST;
  117. regmap_field_write(fifo->field_threshold,
  118. threshold ? threshold - 1 : 0);
  119. /* Enable block count irq */
  120. regmap_update_bits(fifo->map, FIFO_CTRL0,
  121. CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
  122. CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
  123. return 0;
  124. }
  125. EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_params);
  126. int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
  127. struct snd_pcm_substream *ss,
  128. struct snd_pcm_hw_params *params)
  129. {
  130. struct axg_fifo *fifo = axg_fifo_data(ss);
  131. struct snd_pcm_runtime *runtime = ss->runtime;
  132. int ret;
  133. ret = axg_fifo_pcm_hw_params(component, ss, params);
  134. if (ret)
  135. return ret;
  136. /* Set the initial memory address of the DMA */
  137. regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
  138. return 0;
  139. }
  140. EXPORT_SYMBOL_GPL(g12a_fifo_pcm_hw_params);
  141. int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
  142. struct snd_pcm_substream *ss)
  143. {
  144. struct axg_fifo *fifo = axg_fifo_data(ss);
  145. /* Disable the block count irq */
  146. regmap_update_bits(fifo->map, FIFO_CTRL0,
  147. CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
  148. return 0;
  149. }
  150. EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free);
  151. static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
  152. {
  153. regmap_update_bits(fifo->map, FIFO_CTRL1,
  154. CTRL1_INT_CLR(FIFO_INT_MASK),
  155. CTRL1_INT_CLR(mask));
  156. /* Clear must also be cleared */
  157. regmap_update_bits(fifo->map, FIFO_CTRL1,
  158. CTRL1_INT_CLR(FIFO_INT_MASK),
  159. 0);
  160. }
  161. static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
  162. {
  163. struct snd_pcm_substream *ss = dev_id;
  164. struct axg_fifo *fifo = axg_fifo_data(ss);
  165. unsigned int status;
  166. regmap_read(fifo->map, FIFO_STATUS1, &status);
  167. status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
  168. if (status & FIFO_INT_COUNT_REPEAT)
  169. snd_pcm_period_elapsed(ss);
  170. else
  171. dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
  172. status);
  173. /* Ack irqs */
  174. axg_fifo_ack_irq(fifo, status);
  175. return IRQ_RETVAL(status);
  176. }
  177. int axg_fifo_pcm_open(struct snd_soc_component *component,
  178. struct snd_pcm_substream *ss)
  179. {
  180. struct axg_fifo *fifo = axg_fifo_data(ss);
  181. struct device *dev = axg_fifo_dev(ss);
  182. int ret;
  183. snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw);
  184. /*
  185. * Make sure the buffer and period size are multiple of the FIFO
  186. * burst
  187. */
  188. ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
  189. SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  190. AXG_FIFO_BURST);
  191. if (ret)
  192. return ret;
  193. ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
  194. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  195. AXG_FIFO_BURST);
  196. if (ret)
  197. return ret;
  198. ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
  199. dev_name(dev), ss);
  200. if (ret)
  201. return ret;
  202. /* Enable pclk to access registers and clock the fifo ip */
  203. ret = clk_prepare_enable(fifo->pclk);
  204. if (ret)
  205. goto free_irq;
  206. /* Setup status2 so it reports the memory pointer */
  207. regmap_update_bits(fifo->map, FIFO_CTRL1,
  208. CTRL1_STATUS2_SEL_MASK,
  209. CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
  210. /* Make sure the dma is initially disabled */
  211. __dma_enable(fifo, false);
  212. /* Disable irqs until params are ready */
  213. regmap_update_bits(fifo->map, FIFO_CTRL0,
  214. CTRL0_INT_EN(FIFO_INT_MASK), 0);
  215. /* Clear any pending interrupt */
  216. axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
  217. /* Take memory arbitror out of reset */
  218. ret = reset_control_deassert(fifo->arb);
  219. if (ret)
  220. goto free_clk;
  221. return 0;
  222. free_clk:
  223. clk_disable_unprepare(fifo->pclk);
  224. free_irq:
  225. free_irq(fifo->irq, ss);
  226. return ret;
  227. }
  228. EXPORT_SYMBOL_GPL(axg_fifo_pcm_open);
  229. int axg_fifo_pcm_close(struct snd_soc_component *component,
  230. struct snd_pcm_substream *ss)
  231. {
  232. struct axg_fifo *fifo = axg_fifo_data(ss);
  233. int ret;
  234. /* Put the memory arbitror back in reset */
  235. ret = reset_control_assert(fifo->arb);
  236. /* Disable fifo ip and register access */
  237. clk_disable_unprepare(fifo->pclk);
  238. /* remove IRQ */
  239. free_irq(fifo->irq, ss);
  240. return ret;
  241. }
  242. EXPORT_SYMBOL_GPL(axg_fifo_pcm_close);
  243. int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
  244. {
  245. struct snd_card *card = rtd->card->snd_card;
  246. size_t size = axg_fifo_hw.buffer_bytes_max;
  247. snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream,
  248. SNDRV_DMA_TYPE_DEV, card->dev,
  249. size, size);
  250. return 0;
  251. }
  252. EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
  253. static const struct regmap_config axg_fifo_regmap_cfg = {
  254. .reg_bits = 32,
  255. .val_bits = 32,
  256. .reg_stride = 4,
  257. .max_register = FIFO_CTRL2,
  258. };
  259. int axg_fifo_probe(struct platform_device *pdev)
  260. {
  261. struct device *dev = &pdev->dev;
  262. const struct axg_fifo_match_data *data;
  263. struct axg_fifo *fifo;
  264. void __iomem *regs;
  265. int ret;
  266. data = of_device_get_match_data(dev);
  267. if (!data) {
  268. dev_err(dev, "failed to match device\n");
  269. return -ENODEV;
  270. }
  271. fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
  272. if (!fifo)
  273. return -ENOMEM;
  274. platform_set_drvdata(pdev, fifo);
  275. regs = devm_platform_ioremap_resource(pdev, 0);
  276. if (IS_ERR(regs))
  277. return PTR_ERR(regs);
  278. fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
  279. if (IS_ERR(fifo->map)) {
  280. dev_err(dev, "failed to init regmap: %ld\n",
  281. PTR_ERR(fifo->map));
  282. return PTR_ERR(fifo->map);
  283. }
  284. fifo->pclk = devm_clk_get(dev, NULL);
  285. if (IS_ERR(fifo->pclk)) {
  286. if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)
  287. dev_err(dev, "failed to get pclk: %ld\n",
  288. PTR_ERR(fifo->pclk));
  289. return PTR_ERR(fifo->pclk);
  290. }
  291. fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
  292. if (IS_ERR(fifo->arb)) {
  293. if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)
  294. dev_err(dev, "failed to get arb reset: %ld\n",
  295. PTR_ERR(fifo->arb));
  296. return PTR_ERR(fifo->arb);
  297. }
  298. fifo->irq = of_irq_get(dev->of_node, 0);
  299. if (fifo->irq <= 0) {
  300. dev_err(dev, "failed to get irq: %d\n", fifo->irq);
  301. return fifo->irq;
  302. }
  303. fifo->field_threshold =
  304. devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
  305. if (IS_ERR(fifo->field_threshold))
  306. return PTR_ERR(fifo->field_threshold);
  307. ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
  308. &fifo->depth);
  309. if (ret) {
  310. /* Error out for anything but a missing property */
  311. if (ret != -EINVAL)
  312. return ret;
  313. /*
  314. * If the property is missing, it might be because of an old
  315. * DT. In such case, assume the smallest known fifo depth
  316. */
  317. fifo->depth = 256;
  318. dev_warn(dev, "fifo depth not found, assume %u bytes\n",
  319. fifo->depth);
  320. }
  321. return devm_snd_soc_register_component(dev, data->component_drv,
  322. data->dai_drv, 1);
  323. }
  324. EXPORT_SYMBOL_GPL(axg_fifo_probe);
  325. MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");
  326. MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
  327. MODULE_LICENSE("GPL v2");