aiu-fifo-spdif.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2020 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. #include <linux/clk.h>
  6. #include <sound/pcm_params.h>
  7. #include <sound/soc.h>
  8. #include <sound/soc-dai.h>
  9. #include "aiu.h"
  10. #include "aiu-fifo.h"
  11. #define AIU_IEC958_DCU_FF_CTRL_EN BIT(0)
  12. #define AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE BIT(1)
  13. #define AIU_IEC958_DCU_FF_CTRL_IRQ_MODE GENMASK(3, 2)
  14. #define AIU_IEC958_DCU_FF_CTRL_IRQ_OUT_THD BIT(2)
  15. #define AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ BIT(3)
  16. #define AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN BIT(4)
  17. #define AIU_IEC958_DCU_FF_CTRL_BYTE_SEEK BIT(5)
  18. #define AIU_IEC958_DCU_FF_CTRL_CONTINUE BIT(6)
  19. #define AIU_MEM_IEC958_CONTROL_ENDIAN GENMASK(5, 3)
  20. #define AIU_MEM_IEC958_CONTROL_RD_DDR BIT(6)
  21. #define AIU_MEM_IEC958_CONTROL_MODE_16BIT BIT(7)
  22. #define AIU_MEM_IEC958_CONTROL_MODE_LINEAR BIT(8)
  23. #define AIU_MEM_IEC958_BUF_CNTL_INIT BIT(0)
  24. #define AIU_FIFO_SPDIF_BLOCK 8
  25. static struct snd_pcm_hardware fifo_spdif_pcm = {
  26. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  27. SNDRV_PCM_INFO_MMAP |
  28. SNDRV_PCM_INFO_MMAP_VALID |
  29. SNDRV_PCM_INFO_PAUSE),
  30. .formats = AIU_FORMATS,
  31. .rate_min = 5512,
  32. .rate_max = 192000,
  33. .channels_min = 2,
  34. .channels_max = 2,
  35. .period_bytes_min = AIU_FIFO_SPDIF_BLOCK,
  36. .period_bytes_max = AIU_FIFO_SPDIF_BLOCK * USHRT_MAX,
  37. .periods_min = 2,
  38. .periods_max = UINT_MAX,
  39. /* No real justification for this */
  40. .buffer_bytes_max = 1 * 1024 * 1024,
  41. };
  42. static void fifo_spdif_dcu_enable(struct snd_soc_component *component,
  43. bool enable)
  44. {
  45. snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
  46. AIU_IEC958_DCU_FF_CTRL_EN,
  47. enable ? AIU_IEC958_DCU_FF_CTRL_EN : 0);
  48. }
  49. static int fifo_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
  50. struct snd_soc_dai *dai)
  51. {
  52. struct snd_soc_component *component = dai->component;
  53. int ret;
  54. ret = aiu_fifo_trigger(substream, cmd, dai);
  55. if (ret)
  56. return ret;
  57. switch (cmd) {
  58. case SNDRV_PCM_TRIGGER_START:
  59. case SNDRV_PCM_TRIGGER_RESUME:
  60. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  61. fifo_spdif_dcu_enable(component, true);
  62. break;
  63. case SNDRV_PCM_TRIGGER_SUSPEND:
  64. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  65. case SNDRV_PCM_TRIGGER_STOP:
  66. fifo_spdif_dcu_enable(component, false);
  67. break;
  68. default:
  69. return -EINVAL;
  70. }
  71. return 0;
  72. }
  73. static int fifo_spdif_prepare(struct snd_pcm_substream *substream,
  74. struct snd_soc_dai *dai)
  75. {
  76. struct snd_soc_component *component = dai->component;
  77. int ret;
  78. ret = aiu_fifo_prepare(substream, dai);
  79. if (ret)
  80. return ret;
  81. snd_soc_component_update_bits(component,
  82. AIU_MEM_IEC958_BUF_CNTL,
  83. AIU_MEM_IEC958_BUF_CNTL_INIT,
  84. AIU_MEM_IEC958_BUF_CNTL_INIT);
  85. snd_soc_component_update_bits(component,
  86. AIU_MEM_IEC958_BUF_CNTL,
  87. AIU_MEM_IEC958_BUF_CNTL_INIT, 0);
  88. return 0;
  89. }
  90. static int fifo_spdif_hw_params(struct snd_pcm_substream *substream,
  91. struct snd_pcm_hw_params *params,
  92. struct snd_soc_dai *dai)
  93. {
  94. struct snd_soc_component *component = dai->component;
  95. unsigned int val;
  96. int ret;
  97. ret = aiu_fifo_hw_params(substream, params, dai);
  98. if (ret)
  99. return ret;
  100. val = AIU_MEM_IEC958_CONTROL_RD_DDR |
  101. AIU_MEM_IEC958_CONTROL_MODE_LINEAR;
  102. switch (params_physical_width(params)) {
  103. case 16:
  104. val |= AIU_MEM_IEC958_CONTROL_MODE_16BIT;
  105. break;
  106. case 32:
  107. break;
  108. default:
  109. dev_err(dai->dev, "Unsupported physical width %u\n",
  110. params_physical_width(params));
  111. return -EINVAL;
  112. }
  113. snd_soc_component_update_bits(component, AIU_MEM_IEC958_CONTROL,
  114. AIU_MEM_IEC958_CONTROL_ENDIAN |
  115. AIU_MEM_IEC958_CONTROL_RD_DDR |
  116. AIU_MEM_IEC958_CONTROL_MODE_LINEAR |
  117. AIU_MEM_IEC958_CONTROL_MODE_16BIT,
  118. val);
  119. /* Number bytes read by the FIFO between each IRQ */
  120. snd_soc_component_write(component, AIU_IEC958_BPF,
  121. params_period_bytes(params));
  122. /*
  123. * AUTO_DISABLE and SYNC_HEAD are enabled by default but
  124. * this should be disabled in PCM (uncompressed) mode
  125. */
  126. snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
  127. AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE |
  128. AIU_IEC958_DCU_FF_CTRL_IRQ_MODE |
  129. AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN,
  130. AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ);
  131. return 0;
  132. }
  133. const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops = {
  134. .trigger = fifo_spdif_trigger,
  135. .prepare = fifo_spdif_prepare,
  136. .hw_params = fifo_spdif_hw_params,
  137. .hw_free = aiu_fifo_hw_free,
  138. .startup = aiu_fifo_startup,
  139. .shutdown = aiu_fifo_shutdown,
  140. };
  141. int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai)
  142. {
  143. struct snd_soc_component *component = dai->component;
  144. struct aiu *aiu = snd_soc_component_get_drvdata(component);
  145. struct aiu_fifo *fifo;
  146. int ret;
  147. ret = aiu_fifo_dai_probe(dai);
  148. if (ret)
  149. return ret;
  150. fifo = dai->playback_dma_data;
  151. fifo->pcm = &fifo_spdif_pcm;
  152. fifo->mem_offset = AIU_MEM_IEC958_START;
  153. fifo->fifo_block = 1;
  154. fifo->pclk = aiu->spdif.clks[PCLK].clk;
  155. fifo->irq = aiu->spdif.irq;
  156. return 0;
  157. }