aiu-fifo-i2s.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171
  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2020 BayLibre, SAS.
  4. // Author: Jerome Brunet <jbrunet@baylibre.com>
  5. #include <linux/bitfield.h>
  6. #include <linux/clk.h>
  7. #include <sound/pcm_params.h>
  8. #include <sound/soc.h>
  9. #include <sound/soc-dai.h>
  10. #include "aiu.h"
  11. #include "aiu-fifo.h"
  12. #define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
  13. #define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
  14. #define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
  15. #define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
  16. #define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)
  17. #define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)
  18. #define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)
  19. #define AIU_RST_SOFT_I2S_FAST BIT(0)
  20. #define AIU_I2S_MISC_HOLD_EN BIT(2)
  21. #define AIU_I2S_MISC_FORCE_LEFT_RIGHT BIT(4)
  22. #define AIU_FIFO_I2S_BLOCK 256
  23. static struct snd_pcm_hardware fifo_i2s_pcm = {
  24. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  25. SNDRV_PCM_INFO_MMAP |
  26. SNDRV_PCM_INFO_MMAP_VALID |
  27. SNDRV_PCM_INFO_PAUSE),
  28. .formats = AIU_FORMATS,
  29. .rate_min = 5512,
  30. .rate_max = 192000,
  31. .channels_min = 2,
  32. .channels_max = 8,
  33. .period_bytes_min = AIU_FIFO_I2S_BLOCK,
  34. .period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
  35. .periods_min = 2,
  36. .periods_max = UINT_MAX,
  37. /* No real justification for this */
  38. .buffer_bytes_max = 1 * 1024 * 1024,
  39. };
  40. static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  41. struct snd_soc_dai *dai)
  42. {
  43. struct snd_soc_component *component = dai->component;
  44. switch (cmd) {
  45. case SNDRV_PCM_TRIGGER_START:
  46. case SNDRV_PCM_TRIGGER_RESUME:
  47. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  48. snd_soc_component_write(component, AIU_RST_SOFT,
  49. AIU_RST_SOFT_I2S_FAST);
  50. snd_soc_component_read(component, AIU_I2S_SYNC);
  51. break;
  52. }
  53. return aiu_fifo_trigger(substream, cmd, dai);
  54. }
  55. static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
  56. struct snd_soc_dai *dai)
  57. {
  58. struct snd_soc_component *component = dai->component;
  59. int ret;
  60. ret = aiu_fifo_prepare(substream, dai);
  61. if (ret)
  62. return ret;
  63. snd_soc_component_update_bits(component,
  64. AIU_MEM_I2S_BUF_CNTL,
  65. AIU_MEM_I2S_BUF_CNTL_INIT,
  66. AIU_MEM_I2S_BUF_CNTL_INIT);
  67. snd_soc_component_update_bits(component,
  68. AIU_MEM_I2S_BUF_CNTL,
  69. AIU_MEM_I2S_BUF_CNTL_INIT, 0);
  70. return 0;
  71. }
  72. static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
  73. struct snd_pcm_hw_params *params,
  74. struct snd_soc_dai *dai)
  75. {
  76. struct snd_soc_component *component = dai->component;
  77. struct aiu_fifo *fifo = dai->playback_dma_data;
  78. unsigned int val;
  79. int ret;
  80. snd_soc_component_update_bits(component, AIU_I2S_MISC,
  81. AIU_I2S_MISC_HOLD_EN,
  82. AIU_I2S_MISC_HOLD_EN);
  83. ret = aiu_fifo_hw_params(substream, params, dai);
  84. if (ret)
  85. return ret;
  86. switch (params_physical_width(params)) {
  87. case 16:
  88. val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
  89. break;
  90. case 32:
  91. val = 0;
  92. break;
  93. default:
  94. dev_err(dai->dev, "Unsupported physical width %u\n",
  95. params_physical_width(params));
  96. return -EINVAL;
  97. }
  98. snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
  99. AIU_MEM_I2S_CONTROL_MODE_16BIT,
  100. val);
  101. /* Setup the irq periodicity */
  102. val = params_period_bytes(params) / fifo->fifo_block;
  103. val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
  104. snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
  105. AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
  106. /*
  107. * Most (all?) supported SoCs have this bit set by default. The vendor
  108. * driver however sets it manually (depending on the version either
  109. * while un-setting AIU_I2S_MISC_HOLD_EN or right before that). Follow
  110. * the same approach for consistency with the vendor driver.
  111. */
  112. snd_soc_component_update_bits(component, AIU_I2S_MISC,
  113. AIU_I2S_MISC_FORCE_LEFT_RIGHT,
  114. AIU_I2S_MISC_FORCE_LEFT_RIGHT);
  115. snd_soc_component_update_bits(component, AIU_I2S_MISC,
  116. AIU_I2S_MISC_HOLD_EN, 0);
  117. return 0;
  118. }
  119. const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
  120. .trigger = aiu_fifo_i2s_trigger,
  121. .prepare = aiu_fifo_i2s_prepare,
  122. .hw_params = aiu_fifo_i2s_hw_params,
  123. .hw_free = aiu_fifo_hw_free,
  124. .startup = aiu_fifo_startup,
  125. .shutdown = aiu_fifo_shutdown,
  126. };
  127. int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
  128. {
  129. struct snd_soc_component *component = dai->component;
  130. struct aiu *aiu = snd_soc_component_get_drvdata(component);
  131. struct aiu_fifo *fifo;
  132. int ret;
  133. ret = aiu_fifo_dai_probe(dai);
  134. if (ret)
  135. return ret;
  136. fifo = dai->playback_dma_data;
  137. fifo->pcm = &fifo_i2s_pcm;
  138. fifo->mem_offset = AIU_MEM_I2S_START;
  139. fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
  140. fifo->pclk = aiu->i2s.clks[PCLK].clk;
  141. fifo->irq = aiu->i2s.irq;
  142. return 0;
  143. }