img-parallel-out.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * IMG parallel output controller driver
  4. *
  5. * Copyright (C) 2015 Imagination Technologies Ltd.
  6. *
  7. * Author: Damien Horsley <Damien.Horsley@imgtec.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/reset.h>
  17. #include <sound/core.h>
  18. #include <sound/dmaengine_pcm.h>
  19. #include <sound/initval.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #define IMG_PRL_OUT_TX_FIFO 0
  24. #define IMG_PRL_OUT_CTL 0x4
  25. #define IMG_PRL_OUT_CTL_CH_MASK BIT(4)
  26. #define IMG_PRL_OUT_CTL_PACKH_MASK BIT(3)
  27. #define IMG_PRL_OUT_CTL_EDGE_MASK BIT(2)
  28. #define IMG_PRL_OUT_CTL_ME_MASK BIT(1)
  29. #define IMG_PRL_OUT_CTL_SRST_MASK BIT(0)
  30. struct img_prl_out {
  31. void __iomem *base;
  32. struct clk *clk_sys;
  33. struct clk *clk_ref;
  34. struct snd_dmaengine_dai_dma_data dma_data;
  35. struct device *dev;
  36. struct reset_control *rst;
  37. };
  38. static int img_prl_out_suspend(struct device *dev)
  39. {
  40. struct img_prl_out *prl = dev_get_drvdata(dev);
  41. clk_disable_unprepare(prl->clk_ref);
  42. return 0;
  43. }
  44. static int img_prl_out_resume(struct device *dev)
  45. {
  46. struct img_prl_out *prl = dev_get_drvdata(dev);
  47. int ret;
  48. ret = clk_prepare_enable(prl->clk_ref);
  49. if (ret) {
  50. dev_err(dev, "clk_enable failed: %d\n", ret);
  51. return ret;
  52. }
  53. return 0;
  54. }
  55. static inline void img_prl_out_writel(struct img_prl_out *prl,
  56. u32 val, u32 reg)
  57. {
  58. writel(val, prl->base + reg);
  59. }
  60. static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
  61. {
  62. return readl(prl->base + reg);
  63. }
  64. static void img_prl_out_reset(struct img_prl_out *prl)
  65. {
  66. u32 ctl;
  67. ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
  68. ~IMG_PRL_OUT_CTL_ME_MASK;
  69. reset_control_assert(prl->rst);
  70. reset_control_deassert(prl->rst);
  71. img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
  72. }
  73. static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
  74. struct snd_soc_dai *dai)
  75. {
  76. struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
  77. u32 reg;
  78. switch (cmd) {
  79. case SNDRV_PCM_TRIGGER_START:
  80. case SNDRV_PCM_TRIGGER_RESUME:
  81. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  82. reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
  83. reg |= IMG_PRL_OUT_CTL_ME_MASK;
  84. img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
  85. break;
  86. case SNDRV_PCM_TRIGGER_STOP:
  87. case SNDRV_PCM_TRIGGER_SUSPEND:
  88. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  89. img_prl_out_reset(prl);
  90. break;
  91. default:
  92. return -EINVAL;
  93. }
  94. return 0;
  95. }
  96. static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
  97. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  98. {
  99. struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
  100. unsigned int rate, channels;
  101. u32 reg, control_set = 0;
  102. rate = params_rate(params);
  103. channels = params_channels(params);
  104. switch (params_format(params)) {
  105. case SNDRV_PCM_FORMAT_S32_LE:
  106. control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
  107. break;
  108. case SNDRV_PCM_FORMAT_S24_LE:
  109. break;
  110. default:
  111. return -EINVAL;
  112. }
  113. if (channels != 2)
  114. return -EINVAL;
  115. clk_set_rate(prl->clk_ref, rate * 256);
  116. reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
  117. reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
  118. img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
  119. return 0;
  120. }
  121. static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  122. {
  123. struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
  124. u32 reg, control_set = 0;
  125. int ret;
  126. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  127. case SND_SOC_DAIFMT_NB_NF:
  128. break;
  129. case SND_SOC_DAIFMT_NB_IF:
  130. control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
  131. break;
  132. default:
  133. return -EINVAL;
  134. }
  135. ret = pm_runtime_get_sync(prl->dev);
  136. if (ret < 0) {
  137. pm_runtime_put_noidle(prl->dev);
  138. return ret;
  139. }
  140. reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
  141. reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
  142. img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
  143. pm_runtime_put(prl->dev);
  144. return 0;
  145. }
  146. static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
  147. .trigger = img_prl_out_trigger,
  148. .hw_params = img_prl_out_hw_params,
  149. .set_fmt = img_prl_out_set_fmt
  150. };
  151. static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
  152. {
  153. struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
  154. snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
  155. return 0;
  156. }
  157. static struct snd_soc_dai_driver img_prl_out_dai = {
  158. .probe = img_prl_out_dai_probe,
  159. .playback = {
  160. .channels_min = 2,
  161. .channels_max = 2,
  162. .rates = SNDRV_PCM_RATE_8000_192000,
  163. .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
  164. },
  165. .ops = &img_prl_out_dai_ops
  166. };
  167. static const struct snd_soc_component_driver img_prl_out_component = {
  168. .name = "img-prl-out"
  169. };
  170. static int img_prl_out_probe(struct platform_device *pdev)
  171. {
  172. struct img_prl_out *prl;
  173. struct resource *res;
  174. void __iomem *base;
  175. int ret;
  176. struct device *dev = &pdev->dev;
  177. prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
  178. if (!prl)
  179. return -ENOMEM;
  180. platform_set_drvdata(pdev, prl);
  181. prl->dev = &pdev->dev;
  182. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  183. base = devm_ioremap_resource(&pdev->dev, res);
  184. if (IS_ERR(base))
  185. return PTR_ERR(base);
  186. prl->base = base;
  187. prl->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
  188. if (IS_ERR(prl->rst)) {
  189. if (PTR_ERR(prl->rst) != -EPROBE_DEFER)
  190. dev_err(&pdev->dev, "No top level reset found\n");
  191. return PTR_ERR(prl->rst);
  192. }
  193. prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
  194. if (IS_ERR(prl->clk_sys)) {
  195. if (PTR_ERR(prl->clk_sys) != -EPROBE_DEFER)
  196. dev_err(dev, "Failed to acquire clock 'sys'\n");
  197. return PTR_ERR(prl->clk_sys);
  198. }
  199. prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
  200. if (IS_ERR(prl->clk_ref)) {
  201. if (PTR_ERR(prl->clk_ref) != -EPROBE_DEFER)
  202. dev_err(dev, "Failed to acquire clock 'ref'\n");
  203. return PTR_ERR(prl->clk_ref);
  204. }
  205. ret = clk_prepare_enable(prl->clk_sys);
  206. if (ret)
  207. return ret;
  208. img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
  209. img_prl_out_reset(prl);
  210. pm_runtime_enable(&pdev->dev);
  211. if (!pm_runtime_enabled(&pdev->dev)) {
  212. ret = img_prl_out_resume(&pdev->dev);
  213. if (ret)
  214. goto err_pm_disable;
  215. }
  216. prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
  217. prl->dma_data.addr_width = 4;
  218. prl->dma_data.maxburst = 4;
  219. ret = devm_snd_soc_register_component(&pdev->dev,
  220. &img_prl_out_component,
  221. &img_prl_out_dai, 1);
  222. if (ret)
  223. goto err_suspend;
  224. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  225. if (ret)
  226. goto err_suspend;
  227. return 0;
  228. err_suspend:
  229. if (!pm_runtime_status_suspended(&pdev->dev))
  230. img_prl_out_suspend(&pdev->dev);
  231. err_pm_disable:
  232. pm_runtime_disable(&pdev->dev);
  233. clk_disable_unprepare(prl->clk_sys);
  234. return ret;
  235. }
  236. static int img_prl_out_dev_remove(struct platform_device *pdev)
  237. {
  238. struct img_prl_out *prl = platform_get_drvdata(pdev);
  239. pm_runtime_disable(&pdev->dev);
  240. if (!pm_runtime_status_suspended(&pdev->dev))
  241. img_prl_out_suspend(&pdev->dev);
  242. clk_disable_unprepare(prl->clk_sys);
  243. return 0;
  244. }
  245. static const struct of_device_id img_prl_out_of_match[] = {
  246. { .compatible = "img,parallel-out" },
  247. {}
  248. };
  249. MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
  250. static const struct dev_pm_ops img_prl_out_pm_ops = {
  251. SET_RUNTIME_PM_OPS(img_prl_out_suspend,
  252. img_prl_out_resume, NULL)
  253. };
  254. static struct platform_driver img_prl_out_driver = {
  255. .driver = {
  256. .name = "img-parallel-out",
  257. .of_match_table = img_prl_out_of_match,
  258. .pm = &img_prl_out_pm_ops
  259. },
  260. .probe = img_prl_out_probe,
  261. .remove = img_prl_out_dev_remove
  262. };
  263. module_platform_driver(img_prl_out_driver);
  264. MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
  265. MODULE_DESCRIPTION("IMG Parallel Output Driver");
  266. MODULE_LICENSE("GPL v2");