img-i2s-out.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * IMG I2S output controller driver
  4. *
  5. * Copyright (C) 2015 Imagination Technologies Ltd.
  6. *
  7. * Author: Damien Horsley <Damien.Horsley@imgtec.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/reset.h>
  17. #include <sound/core.h>
  18. #include <sound/dmaengine_pcm.h>
  19. #include <sound/initval.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #define IMG_I2S_OUT_TX_FIFO 0x0
  24. #define IMG_I2S_OUT_CTL 0x4
  25. #define IMG_I2S_OUT_CTL_DATA_EN_MASK BIT(24)
  26. #define IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK 0xffe000
  27. #define IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT 13
  28. #define IMG_I2S_OUT_CTL_FRM_SIZE_MASK BIT(8)
  29. #define IMG_I2S_OUT_CTL_MASTER_MASK BIT(6)
  30. #define IMG_I2S_OUT_CTL_CLK_MASK BIT(5)
  31. #define IMG_I2S_OUT_CTL_CLK_EN_MASK BIT(4)
  32. #define IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK BIT(3)
  33. #define IMG_I2S_OUT_CTL_BCLK_POL_MASK BIT(2)
  34. #define IMG_I2S_OUT_CTL_ME_MASK BIT(0)
  35. #define IMG_I2S_OUT_CH_CTL 0x4
  36. #define IMG_I2S_OUT_CHAN_CTL_CH_MASK BIT(11)
  37. #define IMG_I2S_OUT_CHAN_CTL_LT_MASK BIT(10)
  38. #define IMG_I2S_OUT_CHAN_CTL_FMT_MASK 0xf0
  39. #define IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT 4
  40. #define IMG_I2S_OUT_CHAN_CTL_JUST_MASK BIT(3)
  41. #define IMG_I2S_OUT_CHAN_CTL_CLKT_MASK BIT(1)
  42. #define IMG_I2S_OUT_CHAN_CTL_ME_MASK BIT(0)
  43. #define IMG_I2S_OUT_CH_STRIDE 0x20
  44. struct img_i2s_out {
  45. void __iomem *base;
  46. struct clk *clk_sys;
  47. struct clk *clk_ref;
  48. struct snd_dmaengine_dai_dma_data dma_data;
  49. struct device *dev;
  50. unsigned int max_i2s_chan;
  51. void __iomem *channel_base;
  52. bool force_clk_active;
  53. unsigned int active_channels;
  54. struct reset_control *rst;
  55. struct snd_soc_dai_driver dai_driver;
  56. u32 suspend_ctl;
  57. u32 *suspend_ch_ctl;
  58. };
  59. static int img_i2s_out_runtime_suspend(struct device *dev)
  60. {
  61. struct img_i2s_out *i2s = dev_get_drvdata(dev);
  62. clk_disable_unprepare(i2s->clk_ref);
  63. clk_disable_unprepare(i2s->clk_sys);
  64. return 0;
  65. }
  66. static int img_i2s_out_runtime_resume(struct device *dev)
  67. {
  68. struct img_i2s_out *i2s = dev_get_drvdata(dev);
  69. int ret;
  70. ret = clk_prepare_enable(i2s->clk_sys);
  71. if (ret) {
  72. dev_err(dev, "clk_enable failed: %d\n", ret);
  73. return ret;
  74. }
  75. ret = clk_prepare_enable(i2s->clk_ref);
  76. if (ret) {
  77. dev_err(dev, "clk_enable failed: %d\n", ret);
  78. clk_disable_unprepare(i2s->clk_sys);
  79. return ret;
  80. }
  81. return 0;
  82. }
  83. static inline void img_i2s_out_writel(struct img_i2s_out *i2s, u32 val,
  84. u32 reg)
  85. {
  86. writel(val, i2s->base + reg);
  87. }
  88. static inline u32 img_i2s_out_readl(struct img_i2s_out *i2s, u32 reg)
  89. {
  90. return readl(i2s->base + reg);
  91. }
  92. static inline void img_i2s_out_ch_writel(struct img_i2s_out *i2s,
  93. u32 chan, u32 val, u32 reg)
  94. {
  95. writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
  96. }
  97. static inline u32 img_i2s_out_ch_readl(struct img_i2s_out *i2s, u32 chan,
  98. u32 reg)
  99. {
  100. return readl(i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
  101. }
  102. static inline void img_i2s_out_ch_disable(struct img_i2s_out *i2s, u32 chan)
  103. {
  104. u32 reg;
  105. reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
  106. reg &= ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
  107. img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
  108. }
  109. static inline void img_i2s_out_ch_enable(struct img_i2s_out *i2s, u32 chan)
  110. {
  111. u32 reg;
  112. reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);
  113. reg |= IMG_I2S_OUT_CHAN_CTL_ME_MASK;
  114. img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);
  115. }
  116. static inline void img_i2s_out_disable(struct img_i2s_out *i2s)
  117. {
  118. u32 reg;
  119. reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
  120. reg &= ~IMG_I2S_OUT_CTL_ME_MASK;
  121. img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
  122. }
  123. static inline void img_i2s_out_enable(struct img_i2s_out *i2s)
  124. {
  125. u32 reg;
  126. reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
  127. reg |= IMG_I2S_OUT_CTL_ME_MASK;
  128. img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
  129. }
  130. static void img_i2s_out_reset(struct img_i2s_out *i2s)
  131. {
  132. int i;
  133. u32 core_ctl, chan_ctl;
  134. core_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL) &
  135. ~IMG_I2S_OUT_CTL_ME_MASK &
  136. ~IMG_I2S_OUT_CTL_DATA_EN_MASK;
  137. if (!i2s->force_clk_active)
  138. core_ctl &= ~IMG_I2S_OUT_CTL_CLK_EN_MASK;
  139. chan_ctl = img_i2s_out_ch_readl(i2s, 0, IMG_I2S_OUT_CH_CTL) &
  140. ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;
  141. reset_control_assert(i2s->rst);
  142. reset_control_deassert(i2s->rst);
  143. for (i = 0; i < i2s->max_i2s_chan; i++)
  144. img_i2s_out_ch_writel(i2s, i, chan_ctl, IMG_I2S_OUT_CH_CTL);
  145. for (i = 0; i < i2s->active_channels; i++)
  146. img_i2s_out_ch_enable(i2s, i);
  147. img_i2s_out_writel(i2s, core_ctl, IMG_I2S_OUT_CTL);
  148. img_i2s_out_enable(i2s);
  149. }
  150. static int img_i2s_out_trigger(struct snd_pcm_substream *substream, int cmd,
  151. struct snd_soc_dai *dai)
  152. {
  153. struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
  154. u32 reg;
  155. switch (cmd) {
  156. case SNDRV_PCM_TRIGGER_START:
  157. case SNDRV_PCM_TRIGGER_RESUME:
  158. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  159. reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
  160. if (!i2s->force_clk_active)
  161. reg |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
  162. reg |= IMG_I2S_OUT_CTL_DATA_EN_MASK;
  163. img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
  164. break;
  165. case SNDRV_PCM_TRIGGER_STOP:
  166. case SNDRV_PCM_TRIGGER_SUSPEND:
  167. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  168. img_i2s_out_reset(i2s);
  169. break;
  170. default:
  171. return -EINVAL;
  172. }
  173. return 0;
  174. }
  175. static int img_i2s_out_hw_params(struct snd_pcm_substream *substream,
  176. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  177. {
  178. struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
  179. unsigned int channels, i2s_channels;
  180. long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
  181. int i;
  182. u32 reg, control_mask, control_set = 0;
  183. snd_pcm_format_t format;
  184. rate = params_rate(params);
  185. format = params_format(params);
  186. channels = params_channels(params);
  187. i2s_channels = channels / 2;
  188. if (format != SNDRV_PCM_FORMAT_S32_LE)
  189. return -EINVAL;
  190. if ((channels < 2) ||
  191. (channels > (i2s->max_i2s_chan * 2)) ||
  192. (channels % 2))
  193. return -EINVAL;
  194. pre_div_a = clk_round_rate(i2s->clk_ref, rate * 256);
  195. if (pre_div_a < 0)
  196. return pre_div_a;
  197. pre_div_b = clk_round_rate(i2s->clk_ref, rate * 384);
  198. if (pre_div_b < 0)
  199. return pre_div_b;
  200. diff_a = abs((pre_div_a / 256) - rate);
  201. diff_b = abs((pre_div_b / 384) - rate);
  202. /* If diffs are equal, use lower clock rate */
  203. if (diff_a > diff_b)
  204. clk_set_rate(i2s->clk_ref, pre_div_b);
  205. else
  206. clk_set_rate(i2s->clk_ref, pre_div_a);
  207. /*
  208. * Another driver (eg alsa machine driver) may have rejected the above
  209. * change. Get the current rate and set the register bit according to
  210. * the new minimum diff
  211. */
  212. clk_rate = clk_get_rate(i2s->clk_ref);
  213. diff_a = abs((clk_rate / 256) - rate);
  214. diff_b = abs((clk_rate / 384) - rate);
  215. if (diff_a > diff_b)
  216. control_set |= IMG_I2S_OUT_CTL_CLK_MASK;
  217. control_set |= ((i2s_channels - 1) <<
  218. IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT) &
  219. IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
  220. control_mask = IMG_I2S_OUT_CTL_CLK_MASK |
  221. IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK;
  222. img_i2s_out_disable(i2s);
  223. reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
  224. reg = (reg & ~control_mask) | control_set;
  225. img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
  226. for (i = 0; i < i2s_channels; i++)
  227. img_i2s_out_ch_enable(i2s, i);
  228. for (; i < i2s->max_i2s_chan; i++)
  229. img_i2s_out_ch_disable(i2s, i);
  230. img_i2s_out_enable(i2s);
  231. i2s->active_channels = i2s_channels;
  232. return 0;
  233. }
  234. static int img_i2s_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  235. {
  236. struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
  237. int i, ret;
  238. bool force_clk_active;
  239. u32 chan_control_mask, control_mask, chan_control_set = 0;
  240. u32 reg, control_set = 0;
  241. force_clk_active = ((fmt & SND_SOC_DAIFMT_CLOCK_MASK) ==
  242. SND_SOC_DAIFMT_CONT);
  243. if (force_clk_active)
  244. control_set |= IMG_I2S_OUT_CTL_CLK_EN_MASK;
  245. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  246. case SND_SOC_DAIFMT_CBM_CFM:
  247. break;
  248. case SND_SOC_DAIFMT_CBS_CFS:
  249. control_set |= IMG_I2S_OUT_CTL_MASTER_MASK;
  250. break;
  251. default:
  252. return -EINVAL;
  253. }
  254. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  255. case SND_SOC_DAIFMT_NB_NF:
  256. control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
  257. break;
  258. case SND_SOC_DAIFMT_NB_IF:
  259. control_set |= IMG_I2S_OUT_CTL_BCLK_POL_MASK;
  260. control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
  261. break;
  262. case SND_SOC_DAIFMT_IB_NF:
  263. break;
  264. case SND_SOC_DAIFMT_IB_IF:
  265. control_set |= IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
  266. break;
  267. default:
  268. return -EINVAL;
  269. }
  270. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  271. case SND_SOC_DAIFMT_I2S:
  272. chan_control_set |= IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
  273. break;
  274. case SND_SOC_DAIFMT_LEFT_J:
  275. break;
  276. default:
  277. return -EINVAL;
  278. }
  279. control_mask = IMG_I2S_OUT_CTL_CLK_EN_MASK |
  280. IMG_I2S_OUT_CTL_MASTER_MASK |
  281. IMG_I2S_OUT_CTL_BCLK_POL_MASK |
  282. IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK;
  283. chan_control_mask = IMG_I2S_OUT_CHAN_CTL_CLKT_MASK;
  284. ret = pm_runtime_get_sync(i2s->dev);
  285. if (ret < 0) {
  286. pm_runtime_put_noidle(i2s->dev);
  287. return ret;
  288. }
  289. img_i2s_out_disable(i2s);
  290. reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
  291. reg = (reg & ~control_mask) | control_set;
  292. img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
  293. for (i = 0; i < i2s->active_channels; i++)
  294. img_i2s_out_ch_disable(i2s, i);
  295. for (i = 0; i < i2s->max_i2s_chan; i++) {
  296. reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
  297. reg = (reg & ~chan_control_mask) | chan_control_set;
  298. img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
  299. }
  300. for (i = 0; i < i2s->active_channels; i++)
  301. img_i2s_out_ch_enable(i2s, i);
  302. img_i2s_out_enable(i2s);
  303. pm_runtime_put(i2s->dev);
  304. i2s->force_clk_active = force_clk_active;
  305. return 0;
  306. }
  307. static const struct snd_soc_dai_ops img_i2s_out_dai_ops = {
  308. .trigger = img_i2s_out_trigger,
  309. .hw_params = img_i2s_out_hw_params,
  310. .set_fmt = img_i2s_out_set_fmt
  311. };
  312. static int img_i2s_out_dai_probe(struct snd_soc_dai *dai)
  313. {
  314. struct img_i2s_out *i2s = snd_soc_dai_get_drvdata(dai);
  315. snd_soc_dai_init_dma_data(dai, &i2s->dma_data, NULL);
  316. return 0;
  317. }
  318. static const struct snd_soc_component_driver img_i2s_out_component = {
  319. .name = "img-i2s-out"
  320. };
  321. static int img_i2s_out_dma_prepare_slave_config(struct snd_pcm_substream *st,
  322. struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
  323. {
  324. unsigned int i2s_channels = params_channels(params) / 2;
  325. struct snd_soc_pcm_runtime *rtd = st->private_data;
  326. struct snd_dmaengine_dai_dma_data *dma_data;
  327. int ret;
  328. dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
  329. ret = snd_hwparams_to_dma_slave_config(st, params, sc);
  330. if (ret)
  331. return ret;
  332. sc->dst_addr = dma_data->addr;
  333. sc->dst_addr_width = dma_data->addr_width;
  334. sc->dst_maxburst = 4 * i2s_channels;
  335. return 0;
  336. }
  337. static const struct snd_dmaengine_pcm_config img_i2s_out_dma_config = {
  338. .prepare_slave_config = img_i2s_out_dma_prepare_slave_config
  339. };
  340. static int img_i2s_out_probe(struct platform_device *pdev)
  341. {
  342. struct img_i2s_out *i2s;
  343. struct resource *res;
  344. void __iomem *base;
  345. int i, ret;
  346. unsigned int max_i2s_chan_pow_2;
  347. u32 reg;
  348. struct device *dev = &pdev->dev;
  349. i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
  350. if (!i2s)
  351. return -ENOMEM;
  352. platform_set_drvdata(pdev, i2s);
  353. i2s->dev = &pdev->dev;
  354. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  355. base = devm_ioremap_resource(&pdev->dev, res);
  356. if (IS_ERR(base))
  357. return PTR_ERR(base);
  358. i2s->base = base;
  359. if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
  360. &i2s->max_i2s_chan)) {
  361. dev_err(&pdev->dev, "No img,i2s-channels property\n");
  362. return -EINVAL;
  363. }
  364. max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
  365. i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
  366. i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
  367. if (IS_ERR(i2s->rst)) {
  368. if (PTR_ERR(i2s->rst) != -EPROBE_DEFER)
  369. dev_err(&pdev->dev, "No top level reset found\n");
  370. return PTR_ERR(i2s->rst);
  371. }
  372. i2s->clk_sys = devm_clk_get(&pdev->dev, "sys");
  373. if (IS_ERR(i2s->clk_sys)) {
  374. if (PTR_ERR(i2s->clk_sys) != -EPROBE_DEFER)
  375. dev_err(dev, "Failed to acquire clock 'sys'\n");
  376. return PTR_ERR(i2s->clk_sys);
  377. }
  378. i2s->clk_ref = devm_clk_get(&pdev->dev, "ref");
  379. if (IS_ERR(i2s->clk_ref)) {
  380. if (PTR_ERR(i2s->clk_ref) != -EPROBE_DEFER)
  381. dev_err(dev, "Failed to acquire clock 'ref'\n");
  382. return PTR_ERR(i2s->clk_ref);
  383. }
  384. i2s->suspend_ch_ctl = devm_kcalloc(dev,
  385. i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
  386. if (!i2s->suspend_ch_ctl)
  387. return -ENOMEM;
  388. pm_runtime_enable(&pdev->dev);
  389. if (!pm_runtime_enabled(&pdev->dev)) {
  390. ret = img_i2s_out_runtime_resume(&pdev->dev);
  391. if (ret)
  392. goto err_pm_disable;
  393. }
  394. ret = pm_runtime_get_sync(&pdev->dev);
  395. if (ret < 0) {
  396. pm_runtime_put_noidle(&pdev->dev);
  397. goto err_suspend;
  398. }
  399. reg = IMG_I2S_OUT_CTL_FRM_SIZE_MASK;
  400. img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);
  401. reg = IMG_I2S_OUT_CHAN_CTL_JUST_MASK |
  402. IMG_I2S_OUT_CHAN_CTL_LT_MASK |
  403. IMG_I2S_OUT_CHAN_CTL_CH_MASK |
  404. (8 << IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT);
  405. for (i = 0; i < i2s->max_i2s_chan; i++)
  406. img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
  407. img_i2s_out_reset(i2s);
  408. pm_runtime_put(&pdev->dev);
  409. i2s->active_channels = 1;
  410. i2s->dma_data.addr = res->start + IMG_I2S_OUT_TX_FIFO;
  411. i2s->dma_data.addr_width = 4;
  412. i2s->dma_data.maxburst = 4;
  413. i2s->dai_driver.probe = img_i2s_out_dai_probe;
  414. i2s->dai_driver.playback.channels_min = 2;
  415. i2s->dai_driver.playback.channels_max = i2s->max_i2s_chan * 2;
  416. i2s->dai_driver.playback.rates = SNDRV_PCM_RATE_8000_192000;
  417. i2s->dai_driver.playback.formats = SNDRV_PCM_FMTBIT_S32_LE;
  418. i2s->dai_driver.ops = &img_i2s_out_dai_ops;
  419. ret = devm_snd_soc_register_component(&pdev->dev,
  420. &img_i2s_out_component, &i2s->dai_driver, 1);
  421. if (ret)
  422. goto err_suspend;
  423. ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
  424. &img_i2s_out_dma_config, 0);
  425. if (ret)
  426. goto err_suspend;
  427. return 0;
  428. err_suspend:
  429. if (!pm_runtime_status_suspended(&pdev->dev))
  430. img_i2s_out_runtime_suspend(&pdev->dev);
  431. err_pm_disable:
  432. pm_runtime_disable(&pdev->dev);
  433. return ret;
  434. }
  435. static int img_i2s_out_dev_remove(struct platform_device *pdev)
  436. {
  437. pm_runtime_disable(&pdev->dev);
  438. if (!pm_runtime_status_suspended(&pdev->dev))
  439. img_i2s_out_runtime_suspend(&pdev->dev);
  440. return 0;
  441. }
  442. #ifdef CONFIG_PM_SLEEP
  443. static int img_i2s_out_suspend(struct device *dev)
  444. {
  445. struct img_i2s_out *i2s = dev_get_drvdata(dev);
  446. int i, ret;
  447. u32 reg;
  448. if (pm_runtime_status_suspended(dev)) {
  449. ret = img_i2s_out_runtime_resume(dev);
  450. if (ret)
  451. return ret;
  452. }
  453. for (i = 0; i < i2s->max_i2s_chan; i++) {
  454. reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);
  455. i2s->suspend_ch_ctl[i] = reg;
  456. }
  457. i2s->suspend_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);
  458. img_i2s_out_runtime_suspend(dev);
  459. return 0;
  460. }
  461. static int img_i2s_out_resume(struct device *dev)
  462. {
  463. struct img_i2s_out *i2s = dev_get_drvdata(dev);
  464. int i, ret;
  465. u32 reg;
  466. ret = img_i2s_out_runtime_resume(dev);
  467. if (ret)
  468. return ret;
  469. for (i = 0; i < i2s->max_i2s_chan; i++) {
  470. reg = i2s->suspend_ch_ctl[i];
  471. img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);
  472. }
  473. img_i2s_out_writel(i2s, i2s->suspend_ctl, IMG_I2S_OUT_CTL);
  474. if (pm_runtime_status_suspended(dev))
  475. img_i2s_out_runtime_suspend(dev);
  476. return 0;
  477. }
  478. #endif
  479. static const struct of_device_id img_i2s_out_of_match[] = {
  480. { .compatible = "img,i2s-out" },
  481. {}
  482. };
  483. MODULE_DEVICE_TABLE(of, img_i2s_out_of_match);
  484. static const struct dev_pm_ops img_i2s_out_pm_ops = {
  485. SET_RUNTIME_PM_OPS(img_i2s_out_runtime_suspend,
  486. img_i2s_out_runtime_resume, NULL)
  487. SET_SYSTEM_SLEEP_PM_OPS(img_i2s_out_suspend, img_i2s_out_resume)
  488. };
  489. static struct platform_driver img_i2s_out_driver = {
  490. .driver = {
  491. .name = "img-i2s-out",
  492. .of_match_table = img_i2s_out_of_match,
  493. .pm = &img_i2s_out_pm_ops
  494. },
  495. .probe = img_i2s_out_probe,
  496. .remove = img_i2s_out_dev_remove
  497. };
  498. module_platform_driver(img_i2s_out_driver);
  499. MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
  500. MODULE_DESCRIPTION("IMG I2S Output Driver");
  501. MODULE_LICENSE("GPL v2");