img-i2s-in.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * IMG I2S input controller driver
  4. *
  5. * Copyright (C) 2015 Imagination Technologies Ltd.
  6. *
  7. * Author: Damien Horsley <Damien.Horsley@imgtec.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/reset.h>
  17. #include <sound/core.h>
  18. #include <sound/dmaengine_pcm.h>
  19. #include <sound/initval.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #define IMG_I2S_IN_RX_FIFO 0x0
  24. #define IMG_I2S_IN_CTL 0x4
  25. #define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK 0xfffffffc
  26. #define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT 2
  27. #define IMG_I2S_IN_CTL_16PACK_MASK BIT(1)
  28. #define IMG_I2S_IN_CTL_ME_MASK BIT(0)
  29. #define IMG_I2S_IN_CH_CTL 0x4
  30. #define IMG_I2S_IN_CH_CTL_CCDEL_MASK 0x38000
  31. #define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT 15
  32. #define IMG_I2S_IN_CH_CTL_FEN_MASK BIT(14)
  33. #define IMG_I2S_IN_CH_CTL_FMODE_MASK BIT(13)
  34. #define IMG_I2S_IN_CH_CTL_16PACK_MASK BIT(12)
  35. #define IMG_I2S_IN_CH_CTL_JUST_MASK BIT(10)
  36. #define IMG_I2S_IN_CH_CTL_PACKH_MASK BIT(9)
  37. #define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK BIT(8)
  38. #define IMG_I2S_IN_CH_CTL_BLKP_MASK BIT(7)
  39. #define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK BIT(6)
  40. #define IMG_I2S_IN_CH_CTL_LRD_MASK BIT(3)
  41. #define IMG_I2S_IN_CH_CTL_FW_MASK BIT(2)
  42. #define IMG_I2S_IN_CH_CTL_SW_MASK BIT(1)
  43. #define IMG_I2S_IN_CH_CTL_ME_MASK BIT(0)
  44. #define IMG_I2S_IN_CH_STRIDE 0x20
  45. struct img_i2s_in {
  46. void __iomem *base;
  47. struct clk *clk_sys;
  48. struct snd_dmaengine_dai_dma_data dma_data;
  49. struct device *dev;
  50. unsigned int max_i2s_chan;
  51. void __iomem *channel_base;
  52. unsigned int active_channels;
  53. struct snd_soc_dai_driver dai_driver;
  54. u32 suspend_ctl;
  55. u32 *suspend_ch_ctl;
  56. };
  57. static int img_i2s_in_runtime_suspend(struct device *dev)
  58. {
  59. struct img_i2s_in *i2s = dev_get_drvdata(dev);
  60. clk_disable_unprepare(i2s->clk_sys);
  61. return 0;
  62. }
  63. static int img_i2s_in_runtime_resume(struct device *dev)
  64. {
  65. struct img_i2s_in *i2s = dev_get_drvdata(dev);
  66. int ret;
  67. ret = clk_prepare_enable(i2s->clk_sys);
  68. if (ret) {
  69. dev_err(dev, "Unable to enable sys clock\n");
  70. return ret;
  71. }
  72. return 0;
  73. }
  74. static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
  75. {
  76. writel(val, i2s->base + reg);
  77. }
  78. static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
  79. {
  80. return readl(i2s->base + reg);
  81. }
  82. static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
  83. u32 val, u32 reg)
  84. {
  85. writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
  86. }
  87. static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
  88. u32 reg)
  89. {
  90. return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
  91. }
  92. static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
  93. {
  94. u32 reg;
  95. reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
  96. reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
  97. img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
  98. }
  99. static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
  100. {
  101. u32 reg;
  102. reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
  103. reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
  104. img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
  105. }
  106. static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
  107. {
  108. u32 reg;
  109. reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
  110. reg &= ~IMG_I2S_IN_CTL_ME_MASK;
  111. img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
  112. }
  113. static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
  114. {
  115. u32 reg;
  116. reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
  117. reg |= IMG_I2S_IN_CTL_ME_MASK;
  118. img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
  119. }
  120. static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
  121. {
  122. int i;
  123. u32 reg;
  124. for (i = 0; i < i2s->active_channels; i++) {
  125. reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
  126. reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
  127. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  128. reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
  129. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  130. }
  131. }
  132. static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
  133. struct snd_soc_dai *dai)
  134. {
  135. struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
  136. switch (cmd) {
  137. case SNDRV_PCM_TRIGGER_START:
  138. case SNDRV_PCM_TRIGGER_RESUME:
  139. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  140. img_i2s_in_enable(i2s);
  141. break;
  142. case SNDRV_PCM_TRIGGER_STOP:
  143. case SNDRV_PCM_TRIGGER_SUSPEND:
  144. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  145. img_i2s_in_disable(i2s);
  146. break;
  147. default:
  148. return -EINVAL;
  149. }
  150. return 0;
  151. }
  152. static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
  153. unsigned int sample_rate, unsigned int frame_size,
  154. unsigned int *bclk_filter_enable,
  155. unsigned int *bclk_filter_value)
  156. {
  157. unsigned int bclk_freq, cur_freq;
  158. bclk_freq = sample_rate * frame_size;
  159. cur_freq = clk_get_rate(i2s->clk_sys);
  160. if (cur_freq >= bclk_freq * 8) {
  161. *bclk_filter_enable = 1;
  162. *bclk_filter_value = 0;
  163. } else if (cur_freq >= bclk_freq * 7) {
  164. *bclk_filter_enable = 1;
  165. *bclk_filter_value = 1;
  166. } else if (cur_freq >= bclk_freq * 6) {
  167. *bclk_filter_enable = 0;
  168. *bclk_filter_value = 0;
  169. } else {
  170. dev_err(i2s->dev,
  171. "Sys clock rate %u insufficient for sample rate %u\n",
  172. cur_freq, sample_rate);
  173. return -EINVAL;
  174. }
  175. return 0;
  176. }
  177. static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
  178. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  179. {
  180. struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
  181. unsigned int rate, channels, i2s_channels, frame_size;
  182. unsigned int bclk_filter_enable, bclk_filter_value;
  183. int i, ret = 0;
  184. u32 reg, control_mask, chan_control_mask;
  185. u32 control_set = 0, chan_control_set = 0;
  186. snd_pcm_format_t format;
  187. rate = params_rate(params);
  188. format = params_format(params);
  189. channels = params_channels(params);
  190. i2s_channels = channels / 2;
  191. switch (format) {
  192. case SNDRV_PCM_FORMAT_S32_LE:
  193. frame_size = 64;
  194. chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
  195. chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
  196. chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
  197. break;
  198. case SNDRV_PCM_FORMAT_S24_LE:
  199. frame_size = 64;
  200. chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
  201. chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
  202. break;
  203. case SNDRV_PCM_FORMAT_S16_LE:
  204. frame_size = 32;
  205. control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
  206. chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
  207. break;
  208. default:
  209. return -EINVAL;
  210. }
  211. if ((channels < 2) ||
  212. (channels > (i2s->max_i2s_chan * 2)) ||
  213. (channels % 2))
  214. return -EINVAL;
  215. control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
  216. ret = img_i2s_in_check_rate(i2s, rate, frame_size,
  217. &bclk_filter_enable, &bclk_filter_value);
  218. if (ret < 0)
  219. return ret;
  220. if (bclk_filter_enable)
  221. chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
  222. if (bclk_filter_value)
  223. chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
  224. control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
  225. IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
  226. chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
  227. IMG_I2S_IN_CH_CTL_FEN_MASK |
  228. IMG_I2S_IN_CH_CTL_FMODE_MASK |
  229. IMG_I2S_IN_CH_CTL_SW_MASK |
  230. IMG_I2S_IN_CH_CTL_FW_MASK |
  231. IMG_I2S_IN_CH_CTL_PACKH_MASK;
  232. reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
  233. reg = (reg & ~control_mask) | control_set;
  234. img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
  235. for (i = 0; i < i2s->active_channels; i++)
  236. img_i2s_in_ch_disable(i2s, i);
  237. for (i = 0; i < i2s->max_i2s_chan; i++) {
  238. reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
  239. reg = (reg & ~chan_control_mask) | chan_control_set;
  240. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  241. }
  242. i2s->active_channels = i2s_channels;
  243. img_i2s_in_flush(i2s);
  244. for (i = 0; i < i2s->active_channels; i++)
  245. img_i2s_in_ch_enable(i2s, i);
  246. return 0;
  247. }
  248. static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  249. {
  250. struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
  251. int i, ret;
  252. u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
  253. u32 reg;
  254. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  255. case SND_SOC_DAIFMT_NB_NF:
  256. lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
  257. break;
  258. case SND_SOC_DAIFMT_NB_IF:
  259. break;
  260. case SND_SOC_DAIFMT_IB_NF:
  261. lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
  262. blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
  263. break;
  264. case SND_SOC_DAIFMT_IB_IF:
  265. blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
  266. break;
  267. default:
  268. return -EINVAL;
  269. }
  270. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  271. case SND_SOC_DAIFMT_I2S:
  272. chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
  273. break;
  274. case SND_SOC_DAIFMT_LEFT_J:
  275. break;
  276. default:
  277. return -EINVAL;
  278. }
  279. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  280. case SND_SOC_DAIFMT_CBM_CFM:
  281. break;
  282. default:
  283. return -EINVAL;
  284. }
  285. chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
  286. ret = pm_runtime_get_sync(i2s->dev);
  287. if (ret < 0) {
  288. pm_runtime_put_noidle(i2s->dev);
  289. return ret;
  290. }
  291. for (i = 0; i < i2s->active_channels; i++)
  292. img_i2s_in_ch_disable(i2s, i);
  293. /*
  294. * BLKP and LRD must be set during separate register writes
  295. */
  296. for (i = 0; i < i2s->max_i2s_chan; i++) {
  297. reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
  298. reg = (reg & ~chan_control_mask) | chan_control_set;
  299. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  300. reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
  301. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  302. reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
  303. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  304. }
  305. for (i = 0; i < i2s->active_channels; i++)
  306. img_i2s_in_ch_enable(i2s, i);
  307. pm_runtime_put(i2s->dev);
  308. return 0;
  309. }
  310. static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
  311. .trigger = img_i2s_in_trigger,
  312. .hw_params = img_i2s_in_hw_params,
  313. .set_fmt = img_i2s_in_set_fmt
  314. };
  315. static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
  316. {
  317. struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
  318. snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
  319. return 0;
  320. }
  321. static const struct snd_soc_component_driver img_i2s_in_component = {
  322. .name = "img-i2s-in"
  323. };
  324. static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
  325. struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
  326. {
  327. unsigned int i2s_channels = params_channels(params) / 2;
  328. struct snd_soc_pcm_runtime *rtd = st->private_data;
  329. struct snd_dmaengine_dai_dma_data *dma_data;
  330. int ret;
  331. dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
  332. ret = snd_hwparams_to_dma_slave_config(st, params, sc);
  333. if (ret)
  334. return ret;
  335. sc->src_addr = dma_data->addr;
  336. sc->src_addr_width = dma_data->addr_width;
  337. sc->src_maxburst = 4 * i2s_channels;
  338. return 0;
  339. }
  340. static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
  341. .prepare_slave_config = img_i2s_in_dma_prepare_slave_config
  342. };
  343. static int img_i2s_in_probe(struct platform_device *pdev)
  344. {
  345. struct img_i2s_in *i2s;
  346. struct resource *res;
  347. void __iomem *base;
  348. int ret, i;
  349. struct reset_control *rst;
  350. unsigned int max_i2s_chan_pow_2;
  351. struct device *dev = &pdev->dev;
  352. i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
  353. if (!i2s)
  354. return -ENOMEM;
  355. platform_set_drvdata(pdev, i2s);
  356. i2s->dev = dev;
  357. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  358. base = devm_ioremap_resource(dev, res);
  359. if (IS_ERR(base))
  360. return PTR_ERR(base);
  361. i2s->base = base;
  362. if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
  363. &i2s->max_i2s_chan)) {
  364. dev_err(dev, "No img,i2s-channels property\n");
  365. return -EINVAL;
  366. }
  367. max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
  368. i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
  369. i2s->clk_sys = devm_clk_get(dev, "sys");
  370. if (IS_ERR(i2s->clk_sys)) {
  371. if (PTR_ERR(i2s->clk_sys) != -EPROBE_DEFER)
  372. dev_err(dev, "Failed to acquire clock 'sys'\n");
  373. return PTR_ERR(i2s->clk_sys);
  374. }
  375. pm_runtime_enable(&pdev->dev);
  376. if (!pm_runtime_enabled(&pdev->dev)) {
  377. ret = img_i2s_in_runtime_resume(&pdev->dev);
  378. if (ret)
  379. goto err_pm_disable;
  380. }
  381. ret = pm_runtime_resume_and_get(&pdev->dev);
  382. if (ret < 0)
  383. goto err_suspend;
  384. i2s->active_channels = 1;
  385. i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
  386. i2s->dma_data.addr_width = 4;
  387. i2s->dai_driver.probe = img_i2s_in_dai_probe;
  388. i2s->dai_driver.capture.channels_min = 2;
  389. i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
  390. i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
  391. i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
  392. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
  393. i2s->dai_driver.ops = &img_i2s_in_dai_ops;
  394. rst = devm_reset_control_get_exclusive(dev, "rst");
  395. if (IS_ERR(rst)) {
  396. if (PTR_ERR(rst) == -EPROBE_DEFER) {
  397. ret = -EPROBE_DEFER;
  398. pm_runtime_put(&pdev->dev);
  399. goto err_suspend;
  400. }
  401. dev_dbg(dev, "No top level reset found\n");
  402. img_i2s_in_disable(i2s);
  403. for (i = 0; i < i2s->max_i2s_chan; i++)
  404. img_i2s_in_ch_disable(i2s, i);
  405. } else {
  406. reset_control_assert(rst);
  407. reset_control_deassert(rst);
  408. }
  409. img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
  410. for (i = 0; i < i2s->max_i2s_chan; i++)
  411. img_i2s_in_ch_writel(i2s, i,
  412. (4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
  413. IMG_I2S_IN_CH_CTL_JUST_MASK |
  414. IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
  415. pm_runtime_put(&pdev->dev);
  416. i2s->suspend_ch_ctl = devm_kcalloc(dev,
  417. i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
  418. if (!i2s->suspend_ch_ctl) {
  419. ret = -ENOMEM;
  420. goto err_suspend;
  421. }
  422. ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
  423. &i2s->dai_driver, 1);
  424. if (ret)
  425. goto err_suspend;
  426. ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
  427. if (ret)
  428. goto err_suspend;
  429. return 0;
  430. err_suspend:
  431. if (!pm_runtime_enabled(&pdev->dev))
  432. img_i2s_in_runtime_suspend(&pdev->dev);
  433. err_pm_disable:
  434. pm_runtime_disable(&pdev->dev);
  435. return ret;
  436. }
  437. static int img_i2s_in_dev_remove(struct platform_device *pdev)
  438. {
  439. pm_runtime_disable(&pdev->dev);
  440. if (!pm_runtime_status_suspended(&pdev->dev))
  441. img_i2s_in_runtime_suspend(&pdev->dev);
  442. return 0;
  443. }
  444. #ifdef CONFIG_PM_SLEEP
  445. static int img_i2s_in_suspend(struct device *dev)
  446. {
  447. struct img_i2s_in *i2s = dev_get_drvdata(dev);
  448. int i, ret;
  449. u32 reg;
  450. if (pm_runtime_status_suspended(dev)) {
  451. ret = img_i2s_in_runtime_resume(dev);
  452. if (ret)
  453. return ret;
  454. }
  455. for (i = 0; i < i2s->max_i2s_chan; i++) {
  456. reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
  457. i2s->suspend_ch_ctl[i] = reg;
  458. }
  459. i2s->suspend_ctl = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
  460. img_i2s_in_runtime_suspend(dev);
  461. return 0;
  462. }
  463. static int img_i2s_in_resume(struct device *dev)
  464. {
  465. struct img_i2s_in *i2s = dev_get_drvdata(dev);
  466. int i, ret;
  467. u32 reg;
  468. ret = img_i2s_in_runtime_resume(dev);
  469. if (ret)
  470. return ret;
  471. for (i = 0; i < i2s->max_i2s_chan; i++) {
  472. reg = i2s->suspend_ch_ctl[i];
  473. img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
  474. }
  475. img_i2s_in_writel(i2s, i2s->suspend_ctl, IMG_I2S_IN_CTL);
  476. if (pm_runtime_status_suspended(dev))
  477. img_i2s_in_runtime_suspend(dev);
  478. return 0;
  479. }
  480. #endif
  481. static const struct of_device_id img_i2s_in_of_match[] = {
  482. { .compatible = "img,i2s-in" },
  483. {}
  484. };
  485. MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
  486. static const struct dev_pm_ops img_i2s_in_pm_ops = {
  487. SET_RUNTIME_PM_OPS(img_i2s_in_runtime_suspend,
  488. img_i2s_in_runtime_resume, NULL)
  489. SET_SYSTEM_SLEEP_PM_OPS(img_i2s_in_suspend, img_i2s_in_resume)
  490. };
  491. static struct platform_driver img_i2s_in_driver = {
  492. .driver = {
  493. .name = "img-i2s-in",
  494. .of_match_table = img_i2s_in_of_match,
  495. .pm = &img_i2s_in_pm_ops
  496. },
  497. .probe = img_i2s_in_probe,
  498. .remove = img_i2s_in_dev_remove
  499. };
  500. module_platform_driver(img_i2s_in_driver);
  501. MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
  502. MODULE_DESCRIPTION("IMG I2S Input Driver");
  503. MODULE_LICENSE("GPL v2");