hi6210-i2s.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/sound/soc/hisilicon/hi6210-i2s.h
  4. *
  5. * Copyright (C) 2015 Linaro, Ltd
  6. * Author: Andy Green <andy.green@linaro.org>
  7. *
  8. * Note at least on 6220, S2 == BT, S1 == Digital FM Radio IF
  9. */
  10. #ifndef _HI6210_I2S_H
  11. #define _HI6210_I2S_H
  12. #define HII2S_SW_RST_N 0
  13. #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT 28
  14. #define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK 3
  15. #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT 26
  16. #define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK 3
  17. #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT 24
  18. #define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK 3
  19. #define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT 20
  20. #define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK 3
  21. #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT 18
  22. #define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK 3
  23. #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT 16
  24. #define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK 3
  25. #define HII2S_SW_RST_N__SW_RST_N BIT(0)
  26. enum hi6210_bits {
  27. HII2S_BITS_16,
  28. HII2S_BITS_18,
  29. HII2S_BITS_20,
  30. HII2S_BITS_24,
  31. };
  32. #define HII2S_IF_CLK_EN_CFG 4
  33. #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
  34. #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
  35. #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
  36. #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
  37. #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
  38. #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
  39. #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13)
  40. #define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN BIT(12)
  41. #define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN BIT(10)
  42. #define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN BIT(9)
  43. #define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN BIT(8)
  44. #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN BIT(7)
  45. #define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN BIT(6)
  46. #define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN BIT(5)
  47. #define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN BIT(4)
  48. #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN BIT(3)
  49. #define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN BIT(2)
  50. #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN BIT(1)
  51. #define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN BIT(0)
  52. #define HII2S_DIG_FILTER_CLK_EN_CFG 8
  53. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN BIT(30)
  54. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN BIT(28)
  55. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN BIT(25)
  56. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN BIT(24)
  57. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN BIT(22)
  58. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN BIT(20)
  59. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN BIT(17)
  60. #define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN BIT(16)
  61. #define HII2S_FS_CFG 0xc
  62. #define HII2S_FS_CFG__FS_S2_SHIFT 28
  63. #define HII2S_FS_CFG__FS_S2_MASK 7
  64. #define HII2S_FS_CFG__FS_S1_SHIFT 24
  65. #define HII2S_FS_CFG__FS_S1_MASK 7
  66. #define HII2S_FS_CFG__FS_ADCLR_SHIFT 20
  67. #define HII2S_FS_CFG__FS_ADCLR_MASK 7
  68. #define HII2S_FS_CFG__FS_DACLR_SHIFT 16
  69. #define HII2S_FS_CFG__FS_DACLR_MASK 7
  70. #define HII2S_FS_CFG__FS_ST_DL_R_SHIFT 8
  71. #define HII2S_FS_CFG__FS_ST_DL_R_MASK 7
  72. #define HII2S_FS_CFG__FS_ST_DL_L_SHIFT 4
  73. #define HII2S_FS_CFG__FS_ST_DL_L_MASK 7
  74. #define HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT 0
  75. #define HII2S_FS_CFG__FS_VOICE_DLINK_MASK 7
  76. enum hi6210_i2s_rates {
  77. HII2S_FS_RATE_8KHZ = 0,
  78. HII2S_FS_RATE_16KHZ = 1,
  79. HII2S_FS_RATE_32KHZ = 2,
  80. HII2S_FS_RATE_48KHZ = 4,
  81. HII2S_FS_RATE_96KHZ = 5,
  82. HII2S_FS_RATE_192KHZ = 6,
  83. };
  84. #define HII2S_I2S_CFG 0x10
  85. #define HII2S_I2S_CFG__S2_IF_TX_EN BIT(31)
  86. #define HII2S_I2S_CFG__S2_IF_RX_EN BIT(30)
  87. #define HII2S_I2S_CFG__S2_FRAME_MODE BIT(29)
  88. #define HII2S_I2S_CFG__S2_MST_SLV BIT(28)
  89. #define HII2S_I2S_CFG__S2_LRCK_MODE BIT(27)
  90. #define HII2S_I2S_CFG__S2_CHNNL_MODE BIT(26)
  91. #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT 24
  92. #define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK 3
  93. #define HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT 22
  94. #define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK 3
  95. #define HII2S_I2S_CFG__S2_TX_CLK_SEL BIT(21)
  96. #define HII2S_I2S_CFG__S2_RX_CLK_SEL BIT(20)
  97. #define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT BIT(19)
  98. #define HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT 16
  99. #define HII2S_I2S_CFG__S2_FUNC_MODE_MASK 7
  100. #define HII2S_I2S_CFG__S1_IF_TX_EN BIT(15)
  101. #define HII2S_I2S_CFG__S1_IF_RX_EN BIT(14)
  102. #define HII2S_I2S_CFG__S1_FRAME_MODE BIT(13)
  103. #define HII2S_I2S_CFG__S1_MST_SLV BIT(12)
  104. #define HII2S_I2S_CFG__S1_LRCK_MODE BIT(11)
  105. #define HII2S_I2S_CFG__S1_CHNNL_MODE BIT(10)
  106. #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT 8
  107. #define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK 3
  108. #define HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT 6
  109. #define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK 3
  110. #define HII2S_I2S_CFG__S1_TX_CLK_SEL BIT(5)
  111. #define HII2S_I2S_CFG__S1_RX_CLK_SEL BIT(4)
  112. #define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT BIT(3)
  113. #define HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT 0
  114. #define HII2S_I2S_CFG__S1_FUNC_MODE_MASK 7
  115. enum hi6210_i2s_formats {
  116. HII2S_FORMAT_I2S,
  117. HII2S_FORMAT_PCM_STD,
  118. HII2S_FORMAT_PCM_USER,
  119. HII2S_FORMAT_LEFT_JUST,
  120. HII2S_FORMAT_RIGHT_JUST,
  121. };
  122. #define HII2S_DIG_FILTER_MODULE_CFG 0x14
  123. #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT 28
  124. #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK 3
  125. #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE BIT(27)
  126. #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE BIT(26)
  127. #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE BIT(25)
  128. #define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE BIT(24)
  129. #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT 20
  130. #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK 3
  131. #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE BIT(19)
  132. #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE BIT(18)
  133. #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE BIT(17)
  134. #define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE BIT(16)
  135. #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER BIT(9)
  136. #define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER BIT(8)
  137. #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT 4
  138. #define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK 7
  139. #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT 0
  140. #define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK 7
  141. enum hi6210_gains {
  142. HII2S_GAIN_100PC,
  143. HII2S_GAIN_50PC,
  144. HII2S_GAIN_25PC,
  145. };
  146. #define HII2S_MUX_TOP_MODULE_CFG 0x18
  147. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT 14
  148. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK 3
  149. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE BIT(13)
  150. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE BIT(12)
  151. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT 10
  152. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK 3
  153. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE BIT(9)
  154. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE BIT(8)
  155. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY BIT(6)
  156. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT 4
  157. #define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK 3
  158. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY BIT(3)
  159. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT 0
  160. #define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK 7
  161. enum hi6210_s2_src_mode {
  162. HII2S_S2_SRC_MODE_3,
  163. HII2S_S2_SRC_MODE_12,
  164. HII2S_S2_SRC_MODE_6,
  165. HII2S_S2_SRC_MODE_2,
  166. };
  167. enum hi6210_voice_dlink_src_mode {
  168. HII2S_VOICE_DL_SRC_MODE_12 = 1,
  169. HII2S_VOICE_DL_SRC_MODE_6,
  170. HII2S_VOICE_DL_SRC_MODE_2,
  171. HII2S_VOICE_DL_SRC_MODE_3,
  172. };
  173. #define HII2S_ADC_PGA_CFG 0x1c
  174. #define HII2S_S1_INPUT_PGA_CFG 0x20
  175. #define HII2S_S2_INPUT_PGA_CFG 0x24
  176. #define HII2S_ST_DL_PGA_CFG 0x28
  177. #define HII2S_VOICE_SIDETONE_DLINK_PGA_CFG 0x2c
  178. #define HII2S_APB_AFIFO_CFG_1 0x30
  179. #define HII2S_APB_AFIFO_CFG_2 0x34
  180. #define HII2S_ST_DL_FIFO_TH_CFG 0x38
  181. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT 24
  182. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK 0x1f
  183. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT 16
  184. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK 0x1f
  185. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT 8
  186. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK 0x1f
  187. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT 0
  188. #define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK 0x1f
  189. #define HII2S_STEREO_UPLINK_FIFO_TH_CFG 0x3c
  190. #define HII2S_VOICE_UPLINK_FIFO_TH_CFG 0x40
  191. #define HII2S_CODEC_IRQ_MASK 0x44
  192. #define HII2S_CODEC_IRQ 0x48
  193. #define HII2S_DACL_AGC_CFG_1 0x4c
  194. #define HII2S_DACL_AGC_CFG_2 0x50
  195. #define HII2S_DACR_AGC_CFG_1 0x54
  196. #define HII2S_DACR_AGC_CFG_2 0x58
  197. #define HII2S_DMIC_SIF_CFG 0x5c
  198. #define HII2S_MISC_CFG 0x60
  199. #define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL BIT(17)
  200. #define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL BIT(16)
  201. #define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL BIT(14)
  202. #define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL BIT(13)
  203. #define HII2S_MISC_CFG__S3_DIN_TEST_SEL BIT(12)
  204. #define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL BIT(8)
  205. #define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL BIT(7)
  206. #define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL BIT(6)
  207. #define HII2S_MISC_CFG__ST_DL_TEST_SEL BIT(4)
  208. #define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL BIT(3)
  209. #define HII2S_MISC_CFG__S2_DOUT_TEST_SEL BIT(2)
  210. #define HII2S_MISC_CFG__S1_DOUT_TEST_SEL BIT(1)
  211. #define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL BIT(0)
  212. #define HII2S_S2_SRC_CFG 0x64
  213. #define HII2S_MEM_CFG 0x68
  214. #define HII2S_THIRDMD_PCM_PGA_CFG 0x6c
  215. #define HII2S_THIRD_MODEM_FIFO_TH 0x70
  216. #define HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT 0x74
  217. #define HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT 0x78
  218. #define HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT 0x7c
  219. #define HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT 0x80
  220. #define HII2S_ANTI_FREQ_JITTER_EN 0x84
  221. #define HII2S_CLK_SEL 0x88
  222. /* 0 = BT owns the i2s */
  223. #define HII2S_CLK_SEL__I2S_BT_FM_SEL BIT(0)
  224. /* 0 = internal source, 1 = ext */
  225. #define HII2S_CLK_SEL__EXT_12_288MHZ_SEL BIT(1)
  226. #define HII2S_THIRDMD_DLINK_CHANNEL 0xe8
  227. #define HII2S_THIRDMD_ULINK_CHANNEL 0xec
  228. #define HII2S_VOICE_DLINK_CHANNEL 0xf0
  229. /* shovel data in here for playback */
  230. #define HII2S_ST_DL_CHANNEL 0xf4
  231. #define HII2S_STEREO_UPLINK_CHANNEL 0xf8
  232. #define HII2S_VOICE_UPLINK_CHANNEL 0xfc
  233. #endif/* _HI6210_I2S_H */