hi6210-i2s.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
  4. *
  5. * Copyright (C) 2015 Linaro, Ltd
  6. * Author: Andy Green <andy.green@linaro.org>
  7. *
  8. * This driver only deals with S2 interface (BT)
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/device.h>
  13. #include <linux/delay.h>
  14. #include <linux/clk.h>
  15. #include <linux/jiffies.h>
  16. #include <linux/io.h>
  17. #include <linux/gpio.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/dmaengine_pcm.h>
  22. #include <sound/initval.h>
  23. #include <sound/soc.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/reset.h>
  26. #include <linux/of_address.h>
  27. #include <linux/of_irq.h>
  28. #include <linux/mfd/syscon.h>
  29. #include <linux/reset-controller.h>
  30. #include "hi6210-i2s.h"
  31. struct hi6210_i2s {
  32. struct device *dev;
  33. struct reset_control *rc;
  34. struct clk *clk[8];
  35. int clocks;
  36. struct snd_soc_dai_driver dai;
  37. void __iomem *base;
  38. struct regmap *sysctrl;
  39. phys_addr_t base_phys;
  40. struct snd_dmaengine_dai_dma_data dma_data[2];
  41. int clk_rate;
  42. spinlock_t lock;
  43. int rate;
  44. int format;
  45. u8 bits;
  46. u8 channels;
  47. u8 id;
  48. u8 channel_length;
  49. u8 use;
  50. u32 master:1;
  51. u32 status:1;
  52. };
  53. #define SC_PERIPH_CLKEN1 0x210
  54. #define SC_PERIPH_CLKDIS1 0x214
  55. #define SC_PERIPH_CLKEN3 0x230
  56. #define SC_PERIPH_CLKDIS3 0x234
  57. #define SC_PERIPH_CLKEN12 0x270
  58. #define SC_PERIPH_CLKDIS12 0x274
  59. #define SC_PERIPH_RSTEN1 0x310
  60. #define SC_PERIPH_RSTDIS1 0x314
  61. #define SC_PERIPH_RSTSTAT1 0x318
  62. #define SC_PERIPH_RSTEN2 0x320
  63. #define SC_PERIPH_RSTDIS2 0x324
  64. #define SC_PERIPH_RSTSTAT2 0x328
  65. #define SOC_PMCTRL_BBPPLLALIAS 0x48
  66. enum {
  67. CLK_DACODEC,
  68. CLK_I2S_BASE,
  69. };
  70. static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
  71. {
  72. writel(val, i2s->base + reg);
  73. }
  74. static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
  75. {
  76. return readl(i2s->base + reg);
  77. }
  78. static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
  79. struct snd_soc_dai *cpu_dai)
  80. {
  81. struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  82. int ret, n;
  83. u32 val;
  84. /* deassert reset on ABB */
  85. regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
  86. if (val & BIT(4))
  87. regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
  88. for (n = 0; n < i2s->clocks; n++) {
  89. ret = clk_prepare_enable(i2s->clk[n]);
  90. if (ret)
  91. goto err_unprepare_clk;
  92. }
  93. ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
  94. if (ret) {
  95. dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
  96. __func__, ret);
  97. goto err_unprepare_clk;
  98. }
  99. /* enable clock before frequency division */
  100. regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
  101. /* enable codec working clock / == "codec bus clock" */
  102. regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
  103. /* deassert reset on codec / interface clock / working clock */
  104. regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
  105. regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
  106. /* not interested in i2s irqs */
  107. val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
  108. val |= 0x3f;
  109. hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
  110. /* reset the stereo downlink fifo */
  111. val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
  112. val |= (BIT(5) | BIT(4));
  113. hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
  114. val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
  115. val &= ~(BIT(5) | BIT(4));
  116. hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
  117. val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
  118. val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
  119. HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
  120. val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
  121. hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
  122. val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
  123. /* mux 11/12 = APB not i2s */
  124. val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
  125. /* BT R ch 0 = mixer op of DACR ch */
  126. val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
  127. val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
  128. val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
  129. /* BT L ch = 1 = mux 7 = "mixer output of DACL */
  130. val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
  131. hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
  132. val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
  133. val |= HII2S_SW_RST_N__SW_RST_N;
  134. hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
  135. return 0;
  136. err_unprepare_clk:
  137. while (n--)
  138. clk_disable_unprepare(i2s->clk[n]);
  139. return ret;
  140. }
  141. static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
  142. struct snd_soc_dai *cpu_dai)
  143. {
  144. struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  145. int n;
  146. for (n = 0; n < i2s->clocks; n++)
  147. clk_disable_unprepare(i2s->clk[n]);
  148. regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
  149. }
  150. static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
  151. {
  152. struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  153. u32 val;
  154. spin_lock(&i2s->lock);
  155. if (on) {
  156. /* enable S2 TX */
  157. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  158. val |= HII2S_I2S_CFG__S2_IF_TX_EN;
  159. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  160. } else {
  161. /* disable S2 TX */
  162. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  163. val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
  164. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  165. }
  166. spin_unlock(&i2s->lock);
  167. }
  168. static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
  169. {
  170. struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  171. u32 val;
  172. spin_lock(&i2s->lock);
  173. if (on) {
  174. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  175. val |= HII2S_I2S_CFG__S2_IF_RX_EN;
  176. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  177. } else {
  178. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  179. val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
  180. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  181. }
  182. spin_unlock(&i2s->lock);
  183. }
  184. static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  185. {
  186. struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  187. /*
  188. * We don't actually set the hardware until the hw_params
  189. * call, but we need to validate the user input here.
  190. */
  191. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  192. case SND_SOC_DAIFMT_CBM_CFM:
  193. case SND_SOC_DAIFMT_CBS_CFS:
  194. break;
  195. default:
  196. return -EINVAL;
  197. }
  198. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  199. case SND_SOC_DAIFMT_I2S:
  200. case SND_SOC_DAIFMT_LEFT_J:
  201. case SND_SOC_DAIFMT_RIGHT_J:
  202. break;
  203. default:
  204. return -EINVAL;
  205. }
  206. i2s->format = fmt;
  207. i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
  208. SND_SOC_DAIFMT_CBS_CFS;
  209. return 0;
  210. }
  211. static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
  212. struct snd_pcm_hw_params *params,
  213. struct snd_soc_dai *cpu_dai)
  214. {
  215. struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  216. u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
  217. u32 val;
  218. struct snd_dmaengine_dai_dma_data *dma_data;
  219. switch (params_format(params)) {
  220. case SNDRV_PCM_FORMAT_U16_LE:
  221. signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
  222. fallthrough;
  223. case SNDRV_PCM_FORMAT_S16_LE:
  224. bits = HII2S_BITS_16;
  225. break;
  226. case SNDRV_PCM_FORMAT_U24_LE:
  227. signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
  228. fallthrough;
  229. case SNDRV_PCM_FORMAT_S24_LE:
  230. bits = HII2S_BITS_24;
  231. break;
  232. default:
  233. dev_err(cpu_dai->dev, "Bad format\n");
  234. return -EINVAL;
  235. }
  236. switch (params_rate(params)) {
  237. case 8000:
  238. rate = HII2S_FS_RATE_8KHZ;
  239. break;
  240. case 16000:
  241. rate = HII2S_FS_RATE_16KHZ;
  242. break;
  243. case 32000:
  244. rate = HII2S_FS_RATE_32KHZ;
  245. break;
  246. case 48000:
  247. rate = HII2S_FS_RATE_48KHZ;
  248. break;
  249. case 96000:
  250. rate = HII2S_FS_RATE_96KHZ;
  251. break;
  252. case 192000:
  253. rate = HII2S_FS_RATE_192KHZ;
  254. break;
  255. default:
  256. dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
  257. return -EINVAL;
  258. }
  259. if (!(params_channels(params))) {
  260. dev_err(cpu_dai->dev, "Bad channels\n");
  261. return -EINVAL;
  262. }
  263. dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
  264. switch (bits) {
  265. case HII2S_BITS_24:
  266. i2s->bits = 32;
  267. dma_data->addr_width = 3;
  268. break;
  269. default:
  270. i2s->bits = 16;
  271. dma_data->addr_width = 2;
  272. break;
  273. }
  274. i2s->rate = params_rate(params);
  275. i2s->channels = params_channels(params);
  276. i2s->channel_length = i2s->channels * i2s->bits;
  277. val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
  278. val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
  279. HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
  280. (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
  281. HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
  282. (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
  283. HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
  284. (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
  285. HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
  286. val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
  287. (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
  288. (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
  289. (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
  290. hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
  291. val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
  292. val |= (BIT(19) | BIT(18) | BIT(17) |
  293. HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
  294. HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
  295. HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
  296. HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
  297. HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
  298. hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
  299. val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
  300. val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
  301. HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
  302. HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
  303. HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
  304. HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
  305. HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
  306. val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
  307. HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
  308. hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
  309. val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
  310. val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
  311. HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
  312. hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
  313. val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
  314. val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
  315. HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
  316. HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
  317. HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
  318. hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
  319. switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
  320. case SND_SOC_DAIFMT_CBM_CFM:
  321. i2s->master = false;
  322. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  323. val |= HII2S_I2S_CFG__S2_MST_SLV;
  324. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  325. break;
  326. case SND_SOC_DAIFMT_CBS_CFS:
  327. i2s->master = true;
  328. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  329. val &= ~HII2S_I2S_CFG__S2_MST_SLV;
  330. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  331. break;
  332. default:
  333. WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
  334. return -EINVAL;
  335. }
  336. switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
  337. case SND_SOC_DAIFMT_I2S:
  338. fmt = HII2S_FORMAT_I2S;
  339. break;
  340. case SND_SOC_DAIFMT_LEFT_J:
  341. fmt = HII2S_FORMAT_LEFT_JUST;
  342. break;
  343. case SND_SOC_DAIFMT_RIGHT_J:
  344. fmt = HII2S_FORMAT_RIGHT_JUST;
  345. break;
  346. default:
  347. WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
  348. return -EINVAL;
  349. }
  350. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  351. val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
  352. HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
  353. val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
  354. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  355. val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
  356. val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
  357. HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
  358. hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
  359. dma_data->maxburst = 2;
  360. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  361. dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
  362. else
  363. dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
  364. switch (i2s->channels) {
  365. case 1:
  366. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  367. val |= HII2S_I2S_CFG__S2_FRAME_MODE;
  368. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  369. break;
  370. default:
  371. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  372. val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
  373. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  374. break;
  375. }
  376. /* clear loopback, set signed type and word length */
  377. val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
  378. val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
  379. val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
  380. HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
  381. val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
  382. HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
  383. val |= signed_data;
  384. val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
  385. hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
  386. if (!i2s->master)
  387. return 0;
  388. /* set DAC and related units to correct rate */
  389. val = hi6210_read_reg(i2s, HII2S_FS_CFG);
  390. val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
  391. val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
  392. val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
  393. HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
  394. val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
  395. HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
  396. val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
  397. val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
  398. val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
  399. val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
  400. hi6210_write_reg(i2s, HII2S_FS_CFG, val);
  401. return 0;
  402. }
  403. static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  404. struct snd_soc_dai *cpu_dai)
  405. {
  406. pr_debug("%s\n", __func__);
  407. switch (cmd) {
  408. case SNDRV_PCM_TRIGGER_START:
  409. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  410. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  411. hi6210_i2s_rxctrl(cpu_dai, 1);
  412. else
  413. hi6210_i2s_txctrl(cpu_dai, 1);
  414. break;
  415. case SNDRV_PCM_TRIGGER_STOP:
  416. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  417. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  418. hi6210_i2s_rxctrl(cpu_dai, 0);
  419. else
  420. hi6210_i2s_txctrl(cpu_dai, 0);
  421. break;
  422. default:
  423. dev_err(cpu_dai->dev, "unknown cmd\n");
  424. return -EINVAL;
  425. }
  426. return 0;
  427. }
  428. static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
  429. {
  430. struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  431. snd_soc_dai_init_dma_data(dai,
  432. &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
  433. &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
  434. return 0;
  435. }
  436. static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
  437. .trigger = hi6210_i2s_trigger,
  438. .hw_params = hi6210_i2s_hw_params,
  439. .set_fmt = hi6210_i2s_set_fmt,
  440. .startup = hi6210_i2s_startup,
  441. .shutdown = hi6210_i2s_shutdown,
  442. };
  443. static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
  444. .probe = hi6210_i2s_dai_probe,
  445. .playback = {
  446. .channels_min = 2,
  447. .channels_max = 2,
  448. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  449. SNDRV_PCM_FMTBIT_U16_LE,
  450. .rates = SNDRV_PCM_RATE_48000,
  451. },
  452. .capture = {
  453. .channels_min = 2,
  454. .channels_max = 2,
  455. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  456. SNDRV_PCM_FMTBIT_U16_LE,
  457. .rates = SNDRV_PCM_RATE_48000,
  458. },
  459. .ops = &hi6210_i2s_dai_ops,
  460. };
  461. static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
  462. .name = "hi6210_i2s-i2s",
  463. };
  464. static int hi6210_i2s_probe(struct platform_device *pdev)
  465. {
  466. struct device_node *node = pdev->dev.of_node;
  467. struct device *dev = &pdev->dev;
  468. struct hi6210_i2s *i2s;
  469. struct resource *res;
  470. int ret;
  471. i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
  472. if (!i2s)
  473. return -ENOMEM;
  474. i2s->dev = dev;
  475. spin_lock_init(&i2s->lock);
  476. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  477. i2s->base = devm_ioremap_resource(dev, res);
  478. if (IS_ERR(i2s->base))
  479. return PTR_ERR(i2s->base);
  480. i2s->base_phys = (phys_addr_t)res->start;
  481. i2s->dai = hi6210_i2s_dai_init;
  482. dev_set_drvdata(dev, i2s);
  483. i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
  484. "hisilicon,sysctrl-syscon");
  485. if (IS_ERR(i2s->sysctrl))
  486. return PTR_ERR(i2s->sysctrl);
  487. i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec");
  488. if (IS_ERR(i2s->clk[CLK_DACODEC]))
  489. return PTR_ERR(i2s->clk[CLK_DACODEC]);
  490. i2s->clocks++;
  491. i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base");
  492. if (IS_ERR(i2s->clk[CLK_I2S_BASE]))
  493. return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
  494. i2s->clocks++;
  495. ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
  496. if (ret)
  497. return ret;
  498. ret = devm_snd_soc_register_component(dev, &hi6210_i2s_i2s_comp,
  499. &i2s->dai, 1);
  500. return ret;
  501. }
  502. static const struct of_device_id hi6210_i2s_dt_ids[] = {
  503. { .compatible = "hisilicon,hi6210-i2s" },
  504. { /* sentinel */ }
  505. };
  506. MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
  507. static struct platform_driver hi6210_i2s_driver = {
  508. .probe = hi6210_i2s_probe,
  509. .driver = {
  510. .name = "hi6210_i2s",
  511. .of_match_table = hi6210_i2s_dt_ids,
  512. },
  513. };
  514. module_platform_driver(hi6210_i2s_driver);
  515. MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
  516. MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
  517. MODULE_LICENSE("GPL");