hi3660-i2s.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899
  1. /* SPDX-License-Identifier: GPL-2.0+
  2. *
  3. * linux/sound/soc/hisilicon/hi3660-i2s.c
  4. *
  5. * I2S IP driver for hi3660.
  6. *
  7. * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
  8. *
  9. */
  10. #ifndef _HI3660_I2S_H
  11. #define _HI3660_I2S_H
  12. enum hisi_bits {
  13. HII2S_BITS_16,
  14. HII2S_BITS_18,
  15. HII2S_BITS_20,
  16. HII2S_BITS_24,
  17. };
  18. enum hisi_i2s_rates {
  19. HII2S_FS_RATE_8KHZ = 0,
  20. HII2S_FS_RATE_16KHZ = 1,
  21. HII2S_FS_RATE_32KHZ = 2,
  22. HII2S_FS_RATE_48KHZ = 4,
  23. HII2S_FS_RATE_96KHZ = 5,
  24. HII2S_FS_RATE_192KHZ = 6,
  25. };
  26. #define HI_ASP_CFG_R_RST_CTRLEN_REG 0x0
  27. #define HI_ASP_CFG_R_RST_CTRLDIS_REG 0x4
  28. #define HI_ASP_CFG_R_GATE_EN_REG 0xC
  29. #define HI_ASP_CFG_R_GATE_DIS_REG 0x10
  30. #define HI_ASP_CFG_R_GATE_CLKEN_REG 0x14
  31. #define HI_ASP_CFG_R_GATE_CLKSTAT_REG 0x18
  32. #define HI_ASP_CFG_R_GATE_CLKDIV_EN_REG 0x1C
  33. #define HI_ASP_CFG_R_CLK1_DIV_REG 0x20
  34. #define HI_ASP_CFG_R_CLK2_DIV_REG 0x24
  35. #define HI_ASP_CFG_R_CLK3_DIV_REG 0x28
  36. #define HI_ASP_CFG_R_CLK4_DIV_REG 0x2C
  37. #define HI_ASP_CFG_R_CLK5_DIV_REG 0x30
  38. #define HI_ASP_CFG_R_CLK6_DIV_REG 0x34
  39. #define HI_ASP_CFG_R_CLK_SEL_REG 0x38
  40. #define HI_ASP_CFG_R_SEC_REG 0x100
  41. #define HI_ASP_SIO_VERSION_REG (0x3C)
  42. #define HI_ASP_SIO_MODE_REG (0x40)
  43. #define HI_ASP_SIO_INTSTATUS_REG (0x44)
  44. #define HI_ASP_SIO_INTCLR_REG (0x48)
  45. #define HI_ASP_SIO_I2S_LEFT_XD_REG (0x4C)
  46. #define HI_ASP_SIO_I2S_RIGHT_XD_REG (0x50)
  47. #define HI_ASP_SIO_I2S_LEFT_RD_REG (0x54)
  48. #define HI_ASP_SIO_I2S_RIGHT_RD_REG (0x58)
  49. #define HI_ASP_SIO_CT_SET_REG (0x5C)
  50. #define HI_ASP_SIO_CT_CLR_REG (0x60)
  51. #define HI_ASP_SIO_RX_STA_REG (0x68)
  52. #define HI_ASP_SIO_TX_STA_REG (0x6C)
  53. #define HI_ASP_SIO_DATA_WIDTH_SET_REG (0x78)
  54. #define HI_ASP_SIO_I2S_START_POS_REG (0x7C)
  55. #define HI_ASP_SIO_I2S_POS_FLAG_REG (0x80)
  56. #define HI_ASP_SIO_SIGNED_EXT_REG (0x84)
  57. #define HI_ASP_SIO_I2S_POS_MERGE_EN_REG (0x88)
  58. #define HI_ASP_SIO_INTMASK_REG (0x8C)
  59. #define HI_ASP_SIO_I2S_DUAL_RX_CHN_REG (0xA0)
  60. #define HI_ASP_SIO_I2S_DUAL_TX_CHN_REG (0xC0)
  61. #define HI_ASP_CFG_R_CLK_SEL_EN BIT(2)
  62. #define HI_ASP_CFG_R_CLK_SEL 0x140010
  63. #define HI_ASP_CFG_R_CLK1_DIV_SEL 0xbcdc9a
  64. #define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff000f
  65. #define HI_ASP_CFG_R_CLK6_DIV_SEL 0x00ff003f
  66. #define HI_ASP_CFG_SIO_MODE 0
  67. #define HI_ASP_SIO_MODE_SEL_EN BIT(0)
  68. #define HI_ASP_MASK 0xffffffff
  69. #define HI_ASP_SIO_RX_ENABLE BIT(13)
  70. #define HI_ASP_SIO_TX_ENABLE BIT(12)
  71. #define HI_ASP_SIO_RX_FIFO_DISABLE BIT(11)
  72. #define HI_ASP_SIO_TX_FIFO_DISABLE BIT(10)
  73. #define HI_ASP_SIO_RX_DATA_MERGE BIT(9)
  74. #define HI_ASP_SIO_TX_DATA_MERGE BIT(8)
  75. #define HI_ASP_SIO_RX_FIFO_THRESHOLD (0x5 << 4)
  76. #define HI_ASP_SIO_TX_FIFO_THRESHOLD (0xB << 0)
  77. #define HI_ASP_SIO_RX_FIFO_THRESHOLD_CLR (0xF << 4)
  78. #define HI_ASP_SIO_TX_FIFO_THRESHOLD_CLR (0xF << 0)
  79. #define HI_ASP_SIO_BURST (0x4)
  80. enum hisi_i2s_formats {
  81. HII2S_FORMAT_I2S,
  82. HII2S_FORMAT_PCM_STD,
  83. HII2S_FORMAT_PCM_USER,
  84. HII2S_FORMAT_LEFT_JUST,
  85. HII2S_FORMAT_RIGHT_JUST,
  86. };
  87. #endif/* _HI3660_I2S_H */