hi3660-i2s.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * linux/sound/soc/hisilicon/hi3660-i2s.c
  4. *
  5. * I2S IP driver for hi3660.
  6. *
  7. * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/device.h>
  12. #include <linux/delay.h>
  13. #include <linux/clk.h>
  14. #include <linux/jiffies.h>
  15. #include <linux/io.h>
  16. #include <linux/gpio.h>
  17. #include <sound/core.h>
  18. #include <sound/pcm.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/dmaengine_pcm.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/reset.h>
  25. #include <linux/of_address.h>
  26. #include <linux/of_irq.h>
  27. #include <linux/reset-controller.h>
  28. #include <linux/clk.h>
  29. #include <linux/regulator/consumer.h>
  30. #include "hi3660-i2s.h"
  31. struct hi3660_i2s {
  32. struct device *dev;
  33. struct reset_control *rc;
  34. int clocks;
  35. struct regulator *regu_asp;
  36. struct pinctrl *pctrl;
  37. struct pinctrl_state *pin_default;
  38. struct pinctrl_state *pin_idle;
  39. struct clk *asp_subsys_clk;
  40. struct snd_soc_dai_driver dai;
  41. void __iomem *base;
  42. void __iomem *base_syscon;
  43. phys_addr_t base_phys;
  44. struct snd_dmaengine_dai_dma_data dma_data[2];
  45. spinlock_t lock;
  46. int rate;
  47. int format;
  48. int bits;
  49. int channels;
  50. u32 master;
  51. u32 status;
  52. };
  53. static void update_bits(struct hi3660_i2s *i2s, u32 ofs, u32 reset, u32 set)
  54. {
  55. u32 val = readl(i2s->base + ofs) & ~reset;
  56. writel(val | set, i2s->base + ofs);
  57. }
  58. static void update_bits_syscon(struct hi3660_i2s *i2s,
  59. u32 ofs, u32 reset, u32 set)
  60. {
  61. u32 val = readl(i2s->base_syscon + ofs) & ~reset;
  62. writel(val | set, i2s->base_syscon + ofs);
  63. }
  64. static int enable_format(struct hi3660_i2s *i2s,
  65. struct snd_pcm_substream *substream)
  66. {
  67. switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
  68. case SND_SOC_DAIFMT_CBM_CFM:
  69. i2s->master = false;
  70. update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
  71. 0, HI_ASP_CFG_R_CLK_SEL_EN);
  72. break;
  73. case SND_SOC_DAIFMT_CBS_CFS:
  74. i2s->master = true;
  75. update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
  76. HI_ASP_CFG_R_CLK_SEL_EN, 0);
  77. break;
  78. default:
  79. return -EINVAL;
  80. }
  81. return 0;
  82. }
  83. static int startup(struct snd_pcm_substream *substream,
  84. struct snd_soc_dai *cpu_dai)
  85. {
  86. struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  87. /* deassert reset on sio_bt*/
  88. update_bits_syscon(i2s, HI_ASP_CFG_R_RST_CTRLDIS_REG,
  89. 0, BIT(2)|BIT(6)|BIT(8)|BIT(16));
  90. /* enable clk before frequency division */
  91. update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_EN_REG,
  92. 0, BIT(5)|BIT(6));
  93. /* enable frequency division */
  94. update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_CLKDIV_EN_REG,
  95. 0, BIT(2)|BIT(5));
  96. /* select clk */
  97. update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
  98. HI_ASP_MASK, HI_ASP_CFG_R_CLK_SEL);
  99. /* select clk_div */
  100. update_bits_syscon(i2s, HI_ASP_CFG_R_CLK1_DIV_REG,
  101. HI_ASP_MASK, HI_ASP_CFG_R_CLK1_DIV_SEL);
  102. update_bits_syscon(i2s, HI_ASP_CFG_R_CLK4_DIV_REG,
  103. HI_ASP_MASK, HI_ASP_CFG_R_CLK4_DIV_SEL);
  104. update_bits_syscon(i2s, HI_ASP_CFG_R_CLK6_DIV_REG,
  105. HI_ASP_MASK, HI_ASP_CFG_R_CLK6_DIV_SEL);
  106. /* sio config */
  107. update_bits(i2s, HI_ASP_SIO_MODE_REG, HI_ASP_MASK, 0x0);
  108. update_bits(i2s, HI_ASP_SIO_DATA_WIDTH_SET_REG, HI_ASP_MASK, 0x9);
  109. update_bits(i2s, HI_ASP_SIO_I2S_POS_MERGE_EN_REG, HI_ASP_MASK, 0x1);
  110. update_bits(i2s, HI_ASP_SIO_I2S_START_POS_REG, HI_ASP_MASK, 0x0);
  111. return 0;
  112. }
  113. static void shutdown(struct snd_pcm_substream *substream,
  114. struct snd_soc_dai *cpu_dai)
  115. {
  116. struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  117. if (!IS_ERR_OR_NULL(i2s->asp_subsys_clk))
  118. clk_disable_unprepare(i2s->asp_subsys_clk);
  119. }
  120. static void txctrl(struct snd_soc_dai *cpu_dai, int on)
  121. {
  122. struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  123. spin_lock(&i2s->lock);
  124. if (on) {
  125. /* enable SIO TX */
  126. update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
  127. HI_ASP_SIO_TX_ENABLE |
  128. HI_ASP_SIO_TX_DATA_MERGE |
  129. HI_ASP_SIO_TX_FIFO_THRESHOLD |
  130. HI_ASP_SIO_RX_ENABLE |
  131. HI_ASP_SIO_RX_DATA_MERGE |
  132. HI_ASP_SIO_RX_FIFO_THRESHOLD);
  133. } else {
  134. /* disable SIO TX */
  135. update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
  136. HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
  137. }
  138. spin_unlock(&i2s->lock);
  139. }
  140. static void rxctrl(struct snd_soc_dai *cpu_dai, int on)
  141. {
  142. struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  143. spin_lock(&i2s->lock);
  144. if (on)
  145. /* enable SIO RX */
  146. update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
  147. HI_ASP_SIO_TX_ENABLE |
  148. HI_ASP_SIO_TX_DATA_MERGE |
  149. HI_ASP_SIO_TX_FIFO_THRESHOLD |
  150. HI_ASP_SIO_RX_ENABLE |
  151. HI_ASP_SIO_RX_DATA_MERGE |
  152. HI_ASP_SIO_RX_FIFO_THRESHOLD);
  153. else
  154. /* disable SIO RX */
  155. update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
  156. HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
  157. spin_unlock(&i2s->lock);
  158. }
  159. static int set_sysclk(struct snd_soc_dai *cpu_dai,
  160. int clk_id, unsigned int freq, int dir)
  161. {
  162. return 0;
  163. }
  164. static int set_format(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  165. {
  166. struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  167. i2s->format = fmt;
  168. i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
  169. SND_SOC_DAIFMT_CBS_CFS;
  170. return 0;
  171. }
  172. static int hw_params(struct snd_pcm_substream *substream,
  173. struct snd_pcm_hw_params *params,
  174. struct snd_soc_dai *cpu_dai)
  175. {
  176. struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
  177. struct snd_dmaengine_dai_dma_data *dma_data;
  178. dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
  179. enable_format(i2s, substream);
  180. dma_data->maxburst = 4;
  181. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  182. dma_data->addr = i2s->base_phys +
  183. HI_ASP_SIO_I2S_DUAL_TX_CHN_REG;
  184. else
  185. dma_data->addr = i2s->base_phys +
  186. HI_ASP_SIO_I2S_DUAL_RX_CHN_REG;
  187. switch (params_format(params)) {
  188. case SNDRV_PCM_FORMAT_U16_LE:
  189. case SNDRV_PCM_FORMAT_S16_LE:
  190. i2s->bits = 16;
  191. dma_data->addr_width = 4;
  192. break;
  193. case SNDRV_PCM_FORMAT_U24_LE:
  194. case SNDRV_PCM_FORMAT_S24_LE:
  195. i2s->bits = 32;
  196. dma_data->addr_width = 4;
  197. break;
  198. default:
  199. dev_err(cpu_dai->dev, "Bad format\n");
  200. return -EINVAL;
  201. }
  202. return 0;
  203. }
  204. static int trigger(struct snd_pcm_substream *substream, int cmd,
  205. struct snd_soc_dai *cpu_dai)
  206. {
  207. switch (cmd) {
  208. case SNDRV_PCM_TRIGGER_START:
  209. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  210. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  211. rxctrl(cpu_dai, 1);
  212. else
  213. txctrl(cpu_dai, 1);
  214. break;
  215. case SNDRV_PCM_TRIGGER_STOP:
  216. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  217. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  218. rxctrl(cpu_dai, 0);
  219. else
  220. txctrl(cpu_dai, 0);
  221. break;
  222. default:
  223. dev_err(cpu_dai->dev, "unknown cmd\n");
  224. return -EINVAL;
  225. }
  226. return 0;
  227. }
  228. static int dai_probe(struct snd_soc_dai *dai)
  229. {
  230. struct hi3660_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  231. snd_soc_dai_init_dma_data(dai,
  232. &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
  233. &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
  234. return 0;
  235. }
  236. static struct snd_soc_dai_ops dai_ops = {
  237. .trigger = trigger,
  238. .hw_params = hw_params,
  239. .set_fmt = set_format,
  240. .set_sysclk = set_sysclk,
  241. .startup = startup,
  242. .shutdown = shutdown,
  243. };
  244. static struct snd_soc_dai_driver dai_init = {
  245. .name = "hi3660_i2s",
  246. .probe = dai_probe,
  247. .playback = {
  248. .channels_min = 2,
  249. .channels_max = 2,
  250. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  251. SNDRV_PCM_FMTBIT_U16_LE,
  252. .rates = SNDRV_PCM_RATE_48000,
  253. },
  254. .capture = {
  255. .channels_min = 2,
  256. .channels_max = 2,
  257. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  258. SNDRV_PCM_FMTBIT_U16_LE,
  259. .rates = SNDRV_PCM_RATE_48000,
  260. },
  261. .ops = &dai_ops,
  262. };
  263. static const struct snd_soc_component_driver component_driver = {
  264. .name = "hi3660_i2s",
  265. };
  266. #include <sound/dmaengine_pcm.h>
  267. static const struct snd_pcm_hardware sound_hardware = {
  268. .info = SNDRV_PCM_INFO_MMAP |
  269. SNDRV_PCM_INFO_MMAP_VALID |
  270. SNDRV_PCM_INFO_PAUSE |
  271. SNDRV_PCM_INFO_RESUME |
  272. SNDRV_PCM_INFO_INTERLEAVED |
  273. SNDRV_PCM_INFO_HALF_DUPLEX,
  274. .period_bytes_min = 4096,
  275. .period_bytes_max = 4096,
  276. .periods_min = 4,
  277. .periods_max = UINT_MAX,
  278. .buffer_bytes_max = SIZE_MAX,
  279. };
  280. static const struct snd_dmaengine_pcm_config dmaengine_pcm_config = {
  281. .pcm_hardware = &sound_hardware,
  282. .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  283. .prealloc_buffer_size = 64 * 1024,
  284. };
  285. static int hi3660_i2s_probe(struct platform_device *pdev)
  286. {
  287. struct device *dev = &pdev->dev;
  288. struct hi3660_i2s *i2s;
  289. struct resource *res;
  290. int ret;
  291. i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
  292. if (!i2s)
  293. return -ENOMEM;
  294. i2s->dev = dev;
  295. spin_lock_init(&i2s->lock);
  296. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  297. if (!res) {
  298. ret = -ENODEV;
  299. return ret;
  300. }
  301. i2s->base_phys = (phys_addr_t)res->start;
  302. i2s->dai = dai_init;
  303. dev_set_drvdata(&pdev->dev, i2s);
  304. i2s->base = devm_ioremap_resource(dev, res);
  305. if (IS_ERR(i2s->base)) {
  306. dev_err(&pdev->dev, "ioremap failed\n");
  307. ret = PTR_ERR(i2s->base);
  308. return ret;
  309. }
  310. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  311. if (!res) {
  312. ret = -ENODEV;
  313. return ret;
  314. }
  315. i2s->base_syscon = devm_ioremap(dev, res->start, resource_size(res));
  316. if (IS_ERR(i2s->base_syscon)) {
  317. dev_err(&pdev->dev, "ioremap failed\n");
  318. ret = PTR_ERR(i2s->base_syscon);
  319. return ret;
  320. }
  321. /* i2s iomux config */
  322. i2s->pctrl = devm_pinctrl_get(dev);
  323. if (IS_ERR(i2s->pctrl)) {
  324. dev_err(dev, "could not get pinctrl\n");
  325. ret = -EIO;
  326. return ret;
  327. }
  328. i2s->pin_default = pinctrl_lookup_state(i2s->pctrl,
  329. PINCTRL_STATE_DEFAULT);
  330. if (IS_ERR(i2s->pin_default)) {
  331. dev_err(dev,
  332. "could not get default state (%li)\n",
  333. PTR_ERR(i2s->pin_default));
  334. ret = -EIO;
  335. return ret;
  336. }
  337. if (pinctrl_select_state(i2s->pctrl, i2s->pin_default)) {
  338. dev_err(dev, "could not set pins to default state\n");
  339. ret = -EIO;
  340. return ret;
  341. }
  342. ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
  343. &dmaengine_pcm_config, 0);
  344. if (ret)
  345. return ret;
  346. ret = snd_soc_register_component(&pdev->dev, &component_driver,
  347. &i2s->dai, 1);
  348. if (ret) {
  349. dev_err(&pdev->dev, "Failed to register dai\n");
  350. return ret;
  351. }
  352. return 0;
  353. }
  354. static int hi3660_i2s_remove(struct platform_device *pdev)
  355. {
  356. struct hi3660_i2s *i2s = dev_get_drvdata(&pdev->dev);
  357. snd_soc_unregister_component(&pdev->dev);
  358. dev_set_drvdata(&pdev->dev, NULL);
  359. pinctrl_put(i2s->pctrl);
  360. return 0;
  361. }
  362. static const struct of_device_id dt_ids[] = {
  363. { .compatible = "hisilicon,hi3660-i2s-1.0" },
  364. { /* sentinel */ }
  365. };
  366. MODULE_DEVICE_TABLE(of, dt_ids);
  367. static struct platform_driver local_platform_driver = {
  368. .probe = hi3660_i2s_probe,
  369. .remove = hi3660_i2s_remove,
  370. .driver = {
  371. .name = "hi3660_i2s",
  372. .owner = THIS_MODULE,
  373. .of_match_table = dt_ids,
  374. },
  375. };
  376. module_platform_driver(local_platform_driver);
  377. MODULE_DESCRIPTION("Hisilicon I2S driver");
  378. MODULE_AUTHOR("Guangke Ji <j00209069@notesmail.huawei.com>");
  379. MODULE_LICENSE("GPL");