mpc5200_psc_ac97.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
  4. //
  5. // Copyright (C) 2009 Jon Smirl, Digispeaker
  6. // Author: Jon Smirl <jonsmirl@gmail.com>
  7. #include <linux/module.h>
  8. #include <linux/of_device.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/delay.h>
  11. #include <linux/time.h>
  12. #include <sound/pcm.h>
  13. #include <sound/pcm_params.h>
  14. #include <sound/soc.h>
  15. #include <asm/time.h>
  16. #include <asm/delay.h>
  17. #include <asm/mpc52xx.h>
  18. #include <asm/mpc52xx_psc.h>
  19. #include "mpc5200_dma.h"
  20. #define DRV_NAME "mpc5200-psc-ac97"
  21. /* ALSA only supports a single AC97 device so static is recommend here */
  22. static struct psc_dma *psc_dma;
  23. static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  24. {
  25. int status;
  26. unsigned int val;
  27. mutex_lock(&psc_dma->mutex);
  28. /* Wait for command send status zero = ready */
  29. status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
  30. MPC52xx_PSC_SR_CMDSEND), 100, 0);
  31. if (status == 0) {
  32. pr_err("timeout on ac97 bus (rdy)\n");
  33. mutex_unlock(&psc_dma->mutex);
  34. return -ENODEV;
  35. }
  36. /* Force clear the data valid bit */
  37. in_be32(&psc_dma->psc_regs->ac97_data);
  38. /* Send the read */
  39. out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24));
  40. /* Wait for the answer */
  41. status = spin_event_timeout((in_be16(&psc_dma->psc_regs->sr_csr.status) &
  42. MPC52xx_PSC_SR_DATA_VAL), 100, 0);
  43. if (status == 0) {
  44. pr_err("timeout on ac97 read (val) %x\n",
  45. in_be16(&psc_dma->psc_regs->sr_csr.status));
  46. mutex_unlock(&psc_dma->mutex);
  47. return -ENODEV;
  48. }
  49. /* Get the data */
  50. val = in_be32(&psc_dma->psc_regs->ac97_data);
  51. if (((val >> 24) & 0x7f) != reg) {
  52. pr_err("reg echo error on ac97 read\n");
  53. mutex_unlock(&psc_dma->mutex);
  54. return -ENODEV;
  55. }
  56. val = (val >> 8) & 0xffff;
  57. mutex_unlock(&psc_dma->mutex);
  58. return (unsigned short) val;
  59. }
  60. static void psc_ac97_write(struct snd_ac97 *ac97,
  61. unsigned short reg, unsigned short val)
  62. {
  63. int status;
  64. mutex_lock(&psc_dma->mutex);
  65. /* Wait for command status zero = ready */
  66. status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
  67. MPC52xx_PSC_SR_CMDSEND), 100, 0);
  68. if (status == 0) {
  69. pr_err("timeout on ac97 bus (write)\n");
  70. goto out;
  71. }
  72. /* Write data */
  73. out_be32(&psc_dma->psc_regs->ac97_cmd,
  74. ((reg & 0x7f) << 24) | (val << 8));
  75. out:
  76. mutex_unlock(&psc_dma->mutex);
  77. }
  78. static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
  79. {
  80. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  81. mutex_lock(&psc_dma->mutex);
  82. out_be32(&regs->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
  83. udelay(3);
  84. out_be32(&regs->sicr, psc_dma->sicr);
  85. mutex_unlock(&psc_dma->mutex);
  86. }
  87. static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
  88. {
  89. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  90. mutex_lock(&psc_dma->mutex);
  91. dev_dbg(psc_dma->dev, "cold reset\n");
  92. mpc5200_psc_ac97_gpio_reset(psc_dma->id);
  93. /* Notify the PSC that a reset has occurred */
  94. out_be32(&regs->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB);
  95. /* Re-enable RX and TX */
  96. out_8(&regs->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
  97. mutex_unlock(&psc_dma->mutex);
  98. usleep_range(1000, 2000);
  99. psc_ac97_warm_reset(ac97);
  100. }
  101. static struct snd_ac97_bus_ops psc_ac97_ops = {
  102. .read = psc_ac97_read,
  103. .write = psc_ac97_write,
  104. .reset = psc_ac97_cold_reset,
  105. .warm_reset = psc_ac97_warm_reset,
  106. };
  107. static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
  108. struct snd_pcm_hw_params *params,
  109. struct snd_soc_dai *cpu_dai)
  110. {
  111. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
  112. struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
  113. dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
  114. " periods=%i buffer_size=%i buffer_bytes=%i channels=%i"
  115. " rate=%i format=%i\n",
  116. __func__, substream, params_period_size(params),
  117. params_period_bytes(params), params_periods(params),
  118. params_buffer_size(params), params_buffer_bytes(params),
  119. params_channels(params), params_rate(params),
  120. params_format(params));
  121. /* Determine the set of enable bits to turn on */
  122. s->ac97_slot_bits = (params_channels(params) == 1) ? 0x100 : 0x300;
  123. if (substream->pstr->stream != SNDRV_PCM_STREAM_CAPTURE)
  124. s->ac97_slot_bits <<= 16;
  125. return 0;
  126. }
  127. static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
  128. struct snd_pcm_hw_params *params,
  129. struct snd_soc_dai *cpu_dai)
  130. {
  131. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
  132. dev_dbg(psc_dma->dev, "%s(substream=%p)\n", __func__, substream);
  133. if (params_channels(params) == 1)
  134. out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
  135. else
  136. out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);
  137. return 0;
  138. }
  139. static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
  140. struct snd_soc_dai *dai)
  141. {
  142. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(dai);
  143. struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
  144. switch (cmd) {
  145. case SNDRV_PCM_TRIGGER_START:
  146. dev_dbg(psc_dma->dev, "AC97 START: stream=%i\n",
  147. substream->pstr->stream);
  148. /* Set the slot enable bits */
  149. psc_dma->slots |= s->ac97_slot_bits;
  150. out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
  151. break;
  152. case SNDRV_PCM_TRIGGER_STOP:
  153. dev_dbg(psc_dma->dev, "AC97 STOP: stream=%i\n",
  154. substream->pstr->stream);
  155. /* Clear the slot enable bits */
  156. psc_dma->slots &= ~(s->ac97_slot_bits);
  157. out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
  158. break;
  159. }
  160. return 0;
  161. }
  162. static int psc_ac97_probe(struct snd_soc_dai *cpu_dai)
  163. {
  164. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
  165. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  166. /* Go */
  167. out_8(&regs->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
  168. return 0;
  169. }
  170. /* ---------------------------------------------------------------------
  171. * ALSA SoC Bindings
  172. *
  173. * - Digital Audio Interface (DAI) template
  174. * - create/destroy dai hooks
  175. */
  176. /**
  177. * psc_ac97_dai_template: template CPU Digital Audio Interface
  178. */
  179. static const struct snd_soc_dai_ops psc_ac97_analog_ops = {
  180. .hw_params = psc_ac97_hw_analog_params,
  181. .trigger = psc_ac97_trigger,
  182. };
  183. static const struct snd_soc_dai_ops psc_ac97_digital_ops = {
  184. .hw_params = psc_ac97_hw_digital_params,
  185. };
  186. static struct snd_soc_dai_driver psc_ac97_dai[] = {
  187. {
  188. .name = "mpc5200-psc-ac97.0",
  189. .probe = psc_ac97_probe,
  190. .playback = {
  191. .stream_name = "AC97 Playback",
  192. .channels_min = 1,
  193. .channels_max = 6,
  194. .rates = SNDRV_PCM_RATE_8000_48000,
  195. .formats = SNDRV_PCM_FMTBIT_S32_BE,
  196. },
  197. .capture = {
  198. .stream_name = "AC97 Capture",
  199. .channels_min = 1,
  200. .channels_max = 2,
  201. .rates = SNDRV_PCM_RATE_8000_48000,
  202. .formats = SNDRV_PCM_FMTBIT_S32_BE,
  203. },
  204. .ops = &psc_ac97_analog_ops,
  205. },
  206. {
  207. .name = "mpc5200-psc-ac97.1",
  208. .playback = {
  209. .stream_name = "AC97 SPDIF",
  210. .channels_min = 1,
  211. .channels_max = 2,
  212. .rates = SNDRV_PCM_RATE_32000 | \
  213. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
  214. .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
  215. },
  216. .ops = &psc_ac97_digital_ops,
  217. } };
  218. static const struct snd_soc_component_driver psc_ac97_component = {
  219. .name = DRV_NAME,
  220. };
  221. /* ---------------------------------------------------------------------
  222. * OF platform bus binding code:
  223. * - Probe/remove operations
  224. * - OF device match table
  225. */
  226. static int psc_ac97_of_probe(struct platform_device *op)
  227. {
  228. int rc;
  229. struct mpc52xx_psc __iomem *regs;
  230. rc = mpc5200_audio_dma_create(op);
  231. if (rc != 0)
  232. return rc;
  233. rc = snd_soc_set_ac97_ops(&psc_ac97_ops);
  234. if (rc != 0) {
  235. dev_err(&op->dev, "Failed to set AC'97 ops: %d\n", rc);
  236. return rc;
  237. }
  238. rc = snd_soc_register_component(&op->dev, &psc_ac97_component,
  239. psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
  240. if (rc != 0) {
  241. dev_err(&op->dev, "Failed to register DAI\n");
  242. return rc;
  243. }
  244. psc_dma = dev_get_drvdata(&op->dev);
  245. regs = psc_dma->psc_regs;
  246. psc_dma->imr = 0;
  247. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  248. /* Configure the serial interface mode to AC97 */
  249. psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 | MPC52xx_PSC_SICR_ENAC97;
  250. out_be32(&regs->sicr, psc_dma->sicr);
  251. /* No slots active */
  252. out_be32(&regs->ac97_slots, 0x00000000);
  253. return 0;
  254. }
  255. static int psc_ac97_of_remove(struct platform_device *op)
  256. {
  257. mpc5200_audio_dma_destroy(op);
  258. snd_soc_unregister_component(&op->dev);
  259. snd_soc_set_ac97_ops(NULL);
  260. return 0;
  261. }
  262. /* Match table for of_platform binding */
  263. static const struct of_device_id psc_ac97_match[] = {
  264. { .compatible = "fsl,mpc5200-psc-ac97", },
  265. { .compatible = "fsl,mpc5200b-psc-ac97", },
  266. {}
  267. };
  268. MODULE_DEVICE_TABLE(of, psc_ac97_match);
  269. static struct platform_driver psc_ac97_driver = {
  270. .probe = psc_ac97_of_probe,
  271. .remove = psc_ac97_of_remove,
  272. .driver = {
  273. .name = "mpc5200-psc-ac97",
  274. .of_match_table = psc_ac97_match,
  275. },
  276. };
  277. module_platform_driver(psc_ac97_driver);
  278. MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
  279. MODULE_DESCRIPTION("mpc5200 AC97 module");
  280. MODULE_LICENSE("GPL");