mpc5200_dma.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. //
  3. // Freescale MPC5200 PSC DMA
  4. // ALSA SoC Platform driver
  5. //
  6. // Copyright (C) 2008 Secret Lab Technologies Ltd.
  7. // Copyright (C) 2009 Jon Smirl, Digispeaker
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/slab.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_platform.h>
  15. #include <sound/soc.h>
  16. #include <linux/fsl/bestcomm/bestcomm.h>
  17. #include <linux/fsl/bestcomm/gen_bd.h>
  18. #include <asm/mpc52xx_psc.h>
  19. #include "mpc5200_dma.h"
  20. #define DRV_NAME "mpc5200_dma"
  21. /*
  22. * Interrupt handlers
  23. */
  24. static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
  25. {
  26. struct psc_dma *psc_dma = _psc_dma;
  27. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  28. u16 isr;
  29. isr = in_be16(&regs->mpc52xx_psc_isr);
  30. /* Playback underrun error */
  31. if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
  32. psc_dma->stats.underrun_count++;
  33. /* Capture overrun error */
  34. if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
  35. psc_dma->stats.overrun_count++;
  36. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  37. return IRQ_HANDLED;
  38. }
  39. /**
  40. * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
  41. * @s: pointer to stream private data structure
  42. *
  43. * Enqueues another audio period buffer into the bestcomm queue.
  44. *
  45. * Note: The routine must only be called when there is space available in
  46. * the queue. Otherwise the enqueue will fail and the audio ring buffer
  47. * will get out of sync
  48. */
  49. static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
  50. {
  51. struct bcom_bd *bd;
  52. /* Prepare and enqueue the next buffer descriptor */
  53. bd = bcom_prepare_next_buffer(s->bcom_task);
  54. bd->status = s->period_bytes;
  55. bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
  56. bcom_submit_next_buffer(s->bcom_task, NULL);
  57. /* Update for next period */
  58. s->period_next = (s->period_next + 1) % s->runtime->periods;
  59. }
  60. /* Bestcomm DMA irq handler */
  61. static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
  62. {
  63. struct psc_dma_stream *s = _psc_dma_stream;
  64. spin_lock(&s->psc_dma->lock);
  65. /* For each finished period, dequeue the completed period buffer
  66. * and enqueue a new one in it's place. */
  67. while (bcom_buffer_done(s->bcom_task)) {
  68. bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
  69. s->period_current = (s->period_current+1) % s->runtime->periods;
  70. s->period_count++;
  71. psc_dma_bcom_enqueue_next_buffer(s);
  72. }
  73. spin_unlock(&s->psc_dma->lock);
  74. /* If the stream is active, then also inform the PCM middle layer
  75. * of the period finished event. */
  76. if (s->active)
  77. snd_pcm_period_elapsed(s->stream);
  78. return IRQ_HANDLED;
  79. }
  80. static int psc_dma_hw_free(struct snd_soc_component *component,
  81. struct snd_pcm_substream *substream)
  82. {
  83. snd_pcm_set_runtime_buffer(substream, NULL);
  84. return 0;
  85. }
  86. /**
  87. * psc_dma_trigger: start and stop the DMA transfer.
  88. *
  89. * This function is called by ALSA to start, stop, pause, and resume the DMA
  90. * transfer of data.
  91. */
  92. static int psc_dma_trigger(struct snd_soc_component *component,
  93. struct snd_pcm_substream *substream, int cmd)
  94. {
  95. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  96. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  97. struct snd_pcm_runtime *runtime = substream->runtime;
  98. struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
  99. struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
  100. u16 imr;
  101. unsigned long flags;
  102. int i;
  103. switch (cmd) {
  104. case SNDRV_PCM_TRIGGER_START:
  105. dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
  106. substream->pstr->stream, runtime->frame_bits,
  107. (int)runtime->period_size, runtime->periods);
  108. s->period_bytes = frames_to_bytes(runtime,
  109. runtime->period_size);
  110. s->period_next = 0;
  111. s->period_current = 0;
  112. s->active = 1;
  113. s->period_count = 0;
  114. s->runtime = runtime;
  115. /* Fill up the bestcomm bd queue and enable DMA.
  116. * This will begin filling the PSC's fifo.
  117. */
  118. spin_lock_irqsave(&psc_dma->lock, flags);
  119. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  120. bcom_gen_bd_rx_reset(s->bcom_task);
  121. else
  122. bcom_gen_bd_tx_reset(s->bcom_task);
  123. for (i = 0; i < runtime->periods; i++)
  124. if (!bcom_queue_full(s->bcom_task))
  125. psc_dma_bcom_enqueue_next_buffer(s);
  126. bcom_enable(s->bcom_task);
  127. spin_unlock_irqrestore(&psc_dma->lock, flags);
  128. out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
  129. break;
  130. case SNDRV_PCM_TRIGGER_STOP:
  131. dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
  132. substream->pstr->stream, s->period_count);
  133. s->active = 0;
  134. spin_lock_irqsave(&psc_dma->lock, flags);
  135. bcom_disable(s->bcom_task);
  136. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  137. bcom_gen_bd_rx_reset(s->bcom_task);
  138. else
  139. bcom_gen_bd_tx_reset(s->bcom_task);
  140. spin_unlock_irqrestore(&psc_dma->lock, flags);
  141. break;
  142. default:
  143. dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
  144. substream->pstr->stream, cmd);
  145. return -EINVAL;
  146. }
  147. /* Update interrupt enable settings */
  148. imr = 0;
  149. if (psc_dma->playback.active)
  150. imr |= MPC52xx_PSC_IMR_TXEMP;
  151. if (psc_dma->capture.active)
  152. imr |= MPC52xx_PSC_IMR_ORERR;
  153. out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
  154. return 0;
  155. }
  156. /* ---------------------------------------------------------------------
  157. * The PSC DMA 'ASoC platform' driver
  158. *
  159. * Can be referenced by an 'ASoC machine' driver
  160. * This driver only deals with the audio bus; it doesn't have any
  161. * interaction with the attached codec
  162. */
  163. static const struct snd_pcm_hardware psc_dma_hardware = {
  164. .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
  165. SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
  166. SNDRV_PCM_INFO_BATCH,
  167. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
  168. SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
  169. .period_bytes_max = 1024 * 1024,
  170. .period_bytes_min = 32,
  171. .periods_min = 2,
  172. .periods_max = 256,
  173. .buffer_bytes_max = 2 * 1024 * 1024,
  174. .fifo_size = 512,
  175. };
  176. static int psc_dma_open(struct snd_soc_component *component,
  177. struct snd_pcm_substream *substream)
  178. {
  179. struct snd_pcm_runtime *runtime = substream->runtime;
  180. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  181. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  182. struct psc_dma_stream *s;
  183. int rc;
  184. dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
  185. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  186. s = &psc_dma->capture;
  187. else
  188. s = &psc_dma->playback;
  189. snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
  190. rc = snd_pcm_hw_constraint_integer(runtime,
  191. SNDRV_PCM_HW_PARAM_PERIODS);
  192. if (rc < 0) {
  193. dev_err(substream->pcm->card->dev, "invalid buffer size\n");
  194. return rc;
  195. }
  196. s->stream = substream;
  197. return 0;
  198. }
  199. static int psc_dma_close(struct snd_soc_component *component,
  200. struct snd_pcm_substream *substream)
  201. {
  202. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  203. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  204. struct psc_dma_stream *s;
  205. dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
  206. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  207. s = &psc_dma->capture;
  208. else
  209. s = &psc_dma->playback;
  210. if (!psc_dma->playback.active &&
  211. !psc_dma->capture.active) {
  212. /* Disable all interrupts and reset the PSC */
  213. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  214. out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
  215. }
  216. s->stream = NULL;
  217. return 0;
  218. }
  219. static snd_pcm_uframes_t
  220. psc_dma_pointer(struct snd_soc_component *component,
  221. struct snd_pcm_substream *substream)
  222. {
  223. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  224. struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  225. struct psc_dma_stream *s;
  226. dma_addr_t count;
  227. if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
  228. s = &psc_dma->capture;
  229. else
  230. s = &psc_dma->playback;
  231. count = s->period_current * s->period_bytes;
  232. return bytes_to_frames(substream->runtime, count);
  233. }
  234. static int psc_dma_hw_params(struct snd_soc_component *component,
  235. struct snd_pcm_substream *substream,
  236. struct snd_pcm_hw_params *params)
  237. {
  238. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  239. return 0;
  240. }
  241. static int psc_dma_new(struct snd_soc_component *component,
  242. struct snd_soc_pcm_runtime *rtd)
  243. {
  244. struct snd_card *card = rtd->card->snd_card;
  245. struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
  246. struct snd_pcm *pcm = rtd->pcm;
  247. size_t size = psc_dma_hardware.buffer_bytes_max;
  248. int rc;
  249. dev_dbg(component->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
  250. card, dai, pcm);
  251. rc = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
  252. if (rc)
  253. return rc;
  254. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
  255. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  256. size, &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
  257. if (rc)
  258. goto playback_alloc_err;
  259. }
  260. if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
  261. rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
  262. size, &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
  263. if (rc)
  264. goto capture_alloc_err;
  265. }
  266. return 0;
  267. capture_alloc_err:
  268. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
  269. snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
  270. playback_alloc_err:
  271. dev_err(card->dev, "Cannot allocate buffer(s)\n");
  272. return -ENOMEM;
  273. }
  274. static void psc_dma_free(struct snd_soc_component *component,
  275. struct snd_pcm *pcm)
  276. {
  277. struct snd_pcm_substream *substream;
  278. int stream;
  279. dev_dbg(component->dev, "psc_dma_free(pcm=%p)\n", pcm);
  280. for (stream = 0; stream < 2; stream++) {
  281. substream = pcm->streams[stream].substream;
  282. if (substream) {
  283. snd_dma_free_pages(&substream->dma_buffer);
  284. substream->dma_buffer.area = NULL;
  285. substream->dma_buffer.addr = 0;
  286. }
  287. }
  288. }
  289. static const struct snd_soc_component_driver mpc5200_audio_dma_component = {
  290. .name = DRV_NAME,
  291. .open = psc_dma_open,
  292. .close = psc_dma_close,
  293. .hw_free = psc_dma_hw_free,
  294. .pointer = psc_dma_pointer,
  295. .trigger = psc_dma_trigger,
  296. .hw_params = psc_dma_hw_params,
  297. .pcm_construct = psc_dma_new,
  298. .pcm_destruct = psc_dma_free,
  299. };
  300. int mpc5200_audio_dma_create(struct platform_device *op)
  301. {
  302. phys_addr_t fifo;
  303. struct psc_dma *psc_dma;
  304. struct resource res;
  305. int size, irq, rc;
  306. const __be32 *prop;
  307. void __iomem *regs;
  308. int ret;
  309. /* Fetch the registers and IRQ of the PSC */
  310. irq = irq_of_parse_and_map(op->dev.of_node, 0);
  311. if (of_address_to_resource(op->dev.of_node, 0, &res)) {
  312. dev_err(&op->dev, "Missing reg property\n");
  313. return -ENODEV;
  314. }
  315. regs = ioremap(res.start, resource_size(&res));
  316. if (!regs) {
  317. dev_err(&op->dev, "Could not map registers\n");
  318. return -ENODEV;
  319. }
  320. /* Allocate and initialize the driver private data */
  321. psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
  322. if (!psc_dma) {
  323. ret = -ENOMEM;
  324. goto out_unmap;
  325. }
  326. /* Get the PSC ID */
  327. prop = of_get_property(op->dev.of_node, "cell-index", &size);
  328. if (!prop || size < sizeof *prop) {
  329. ret = -ENODEV;
  330. goto out_free;
  331. }
  332. spin_lock_init(&psc_dma->lock);
  333. mutex_init(&psc_dma->mutex);
  334. psc_dma->id = be32_to_cpu(*prop);
  335. psc_dma->irq = irq;
  336. psc_dma->psc_regs = regs;
  337. psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
  338. psc_dma->dev = &op->dev;
  339. psc_dma->playback.psc_dma = psc_dma;
  340. psc_dma->capture.psc_dma = psc_dma;
  341. snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
  342. /* Find the address of the fifo data registers and setup the
  343. * DMA tasks */
  344. fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
  345. psc_dma->capture.bcom_task =
  346. bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
  347. psc_dma->playback.bcom_task =
  348. bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
  349. if (!psc_dma->capture.bcom_task ||
  350. !psc_dma->playback.bcom_task) {
  351. dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
  352. ret = -ENODEV;
  353. goto out_free;
  354. }
  355. /* Disable all interrupts and reset the PSC */
  356. out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
  357. /* reset receiver */
  358. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
  359. /* reset transmitter */
  360. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
  361. /* reset error */
  362. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
  363. /* reset mode */
  364. out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
  365. /* Set up mode register;
  366. * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
  367. * Second write: register Normal mode for non loopback
  368. */
  369. out_8(&psc_dma->psc_regs->mode, 0);
  370. out_8(&psc_dma->psc_regs->mode, 0);
  371. /* Set the TX and RX fifo alarm thresholds */
  372. out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
  373. out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
  374. out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
  375. out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
  376. /* Lookup the IRQ numbers */
  377. psc_dma->playback.irq =
  378. bcom_get_task_irq(psc_dma->playback.bcom_task);
  379. psc_dma->capture.irq =
  380. bcom_get_task_irq(psc_dma->capture.bcom_task);
  381. rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
  382. "psc-dma-status", psc_dma);
  383. rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  384. "psc-dma-capture", &psc_dma->capture);
  385. rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
  386. "psc-dma-playback", &psc_dma->playback);
  387. if (rc) {
  388. ret = -ENODEV;
  389. goto out_irq;
  390. }
  391. /* Save what we've done so it can be found again later */
  392. dev_set_drvdata(&op->dev, psc_dma);
  393. /* Tell the ASoC OF helpers about it */
  394. return devm_snd_soc_register_component(&op->dev,
  395. &mpc5200_audio_dma_component, NULL, 0);
  396. out_irq:
  397. free_irq(psc_dma->irq, psc_dma);
  398. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  399. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  400. out_free:
  401. kfree(psc_dma);
  402. out_unmap:
  403. iounmap(regs);
  404. return ret;
  405. }
  406. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
  407. int mpc5200_audio_dma_destroy(struct platform_device *op)
  408. {
  409. struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
  410. dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
  411. bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
  412. bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
  413. /* Release irqs */
  414. free_irq(psc_dma->irq, psc_dma);
  415. free_irq(psc_dma->capture.irq, &psc_dma->capture);
  416. free_irq(psc_dma->playback.irq, &psc_dma->playback);
  417. iounmap(psc_dma->psc_regs);
  418. kfree(psc_dma);
  419. dev_set_drvdata(&op->dev, NULL);
  420. return 0;
  421. }
  422. EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
  423. MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  424. MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
  425. MODULE_LICENSE("GPL");