fsl_ssi.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
  4. *
  5. * Author: Timur Tabi <timur@freescale.com>
  6. *
  7. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  8. */
  9. #ifndef _MPC8610_I2S_H
  10. #define _MPC8610_I2S_H
  11. /* -- SSI Register Map -- */
  12. /* SSI Transmit Data Register 0 */
  13. #define REG_SSI_STX0 0x00
  14. /* SSI Transmit Data Register 1 */
  15. #define REG_SSI_STX1 0x04
  16. /* SSI Receive Data Register 0 */
  17. #define REG_SSI_SRX0 0x08
  18. /* SSI Receive Data Register 1 */
  19. #define REG_SSI_SRX1 0x0c
  20. /* SSI Control Register */
  21. #define REG_SSI_SCR 0x10
  22. /* SSI Interrupt Status Register */
  23. #define REG_SSI_SISR 0x14
  24. /* SSI Interrupt Enable Register */
  25. #define REG_SSI_SIER 0x18
  26. /* SSI Transmit Configuration Register */
  27. #define REG_SSI_STCR 0x1c
  28. /* SSI Receive Configuration Register */
  29. #define REG_SSI_SRCR 0x20
  30. #define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
  31. /* SSI Transmit Clock Control Register */
  32. #define REG_SSI_STCCR 0x24
  33. /* SSI Receive Clock Control Register */
  34. #define REG_SSI_SRCCR 0x28
  35. #define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
  36. /* SSI FIFO Control/Status Register */
  37. #define REG_SSI_SFCSR 0x2c
  38. /*
  39. * SSI Test Register (Intended for debugging purposes only)
  40. *
  41. * Note: STR is not documented in recent IMX datasheet, but
  42. * is described in IMX51 reference manual at section 56.3.3.14
  43. */
  44. #define REG_SSI_STR 0x30
  45. /*
  46. * SSI Option Register (Intended for internal use only)
  47. *
  48. * Note: SOR is not documented in recent IMX datasheet, but
  49. * is described in IMX51 reference manual at section 56.3.3.15
  50. */
  51. #define REG_SSI_SOR 0x34
  52. /* SSI AC97 Control Register */
  53. #define REG_SSI_SACNT 0x38
  54. /* SSI AC97 Command Address Register */
  55. #define REG_SSI_SACADD 0x3c
  56. /* SSI AC97 Command Data Register */
  57. #define REG_SSI_SACDAT 0x40
  58. /* SSI AC97 Tag Register */
  59. #define REG_SSI_SATAG 0x44
  60. /* SSI Transmit Time Slot Mask Register */
  61. #define REG_SSI_STMSK 0x48
  62. /* SSI Receive Time Slot Mask Register */
  63. #define REG_SSI_SRMSK 0x4c
  64. #define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
  65. /*
  66. * SSI AC97 Channel Status Register
  67. *
  68. * The status could be changed by:
  69. * 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST
  70. * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
  71. * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
  72. */
  73. #define REG_SSI_SACCST 0x50
  74. /* SSI AC97 Channel Enable Register -- Set bits in SACCST */
  75. #define REG_SSI_SACCEN 0x54
  76. /* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
  77. #define REG_SSI_SACCDIS 0x58
  78. /* -- SSI Register Field Maps -- */
  79. /* SSI Control Register -- REG_SSI_SCR 0x10 */
  80. #define SSI_SCR_SYNC_TX_FS 0x00001000
  81. #define SSI_SCR_RFR_CLK_DIS 0x00000800
  82. #define SSI_SCR_TFR_CLK_DIS 0x00000400
  83. #define SSI_SCR_TCH_EN 0x00000100
  84. #define SSI_SCR_SYS_CLK_EN 0x00000080
  85. #define SSI_SCR_I2S_MODE_MASK 0x00000060
  86. #define SSI_SCR_I2S_MODE_NORMAL 0x00000000
  87. #define SSI_SCR_I2S_MODE_MASTER 0x00000020
  88. #define SSI_SCR_I2S_MODE_SLAVE 0x00000040
  89. #define SSI_SCR_SYN 0x00000010
  90. #define SSI_SCR_NET 0x00000008
  91. #define SSI_SCR_I2S_NET_MASK (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK)
  92. #define SSI_SCR_RE 0x00000004
  93. #define SSI_SCR_TE 0x00000002
  94. #define SSI_SCR_SSIEN 0x00000001
  95. /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
  96. #define SSI_SISR_RFRC 0x01000000
  97. #define SSI_SISR_TFRC 0x00800000
  98. #define SSI_SISR_CMDAU 0x00040000
  99. #define SSI_SISR_CMDDU 0x00020000
  100. #define SSI_SISR_RXT 0x00010000
  101. #define SSI_SISR_RDR1 0x00008000
  102. #define SSI_SISR_RDR0 0x00004000
  103. #define SSI_SISR_TDE1 0x00002000
  104. #define SSI_SISR_TDE0 0x00001000
  105. #define SSI_SISR_ROE1 0x00000800
  106. #define SSI_SISR_ROE0 0x00000400
  107. #define SSI_SISR_TUE1 0x00000200
  108. #define SSI_SISR_TUE0 0x00000100
  109. #define SSI_SISR_TFS 0x00000080
  110. #define SSI_SISR_RFS 0x00000040
  111. #define SSI_SISR_TLS 0x00000020
  112. #define SSI_SISR_RLS 0x00000010
  113. #define SSI_SISR_RFF1 0x00000008
  114. #define SSI_SISR_RFF0 0x00000004
  115. #define SSI_SISR_TFE1 0x00000002
  116. #define SSI_SISR_TFE0 0x00000001
  117. /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
  118. #define SSI_SIER_RFRC_EN 0x01000000
  119. #define SSI_SIER_TFRC_EN 0x00800000
  120. #define SSI_SIER_RDMAE 0x00400000
  121. #define SSI_SIER_RIE 0x00200000
  122. #define SSI_SIER_TDMAE 0x00100000
  123. #define SSI_SIER_TIE 0x00080000
  124. #define SSI_SIER_CMDAU_EN 0x00040000
  125. #define SSI_SIER_CMDDU_EN 0x00020000
  126. #define SSI_SIER_RXT_EN 0x00010000
  127. #define SSI_SIER_RDR1_EN 0x00008000
  128. #define SSI_SIER_RDR0_EN 0x00004000
  129. #define SSI_SIER_TDE1_EN 0x00002000
  130. #define SSI_SIER_TDE0_EN 0x00001000
  131. #define SSI_SIER_ROE1_EN 0x00000800
  132. #define SSI_SIER_ROE0_EN 0x00000400
  133. #define SSI_SIER_TUE1_EN 0x00000200
  134. #define SSI_SIER_TUE0_EN 0x00000100
  135. #define SSI_SIER_TFS_EN 0x00000080
  136. #define SSI_SIER_RFS_EN 0x00000040
  137. #define SSI_SIER_TLS_EN 0x00000020
  138. #define SSI_SIER_RLS_EN 0x00000010
  139. #define SSI_SIER_RFF1_EN 0x00000008
  140. #define SSI_SIER_RFF0_EN 0x00000004
  141. #define SSI_SIER_TFE1_EN 0x00000002
  142. #define SSI_SIER_TFE0_EN 0x00000001
  143. /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
  144. #define SSI_STCR_TXBIT0 0x00000200
  145. #define SSI_STCR_TFEN1 0x00000100
  146. #define SSI_STCR_TFEN0 0x00000080
  147. #define SSI_STCR_TFDIR 0x00000040
  148. #define SSI_STCR_TXDIR 0x00000020
  149. #define SSI_STCR_TSHFD 0x00000010
  150. #define SSI_STCR_TSCKP 0x00000008
  151. #define SSI_STCR_TFSI 0x00000004
  152. #define SSI_STCR_TFSL 0x00000002
  153. #define SSI_STCR_TEFS 0x00000001
  154. /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
  155. #define SSI_SRCR_RXEXT 0x00000400
  156. #define SSI_SRCR_RXBIT0 0x00000200
  157. #define SSI_SRCR_RFEN1 0x00000100
  158. #define SSI_SRCR_RFEN0 0x00000080
  159. #define SSI_SRCR_RFDIR 0x00000040
  160. #define SSI_SRCR_RXDIR 0x00000020
  161. #define SSI_SRCR_RSHFD 0x00000010
  162. #define SSI_SRCR_RSCKP 0x00000008
  163. #define SSI_SRCR_RFSI 0x00000004
  164. #define SSI_SRCR_RFSL 0x00000002
  165. #define SSI_SRCR_REFS 0x00000001
  166. /*
  167. * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
  168. * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
  169. */
  170. #define SSI_SxCCR_DIV2_SHIFT 18
  171. #define SSI_SxCCR_DIV2 0x00040000
  172. #define SSI_SxCCR_PSR_SHIFT 17
  173. #define SSI_SxCCR_PSR 0x00020000
  174. #define SSI_SxCCR_WL_SHIFT 13
  175. #define SSI_SxCCR_WL_MASK 0x0001E000
  176. #define SSI_SxCCR_WL(x) \
  177. (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
  178. #define SSI_SxCCR_DC_SHIFT 8
  179. #define SSI_SxCCR_DC_MASK 0x00001F00
  180. #define SSI_SxCCR_DC(x) \
  181. ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
  182. #define SSI_SxCCR_PM_SHIFT 0
  183. #define SSI_SxCCR_PM_MASK 0x000000FF
  184. #define SSI_SxCCR_PM(x) \
  185. ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
  186. /*
  187. * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
  188. *
  189. * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
  190. * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
  191. */
  192. #define SSI_SFCSR_RFCNT1_SHIFT 28
  193. #define SSI_SFCSR_RFCNT1_MASK 0xF0000000
  194. #define SSI_SFCSR_RFCNT1(x) \
  195. (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
  196. #define SSI_SFCSR_TFCNT1_SHIFT 24
  197. #define SSI_SFCSR_TFCNT1_MASK 0x0F000000
  198. #define SSI_SFCSR_TFCNT1(x) \
  199. (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
  200. #define SSI_SFCSR_RFWM1_SHIFT 20
  201. #define SSI_SFCSR_RFWM1_MASK 0x00F00000
  202. #define SSI_SFCSR_RFWM1(x) \
  203. (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
  204. #define SSI_SFCSR_TFWM1_SHIFT 16
  205. #define SSI_SFCSR_TFWM1_MASK 0x000F0000
  206. #define SSI_SFCSR_TFWM1(x) \
  207. (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
  208. #define SSI_SFCSR_RFCNT0_SHIFT 12
  209. #define SSI_SFCSR_RFCNT0_MASK 0x0000F000
  210. #define SSI_SFCSR_RFCNT0(x) \
  211. (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
  212. #define SSI_SFCSR_TFCNT0_SHIFT 8
  213. #define SSI_SFCSR_TFCNT0_MASK 0x00000F00
  214. #define SSI_SFCSR_TFCNT0(x) \
  215. (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
  216. #define SSI_SFCSR_RFWM0_SHIFT 4
  217. #define SSI_SFCSR_RFWM0_MASK 0x000000F0
  218. #define SSI_SFCSR_RFWM0(x) \
  219. (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
  220. #define SSI_SFCSR_TFWM0_SHIFT 0
  221. #define SSI_SFCSR_TFWM0_MASK 0x0000000F
  222. #define SSI_SFCSR_TFWM0(x) \
  223. (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
  224. /* SSI Test Register -- REG_SSI_STR 0x30 */
  225. #define SSI_STR_TEST 0x00008000
  226. #define SSI_STR_RCK2TCK 0x00004000
  227. #define SSI_STR_RFS2TFS 0x00002000
  228. #define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
  229. #define SSI_STR_TXD2RXD 0x00000080
  230. #define SSI_STR_TCK2RCK 0x00000040
  231. #define SSI_STR_TFS2RFS 0x00000020
  232. #define SSI_STR_TXSTATE(x) ((x) & 0x1F)
  233. /* SSI Option Register -- REG_SSI_SOR 0x34 */
  234. #define SSI_SOR_CLKOFF 0x00000040
  235. #define SSI_SOR_RX_CLR 0x00000020
  236. #define SSI_SOR_TX_CLR 0x00000010
  237. #define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
  238. #define SSI_SOR_INIT 0x00000008
  239. #define SSI_SOR_WAIT_SHIFT 1
  240. #define SSI_SOR_WAIT_MASK 0x00000006
  241. #define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT)
  242. #define SSI_SOR_SYNRST 0x00000001
  243. /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
  244. #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
  245. #define SSI_SACNT_WR 0x00000010
  246. #define SSI_SACNT_RD 0x00000008
  247. #define SSI_SACNT_RDWR_MASK 0x00000018
  248. #define SSI_SACNT_TIF 0x00000004
  249. #define SSI_SACNT_FV 0x00000002
  250. #define SSI_SACNT_AC97EN 0x00000001
  251. struct device;
  252. #if IS_ENABLED(CONFIG_DEBUG_FS)
  253. struct fsl_ssi_dbg {
  254. struct dentry *dbg_dir;
  255. struct {
  256. unsigned int rfrc;
  257. unsigned int tfrc;
  258. unsigned int cmdau;
  259. unsigned int cmddu;
  260. unsigned int rxt;
  261. unsigned int rdr1;
  262. unsigned int rdr0;
  263. unsigned int tde1;
  264. unsigned int tde0;
  265. unsigned int roe1;
  266. unsigned int roe0;
  267. unsigned int tue1;
  268. unsigned int tue0;
  269. unsigned int tfs;
  270. unsigned int rfs;
  271. unsigned int tls;
  272. unsigned int rls;
  273. unsigned int rff1;
  274. unsigned int rff0;
  275. unsigned int tfe1;
  276. unsigned int tfe0;
  277. } stats;
  278. };
  279. void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
  280. void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
  281. void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
  282. #else
  283. struct fsl_ssi_dbg {
  284. };
  285. static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
  286. {
  287. }
  288. static inline void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
  289. struct device *dev)
  290. {
  291. }
  292. static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
  293. {
  294. }
  295. #endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
  296. #endif