fsl_ssi.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  4. //
  5. // Author: Timur Tabi <timur@freescale.com>
  6. //
  7. // Copyright 2007-2010 Freescale Semiconductor, Inc.
  8. //
  9. // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
  10. //
  11. // The i.MX SSI core has some nasty limitations in AC97 mode. While most
  12. // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
  13. // one FIFO which combines all valid receive slots. We cannot even select
  14. // which slots we want to receive. The WM9712 with which this driver
  15. // was developed with always sends GPIO status data in slot 12 which
  16. // we receive in our (PCM-) data stream. The only chance we have is to
  17. // manually skip this data in the FIQ handler. With sampling rates different
  18. // from 48000Hz not every frame has valid receive data, so the ratio
  19. // between pcm data and GPIO status data changes. Our FIQ handler is not
  20. // able to handle this, hence this driver only works with 48000Hz sampling
  21. // rate.
  22. // Reading and writing AC97 registers is another challenge. The core
  23. // provides us status bits when the read register is updated with *another*
  24. // value. When we read the same register two times (and the register still
  25. // contains the same value) these status bits are not set. We work
  26. // around this by not polling these bits but only wait a fixed delay.
  27. #include <linux/init.h>
  28. #include <linux/io.h>
  29. #include <linux/module.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/clk.h>
  32. #include <linux/ctype.h>
  33. #include <linux/device.h>
  34. #include <linux/delay.h>
  35. #include <linux/mutex.h>
  36. #include <linux/slab.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/of.h>
  39. #include <linux/of_address.h>
  40. #include <linux/of_irq.h>
  41. #include <linux/of_platform.h>
  42. #include <sound/core.h>
  43. #include <sound/pcm.h>
  44. #include <sound/pcm_params.h>
  45. #include <sound/initval.h>
  46. #include <sound/soc.h>
  47. #include <sound/dmaengine_pcm.h>
  48. #include "fsl_ssi.h"
  49. #include "imx-pcm.h"
  50. /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
  51. #define RX 0
  52. #define TX 1
  53. /**
  54. * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
  55. *
  56. * The SSI has a limitation in that the samples must be in the same byte
  57. * order as the host CPU. This is because when multiple bytes are written
  58. * to the STX register, the bytes and bits must be written in the same
  59. * order. The STX is a shift register, so all the bits need to be aligned
  60. * (bit-endianness must match byte-endianness). Processors typically write
  61. * the bits within a byte in the same order that the bytes of a word are
  62. * written in. So if the host CPU is big-endian, then only big-endian
  63. * samples will be written to STX properly.
  64. */
  65. #ifdef __BIG_ENDIAN
  66. #define FSLSSI_I2S_FORMATS \
  67. (SNDRV_PCM_FMTBIT_S8 | \
  68. SNDRV_PCM_FMTBIT_S16_BE | \
  69. SNDRV_PCM_FMTBIT_S18_3BE | \
  70. SNDRV_PCM_FMTBIT_S20_3BE | \
  71. SNDRV_PCM_FMTBIT_S24_3BE | \
  72. SNDRV_PCM_FMTBIT_S24_BE)
  73. #else
  74. #define FSLSSI_I2S_FORMATS \
  75. (SNDRV_PCM_FMTBIT_S8 | \
  76. SNDRV_PCM_FMTBIT_S16_LE | \
  77. SNDRV_PCM_FMTBIT_S18_3LE | \
  78. SNDRV_PCM_FMTBIT_S20_3LE | \
  79. SNDRV_PCM_FMTBIT_S24_3LE | \
  80. SNDRV_PCM_FMTBIT_S24_LE)
  81. #endif
  82. /*
  83. * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
  84. * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
  85. * - Also have NB_NF to mark these two clocks will not be inverted
  86. */
  87. #define FSLSSI_AC97_DAIFMT \
  88. (SND_SOC_DAIFMT_AC97 | \
  89. SND_SOC_DAIFMT_CBM_CFS | \
  90. SND_SOC_DAIFMT_NB_NF)
  91. #define FSLSSI_SIER_DBG_RX_FLAGS \
  92. (SSI_SIER_RFF0_EN | \
  93. SSI_SIER_RLS_EN | \
  94. SSI_SIER_RFS_EN | \
  95. SSI_SIER_ROE0_EN | \
  96. SSI_SIER_RFRC_EN)
  97. #define FSLSSI_SIER_DBG_TX_FLAGS \
  98. (SSI_SIER_TFE0_EN | \
  99. SSI_SIER_TLS_EN | \
  100. SSI_SIER_TFS_EN | \
  101. SSI_SIER_TUE0_EN | \
  102. SSI_SIER_TFRC_EN)
  103. enum fsl_ssi_type {
  104. FSL_SSI_MCP8610,
  105. FSL_SSI_MX21,
  106. FSL_SSI_MX35,
  107. FSL_SSI_MX51,
  108. };
  109. struct fsl_ssi_regvals {
  110. u32 sier;
  111. u32 srcr;
  112. u32 stcr;
  113. u32 scr;
  114. };
  115. static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
  116. {
  117. switch (reg) {
  118. case REG_SSI_SACCEN:
  119. case REG_SSI_SACCDIS:
  120. return false;
  121. default:
  122. return true;
  123. }
  124. }
  125. static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
  126. {
  127. switch (reg) {
  128. case REG_SSI_STX0:
  129. case REG_SSI_STX1:
  130. case REG_SSI_SRX0:
  131. case REG_SSI_SRX1:
  132. case REG_SSI_SISR:
  133. case REG_SSI_SFCSR:
  134. case REG_SSI_SACNT:
  135. case REG_SSI_SACADD:
  136. case REG_SSI_SACDAT:
  137. case REG_SSI_SATAG:
  138. case REG_SSI_SACCST:
  139. case REG_SSI_SOR:
  140. return true;
  141. default:
  142. return false;
  143. }
  144. }
  145. static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
  146. {
  147. switch (reg) {
  148. case REG_SSI_SRX0:
  149. case REG_SSI_SRX1:
  150. case REG_SSI_SISR:
  151. case REG_SSI_SACADD:
  152. case REG_SSI_SACDAT:
  153. case REG_SSI_SATAG:
  154. return true;
  155. default:
  156. return false;
  157. }
  158. }
  159. static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
  160. {
  161. switch (reg) {
  162. case REG_SSI_SRX0:
  163. case REG_SSI_SRX1:
  164. case REG_SSI_SACCST:
  165. return false;
  166. default:
  167. return true;
  168. }
  169. }
  170. static const struct regmap_config fsl_ssi_regconfig = {
  171. .max_register = REG_SSI_SACCDIS,
  172. .reg_bits = 32,
  173. .val_bits = 32,
  174. .reg_stride = 4,
  175. .val_format_endian = REGMAP_ENDIAN_NATIVE,
  176. .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
  177. .readable_reg = fsl_ssi_readable_reg,
  178. .volatile_reg = fsl_ssi_volatile_reg,
  179. .precious_reg = fsl_ssi_precious_reg,
  180. .writeable_reg = fsl_ssi_writeable_reg,
  181. .cache_type = REGCACHE_FLAT,
  182. };
  183. struct fsl_ssi_soc_data {
  184. bool imx;
  185. bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
  186. bool offline_config;
  187. u32 sisr_write_mask;
  188. };
  189. /**
  190. * struct fsl_ssi - per-SSI private data
  191. * @regs: Pointer to the regmap registers
  192. * @irq: IRQ of this SSI
  193. * @cpu_dai_drv: CPU DAI driver for this device
  194. * @dai_fmt: DAI configuration this device is currently used with
  195. * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
  196. * @i2s_net: I2S and Network mode configurations of SCR register
  197. * (this is the initial settings based on the DAI format)
  198. * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
  199. * @use_dma: DMA is used or FIQ with stream filter
  200. * @use_dual_fifo: DMA with support for dual FIFO mode
  201. * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
  202. * @fifo_depth: Depth of the SSI FIFOs
  203. * @slot_width: Width of each DAI slot
  204. * @slots: Number of slots
  205. * @regvals: Specific RX/TX register settings
  206. * @clk: Clock source to access register
  207. * @baudclk: Clock source to generate bit and frame-sync clocks
  208. * @baudclk_streams: Active streams that are using baudclk
  209. * @regcache_sfcsr: Cache sfcsr register value during suspend and resume
  210. * @regcache_sacnt: Cache sacnt register value during suspend and resume
  211. * @dma_params_tx: DMA transmit parameters
  212. * @dma_params_rx: DMA receive parameters
  213. * @ssi_phys: physical address of the SSI registers
  214. * @fiq_params: FIQ stream filtering parameters
  215. * @card_pdev: Platform_device pointer to register a sound card for PowerPC or
  216. * to register a CODEC platform device for AC97
  217. * @card_name: Platform_device name to register a sound card for PowerPC or
  218. * to register a CODEC platform device for AC97
  219. * @card_idx: The index of SSI to register a sound card for PowerPC or
  220. * to register a CODEC platform device for AC97
  221. * @dbg_stats: Debugging statistics
  222. * @soc: SoC specific data
  223. * @dev: Pointer to &pdev->dev
  224. * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
  225. * @fifo_watermark or fewer words in TX fifo or
  226. * @fifo_watermark or more empty words in RX fifo.
  227. * @dma_maxburst: Max number of words to transfer in one go. So far,
  228. * this is always the same as fifo_watermark.
  229. * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
  230. */
  231. struct fsl_ssi {
  232. struct regmap *regs;
  233. int irq;
  234. struct snd_soc_dai_driver cpu_dai_drv;
  235. unsigned int dai_fmt;
  236. u8 streams;
  237. u8 i2s_net;
  238. bool synchronous;
  239. bool use_dma;
  240. bool use_dual_fifo;
  241. bool has_ipg_clk_name;
  242. unsigned int fifo_depth;
  243. unsigned int slot_width;
  244. unsigned int slots;
  245. struct fsl_ssi_regvals regvals[2];
  246. struct clk *clk;
  247. struct clk *baudclk;
  248. unsigned int baudclk_streams;
  249. u32 regcache_sfcsr;
  250. u32 regcache_sacnt;
  251. struct snd_dmaengine_dai_dma_data dma_params_tx;
  252. struct snd_dmaengine_dai_dma_data dma_params_rx;
  253. dma_addr_t ssi_phys;
  254. struct imx_pcm_fiq_params fiq_params;
  255. struct platform_device *card_pdev;
  256. char card_name[32];
  257. u32 card_idx;
  258. struct fsl_ssi_dbg dbg_stats;
  259. const struct fsl_ssi_soc_data *soc;
  260. struct device *dev;
  261. u32 fifo_watermark;
  262. u32 dma_maxburst;
  263. struct mutex ac97_reg_lock;
  264. };
  265. /*
  266. * SoC specific data
  267. *
  268. * Notes:
  269. * 1) SSI in earlier SoCS has critical bits in control registers that
  270. * cannot be changed after SSI starts running -- a software reset
  271. * (set SSIEN to 0) is required to change their values. So adding
  272. * an offline_config flag for these SoCs.
  273. * 2) SDMA is available since imx35. However, imx35 does not support
  274. * DMA bits changing when SSI is running, so set offline_config.
  275. * 3) imx51 and later versions support register configurations when
  276. * SSI is running (SSIEN); For these versions, DMA needs to be
  277. * configured before SSI sends DMA request to avoid an undefined
  278. * DMA request on the SDMA side.
  279. */
  280. static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
  281. .imx = false,
  282. .offline_config = true,
  283. .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
  284. SSI_SISR_ROE0 | SSI_SISR_ROE1 |
  285. SSI_SISR_TUE0 | SSI_SISR_TUE1,
  286. };
  287. static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
  288. .imx = true,
  289. .imx21regs = true,
  290. .offline_config = true,
  291. .sisr_write_mask = 0,
  292. };
  293. static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
  294. .imx = true,
  295. .offline_config = true,
  296. .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
  297. SSI_SISR_ROE0 | SSI_SISR_ROE1 |
  298. SSI_SISR_TUE0 | SSI_SISR_TUE1,
  299. };
  300. static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
  301. .imx = true,
  302. .offline_config = false,
  303. .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
  304. SSI_SISR_TUE0 | SSI_SISR_TUE1,
  305. };
  306. static const struct of_device_id fsl_ssi_ids[] = {
  307. { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
  308. { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
  309. { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
  310. { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
  311. {}
  312. };
  313. MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
  314. static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
  315. {
  316. return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
  317. SND_SOC_DAIFMT_AC97;
  318. }
  319. static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi)
  320. {
  321. return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
  322. SND_SOC_DAIFMT_CBS_CFS;
  323. }
  324. static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi)
  325. {
  326. return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
  327. SND_SOC_DAIFMT_CBM_CFS;
  328. }
  329. /**
  330. * fsl_ssi_irq - Interrupt handler to gather states
  331. * @irq: irq number
  332. * @dev_id: context
  333. */
  334. static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
  335. {
  336. struct fsl_ssi *ssi = dev_id;
  337. struct regmap *regs = ssi->regs;
  338. u32 sisr, sisr2;
  339. regmap_read(regs, REG_SSI_SISR, &sisr);
  340. sisr2 = sisr & ssi->soc->sisr_write_mask;
  341. /* Clear the bits that we set */
  342. if (sisr2)
  343. regmap_write(regs, REG_SSI_SISR, sisr2);
  344. fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
  345. return IRQ_HANDLED;
  346. }
  347. /**
  348. * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
  349. * cached values in regvals
  350. * @ssi: SSI context
  351. * @tx: direction
  352. *
  353. * Notes:
  354. * 1) For offline_config SoCs, enable all necessary bits of both streams
  355. * when 1st stream starts, even if the opposite stream will not start
  356. * 2) It also clears FIFO before setting regvals; SOR is safe to set online
  357. */
  358. static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
  359. {
  360. struct fsl_ssi_regvals *vals = ssi->regvals;
  361. int dir = tx ? TX : RX;
  362. u32 sier, srcr, stcr;
  363. /* Clear dirty data in the FIFO; It also prevents channel slipping */
  364. regmap_update_bits(ssi->regs, REG_SSI_SOR,
  365. SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
  366. /*
  367. * On offline_config SoCs, SxCR and SIER are already configured when
  368. * the previous stream started. So skip all SxCR and SIER settings
  369. * to prevent online reconfigurations, then jump to set SCR directly
  370. */
  371. if (ssi->soc->offline_config && ssi->streams)
  372. goto enable_scr;
  373. if (ssi->soc->offline_config) {
  374. /*
  375. * Online reconfiguration not supported, so enable all bits for
  376. * both streams at once to avoid necessity of reconfigurations
  377. */
  378. srcr = vals[RX].srcr | vals[TX].srcr;
  379. stcr = vals[RX].stcr | vals[TX].stcr;
  380. sier = vals[RX].sier | vals[TX].sier;
  381. } else {
  382. /* Otherwise, only set bits for the current stream */
  383. srcr = vals[dir].srcr;
  384. stcr = vals[dir].stcr;
  385. sier = vals[dir].sier;
  386. }
  387. /* Configure SRCR, STCR and SIER at once */
  388. regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
  389. regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
  390. regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
  391. enable_scr:
  392. /*
  393. * Start DMA before setting TE to avoid FIFO underrun
  394. * which may cause a channel slip or a channel swap
  395. *
  396. * TODO: FIQ cases might also need this upon testing
  397. */
  398. if (ssi->use_dma && tx) {
  399. int try = 100;
  400. u32 sfcsr;
  401. /* Enable SSI first to send TX DMA request */
  402. regmap_update_bits(ssi->regs, REG_SSI_SCR,
  403. SSI_SCR_SSIEN, SSI_SCR_SSIEN);
  404. /* Busy wait until TX FIFO not empty -- DMA working */
  405. do {
  406. regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
  407. if (SSI_SFCSR_TFCNT0(sfcsr))
  408. break;
  409. } while (--try);
  410. /* FIFO still empty -- something might be wrong */
  411. if (!SSI_SFCSR_TFCNT0(sfcsr))
  412. dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
  413. }
  414. /* Enable all remaining bits in SCR */
  415. regmap_update_bits(ssi->regs, REG_SSI_SCR,
  416. vals[dir].scr, vals[dir].scr);
  417. /* Log the enabled stream to the mask */
  418. ssi->streams |= BIT(dir);
  419. }
  420. /*
  421. * Exclude bits that are used by the opposite stream
  422. *
  423. * When both streams are active, disabling some bits for the current stream
  424. * might break the other stream if these bits are used by it.
  425. *
  426. * @vals : regvals of the current stream
  427. * @avals: regvals of the opposite stream
  428. * @aactive: active state of the opposite stream
  429. *
  430. * 1) XOR vals and avals to get the differences if the other stream is active;
  431. * Otherwise, return current vals if the other stream is not active
  432. * 2) AND the result of 1) with the current vals
  433. */
  434. #define _ssi_xor_shared_bits(vals, avals, aactive) \
  435. ((vals) ^ ((avals) * (aactive)))
  436. #define ssi_excl_shared_bits(vals, avals, aactive) \
  437. ((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
  438. /**
  439. * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
  440. * with cached values in regvals
  441. * @ssi: SSI context
  442. * @tx: direction
  443. *
  444. * Notes:
  445. * 1) For offline_config SoCs, to avoid online reconfigurations, disable all
  446. * bits of both streams at once when the last stream is abort to end
  447. * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
  448. */
  449. static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
  450. {
  451. struct fsl_ssi_regvals *vals, *avals;
  452. u32 sier, srcr, stcr, scr;
  453. int adir = tx ? RX : TX;
  454. int dir = tx ? TX : RX;
  455. bool aactive;
  456. /* Check if the opposite stream is active */
  457. aactive = ssi->streams & BIT(adir);
  458. vals = &ssi->regvals[dir];
  459. /* Get regvals of the opposite stream to keep opposite stream safe */
  460. avals = &ssi->regvals[adir];
  461. /*
  462. * To keep the other stream safe, exclude shared bits between
  463. * both streams, and get safe bits to disable current stream
  464. */
  465. scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
  466. /* Disable safe bits of SCR register for the current stream */
  467. regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
  468. /* Log the disabled stream to the mask */
  469. ssi->streams &= ~BIT(dir);
  470. /*
  471. * On offline_config SoCs, if the other stream is active, skip
  472. * SxCR and SIER settings to prevent online reconfigurations
  473. */
  474. if (ssi->soc->offline_config && aactive)
  475. goto fifo_clear;
  476. if (ssi->soc->offline_config) {
  477. /* Now there is only current stream active, disable all bits */
  478. srcr = vals->srcr | avals->srcr;
  479. stcr = vals->stcr | avals->stcr;
  480. sier = vals->sier | avals->sier;
  481. } else {
  482. /*
  483. * To keep the other stream safe, exclude shared bits between
  484. * both streams, and get safe bits to disable current stream
  485. */
  486. sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
  487. srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
  488. stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
  489. }
  490. /* Clear configurations of SRCR, STCR and SIER at once */
  491. regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
  492. regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
  493. regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
  494. fifo_clear:
  495. /* Clear remaining data in the FIFO */
  496. regmap_update_bits(ssi->regs, REG_SSI_SOR,
  497. SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
  498. }
  499. static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
  500. {
  501. struct regmap *regs = ssi->regs;
  502. /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
  503. if (!ssi->soc->imx21regs) {
  504. /* Disable all channel slots */
  505. regmap_write(regs, REG_SSI_SACCDIS, 0xff);
  506. /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
  507. regmap_write(regs, REG_SSI_SACCEN, 0x300);
  508. }
  509. }
  510. /**
  511. * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
  512. * SCR to later set them safely
  513. * @ssi: SSI context
  514. */
  515. static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
  516. {
  517. struct fsl_ssi_regvals *vals = ssi->regvals;
  518. vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
  519. vals[RX].srcr = SSI_SRCR_RFEN0;
  520. vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
  521. vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
  522. vals[TX].stcr = SSI_STCR_TFEN0;
  523. vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
  524. /* AC97 has already enabled SSIEN, RE and TE, so ignore them */
  525. if (fsl_ssi_is_ac97(ssi))
  526. vals[RX].scr = vals[TX].scr = 0;
  527. if (ssi->use_dual_fifo) {
  528. vals[RX].srcr |= SSI_SRCR_RFEN1;
  529. vals[TX].stcr |= SSI_STCR_TFEN1;
  530. }
  531. if (ssi->use_dma) {
  532. vals[RX].sier |= SSI_SIER_RDMAE;
  533. vals[TX].sier |= SSI_SIER_TDMAE;
  534. } else {
  535. vals[RX].sier |= SSI_SIER_RIE;
  536. vals[TX].sier |= SSI_SIER_TIE;
  537. }
  538. }
  539. static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
  540. {
  541. struct regmap *regs = ssi->regs;
  542. /* Setup the clock control register */
  543. regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
  544. regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
  545. /* Enable AC97 mode and startup the SSI */
  546. regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
  547. /* AC97 has to communicate with codec before starting a stream */
  548. regmap_update_bits(regs, REG_SSI_SCR,
  549. SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
  550. SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
  551. regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
  552. }
  553. static int fsl_ssi_startup(struct snd_pcm_substream *substream,
  554. struct snd_soc_dai *dai)
  555. {
  556. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  557. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  558. int ret;
  559. ret = clk_prepare_enable(ssi->clk);
  560. if (ret)
  561. return ret;
  562. /*
  563. * When using dual fifo mode, it is safer to ensure an even period
  564. * size. If appearing to an odd number while DMA always starts its
  565. * task from fifo0, fifo1 would be neglected at the end of each
  566. * period. But SSI would still access fifo1 with an invalid data.
  567. */
  568. if (ssi->use_dual_fifo)
  569. snd_pcm_hw_constraint_step(substream->runtime, 0,
  570. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
  571. return 0;
  572. }
  573. static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
  574. struct snd_soc_dai *dai)
  575. {
  576. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  577. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  578. clk_disable_unprepare(ssi->clk);
  579. }
  580. /**
  581. * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
  582. * @substream: ASoC substream
  583. * @dai: pointer to DAI
  584. * @hw_params: pointers to hw_params
  585. *
  586. * Notes: This function can be only called when using SSI as DAI master
  587. *
  588. * Quick instruction for parameters:
  589. * freq: Output BCLK frequency = samplerate * slots * slot_width
  590. * (In 2-channel I2S Master mode, slot_width is fixed 32)
  591. */
  592. static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
  593. struct snd_soc_dai *dai,
  594. struct snd_pcm_hw_params *hw_params)
  595. {
  596. bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  597. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
  598. struct regmap *regs = ssi->regs;
  599. u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
  600. unsigned long clkrate, baudrate, tmprate;
  601. unsigned int channels = params_channels(hw_params);
  602. unsigned int slot_width = params_width(hw_params);
  603. unsigned int slots = 2;
  604. u64 sub, savesub = 100000;
  605. unsigned int freq;
  606. bool baudclk_is_used;
  607. int ret;
  608. /* Override slots and slot_width if being specifically set... */
  609. if (ssi->slots)
  610. slots = ssi->slots;
  611. if (ssi->slot_width)
  612. slot_width = ssi->slot_width;
  613. /* ...but force 32 bits for stereo audio using I2S Master Mode */
  614. if (channels == 2 &&
  615. (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
  616. slot_width = 32;
  617. /* Generate bit clock based on the slot number and slot width */
  618. freq = slots * slot_width * params_rate(hw_params);
  619. /* Don't apply it to any non-baudclk circumstance */
  620. if (IS_ERR(ssi->baudclk))
  621. return -EINVAL;
  622. /*
  623. * Hardware limitation: The bclk rate must be
  624. * never greater than 1/5 IPG clock rate
  625. */
  626. if (freq * 5 > clk_get_rate(ssi->clk)) {
  627. dev_err(dai->dev, "bitclk > ipgclk / 5\n");
  628. return -EINVAL;
  629. }
  630. baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
  631. /* It should be already enough to divide clock by setting pm alone */
  632. psr = 0;
  633. div2 = 0;
  634. factor = (div2 + 1) * (7 * psr + 1) * 2;
  635. for (i = 0; i < 255; i++) {
  636. tmprate = freq * factor * (i + 1);
  637. if (baudclk_is_used)
  638. clkrate = clk_get_rate(ssi->baudclk);
  639. else
  640. clkrate = clk_round_rate(ssi->baudclk, tmprate);
  641. clkrate /= factor;
  642. afreq = clkrate / (i + 1);
  643. if (freq == afreq)
  644. sub = 0;
  645. else if (freq / afreq == 1)
  646. sub = freq - afreq;
  647. else if (afreq / freq == 1)
  648. sub = afreq - freq;
  649. else
  650. continue;
  651. /* Calculate the fraction */
  652. sub *= 100000;
  653. do_div(sub, freq);
  654. if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
  655. baudrate = tmprate;
  656. savesub = sub;
  657. pm = i;
  658. }
  659. /* We are lucky */
  660. if (savesub == 0)
  661. break;
  662. }
  663. /* No proper pm found if it is still remaining the initial value */
  664. if (pm == 999) {
  665. dev_err(dai->dev, "failed to handle the required sysclk\n");
  666. return -EINVAL;
  667. }
  668. stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
  669. (psr ? SSI_SxCCR_PSR : 0);
  670. mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
  671. /* STCCR is used for RX in synchronous mode */
  672. tx2 = tx || ssi->synchronous;
  673. regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
  674. if (!baudclk_is_used) {
  675. ret = clk_set_rate(ssi->baudclk, baudrate);
  676. if (ret) {
  677. dev_err(dai->dev, "failed to set baudclk rate\n");
  678. return -EINVAL;
  679. }
  680. }
  681. return 0;
  682. }
  683. /**
  684. * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
  685. * @substream: ASoC substream
  686. * @hw_params: pointers to hw_params
  687. * @dai: pointer to DAI
  688. *
  689. * Notes:
  690. * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
  691. * disabled on offline_config SoCs. Even for online configurable SoCs
  692. * running in synchronous mode (both TX and RX use STCCR), it is not
  693. * safe to re-configure them when both two streams start running.
  694. * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
  695. * fsl_ssi_set_bclk() if SSI is the DAI clock master.
  696. */
  697. static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
  698. struct snd_pcm_hw_params *hw_params,
  699. struct snd_soc_dai *dai)
  700. {
  701. bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  702. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
  703. struct regmap *regs = ssi->regs;
  704. unsigned int channels = params_channels(hw_params);
  705. unsigned int sample_size = params_width(hw_params);
  706. u32 wl = SSI_SxCCR_WL(sample_size);
  707. int ret;
  708. if (fsl_ssi_is_i2s_master(ssi)) {
  709. ret = fsl_ssi_set_bclk(substream, dai, hw_params);
  710. if (ret)
  711. return ret;
  712. /* Do not enable the clock if it is already enabled */
  713. if (!(ssi->baudclk_streams & BIT(substream->stream))) {
  714. ret = clk_prepare_enable(ssi->baudclk);
  715. if (ret)
  716. return ret;
  717. ssi->baudclk_streams |= BIT(substream->stream);
  718. }
  719. }
  720. /*
  721. * SSI is properly configured if it is enabled and running in
  722. * the synchronous mode; Note that AC97 mode is an exception
  723. * that should set separate configurations for STCCR and SRCCR
  724. * despite running in the synchronous mode.
  725. */
  726. if (ssi->streams && ssi->synchronous)
  727. return 0;
  728. if (!fsl_ssi_is_ac97(ssi)) {
  729. /*
  730. * Keep the ssi->i2s_net intact while having a local variable
  731. * to override settings for special use cases. Otherwise, the
  732. * ssi->i2s_net will lose the settings for regular use cases.
  733. */
  734. u8 i2s_net = ssi->i2s_net;
  735. /* Normal + Network mode to send 16-bit data in 32-bit frames */
  736. if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
  737. i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
  738. /* Use Normal mode to send mono data at 1st slot of 2 slots */
  739. if (channels == 1)
  740. i2s_net = SSI_SCR_I2S_MODE_NORMAL;
  741. regmap_update_bits(regs, REG_SSI_SCR,
  742. SSI_SCR_I2S_NET_MASK, i2s_net);
  743. }
  744. /* In synchronous mode, the SSI uses STCCR for capture */
  745. tx2 = tx || ssi->synchronous;
  746. regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
  747. return 0;
  748. }
  749. static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
  750. struct snd_soc_dai *dai)
  751. {
  752. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  753. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  754. if (fsl_ssi_is_i2s_master(ssi) &&
  755. ssi->baudclk_streams & BIT(substream->stream)) {
  756. clk_disable_unprepare(ssi->baudclk);
  757. ssi->baudclk_streams &= ~BIT(substream->stream);
  758. }
  759. return 0;
  760. }
  761. static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
  762. {
  763. u32 strcr = 0, scr = 0, stcr, srcr, mask;
  764. unsigned int slots;
  765. ssi->dai_fmt = fmt;
  766. /* Synchronize frame sync clock for TE to avoid data slipping */
  767. scr |= SSI_SCR_SYNC_TX_FS;
  768. /* Set to default shifting settings: LSB_ALIGNED */
  769. strcr |= SSI_STCR_TXBIT0;
  770. /* Use Network mode as default */
  771. ssi->i2s_net = SSI_SCR_NET;
  772. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  773. case SND_SOC_DAIFMT_I2S:
  774. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  775. case SND_SOC_DAIFMT_CBS_CFS:
  776. if (IS_ERR(ssi->baudclk)) {
  777. dev_err(ssi->dev,
  778. "missing baudclk for master mode\n");
  779. return -EINVAL;
  780. }
  781. fallthrough;
  782. case SND_SOC_DAIFMT_CBM_CFS:
  783. ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
  784. break;
  785. case SND_SOC_DAIFMT_CBM_CFM:
  786. ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
  787. break;
  788. default:
  789. return -EINVAL;
  790. }
  791. slots = ssi->slots ? : 2;
  792. regmap_update_bits(ssi->regs, REG_SSI_STCCR,
  793. SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
  794. regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
  795. SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
  796. /* Data on rising edge of bclk, frame low, 1clk before data */
  797. strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
  798. break;
  799. case SND_SOC_DAIFMT_LEFT_J:
  800. /* Data on rising edge of bclk, frame high */
  801. strcr |= SSI_STCR_TSCKP;
  802. break;
  803. case SND_SOC_DAIFMT_DSP_A:
  804. /* Data on rising edge of bclk, frame high, 1clk before data */
  805. strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
  806. break;
  807. case SND_SOC_DAIFMT_DSP_B:
  808. /* Data on rising edge of bclk, frame high */
  809. strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
  810. break;
  811. case SND_SOC_DAIFMT_AC97:
  812. /* Data on falling edge of bclk, frame high, 1clk before data */
  813. strcr |= SSI_STCR_TEFS;
  814. break;
  815. default:
  816. return -EINVAL;
  817. }
  818. scr |= ssi->i2s_net;
  819. /* DAI clock inversion */
  820. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  821. case SND_SOC_DAIFMT_NB_NF:
  822. /* Nothing to do for both normal cases */
  823. break;
  824. case SND_SOC_DAIFMT_IB_NF:
  825. /* Invert bit clock */
  826. strcr ^= SSI_STCR_TSCKP;
  827. break;
  828. case SND_SOC_DAIFMT_NB_IF:
  829. /* Invert frame clock */
  830. strcr ^= SSI_STCR_TFSI;
  831. break;
  832. case SND_SOC_DAIFMT_IB_IF:
  833. /* Invert both clocks */
  834. strcr ^= SSI_STCR_TSCKP;
  835. strcr ^= SSI_STCR_TFSI;
  836. break;
  837. default:
  838. return -EINVAL;
  839. }
  840. /* DAI clock master masks */
  841. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  842. case SND_SOC_DAIFMT_CBS_CFS:
  843. /* Output bit and frame sync clocks */
  844. strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
  845. scr |= SSI_SCR_SYS_CLK_EN;
  846. break;
  847. case SND_SOC_DAIFMT_CBM_CFM:
  848. /* Input bit or frame sync clocks */
  849. break;
  850. case SND_SOC_DAIFMT_CBM_CFS:
  851. /* Input bit clock but output frame sync clock */
  852. strcr |= SSI_STCR_TFDIR;
  853. break;
  854. default:
  855. return -EINVAL;
  856. }
  857. stcr = strcr;
  858. srcr = strcr;
  859. /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
  860. if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
  861. srcr &= ~SSI_SRCR_RXDIR;
  862. scr |= SSI_SCR_SYN;
  863. }
  864. mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
  865. SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
  866. regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
  867. regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
  868. mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
  869. SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
  870. regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
  871. return 0;
  872. }
  873. /**
  874. * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
  875. * @dai: pointer to DAI
  876. * @fmt: format mask
  877. */
  878. static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  879. {
  880. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
  881. /* AC97 configured DAIFMT earlier in the probe() */
  882. if (fsl_ssi_is_ac97(ssi))
  883. return 0;
  884. return _fsl_ssi_set_dai_fmt(ssi, fmt);
  885. }
  886. /**
  887. * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
  888. * @dai: pointer to DAI
  889. * @tx_mask: mask for TX
  890. * @rx_mask: mask for RX
  891. * @slots: number of slots
  892. * @slot_width: number of bits per slot
  893. */
  894. static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
  895. u32 rx_mask, int slots, int slot_width)
  896. {
  897. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
  898. struct regmap *regs = ssi->regs;
  899. u32 val;
  900. /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
  901. if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
  902. dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
  903. return -EINVAL;
  904. }
  905. /* The slot number should be >= 2 if using Network mode or I2S mode */
  906. if (ssi->i2s_net && slots < 2) {
  907. dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
  908. return -EINVAL;
  909. }
  910. regmap_update_bits(regs, REG_SSI_STCCR,
  911. SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
  912. regmap_update_bits(regs, REG_SSI_SRCCR,
  913. SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
  914. /* Save the SCR register value */
  915. regmap_read(regs, REG_SSI_SCR, &val);
  916. /* Temporarily enable SSI to allow SxMSKs to be configurable */
  917. regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
  918. regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
  919. regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
  920. /* Restore the value of SSIEN bit */
  921. regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
  922. ssi->slot_width = slot_width;
  923. ssi->slots = slots;
  924. return 0;
  925. }
  926. /**
  927. * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
  928. * @substream: ASoC substream
  929. * @cmd: trigger command
  930. * @dai: pointer to DAI
  931. *
  932. * The DMA channel is in external master start and pause mode, which
  933. * means the SSI completely controls the flow of data.
  934. */
  935. static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
  936. struct snd_soc_dai *dai)
  937. {
  938. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  939. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  940. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  941. switch (cmd) {
  942. case SNDRV_PCM_TRIGGER_START:
  943. case SNDRV_PCM_TRIGGER_RESUME:
  944. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  945. /*
  946. * SACCST might be modified via AC Link by a CODEC if it sends
  947. * extra bits in their SLOTREQ requests, which'll accidentally
  948. * send valid data to slots other than normal playback slots.
  949. *
  950. * To be safe, configure SACCST right before TX starts.
  951. */
  952. if (tx && fsl_ssi_is_ac97(ssi))
  953. fsl_ssi_tx_ac97_saccst_setup(ssi);
  954. fsl_ssi_config_enable(ssi, tx);
  955. break;
  956. case SNDRV_PCM_TRIGGER_STOP:
  957. case SNDRV_PCM_TRIGGER_SUSPEND:
  958. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  959. fsl_ssi_config_disable(ssi, tx);
  960. break;
  961. default:
  962. return -EINVAL;
  963. }
  964. return 0;
  965. }
  966. static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
  967. {
  968. struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
  969. if (ssi->soc->imx && ssi->use_dma)
  970. snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
  971. &ssi->dma_params_rx);
  972. return 0;
  973. }
  974. static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
  975. .startup = fsl_ssi_startup,
  976. .shutdown = fsl_ssi_shutdown,
  977. .hw_params = fsl_ssi_hw_params,
  978. .hw_free = fsl_ssi_hw_free,
  979. .set_fmt = fsl_ssi_set_dai_fmt,
  980. .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
  981. .trigger = fsl_ssi_trigger,
  982. };
  983. static struct snd_soc_dai_driver fsl_ssi_dai_template = {
  984. .probe = fsl_ssi_dai_probe,
  985. .playback = {
  986. .stream_name = "CPU-Playback",
  987. .channels_min = 1,
  988. .channels_max = 32,
  989. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  990. .formats = FSLSSI_I2S_FORMATS,
  991. },
  992. .capture = {
  993. .stream_name = "CPU-Capture",
  994. .channels_min = 1,
  995. .channels_max = 32,
  996. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  997. .formats = FSLSSI_I2S_FORMATS,
  998. },
  999. .ops = &fsl_ssi_dai_ops,
  1000. };
  1001. static const struct snd_soc_component_driver fsl_ssi_component = {
  1002. .name = "fsl-ssi",
  1003. };
  1004. static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
  1005. .symmetric_channels = 1,
  1006. .probe = fsl_ssi_dai_probe,
  1007. .playback = {
  1008. .stream_name = "AC97 Playback",
  1009. .channels_min = 2,
  1010. .channels_max = 2,
  1011. .rates = SNDRV_PCM_RATE_8000_48000,
  1012. .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
  1013. },
  1014. .capture = {
  1015. .stream_name = "AC97 Capture",
  1016. .channels_min = 2,
  1017. .channels_max = 2,
  1018. .rates = SNDRV_PCM_RATE_48000,
  1019. /* 16-bit capture is broken (errata ERR003778) */
  1020. .formats = SNDRV_PCM_FMTBIT_S20,
  1021. },
  1022. .ops = &fsl_ssi_dai_ops,
  1023. };
  1024. static struct fsl_ssi *fsl_ac97_data;
  1025. static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  1026. unsigned short val)
  1027. {
  1028. struct regmap *regs = fsl_ac97_data->regs;
  1029. unsigned int lreg;
  1030. unsigned int lval;
  1031. int ret;
  1032. if (reg > 0x7f)
  1033. return;
  1034. mutex_lock(&fsl_ac97_data->ac97_reg_lock);
  1035. ret = clk_prepare_enable(fsl_ac97_data->clk);
  1036. if (ret) {
  1037. pr_err("ac97 write clk_prepare_enable failed: %d\n",
  1038. ret);
  1039. goto ret_unlock;
  1040. }
  1041. lreg = reg << 12;
  1042. regmap_write(regs, REG_SSI_SACADD, lreg);
  1043. lval = val << 4;
  1044. regmap_write(regs, REG_SSI_SACDAT, lval);
  1045. regmap_update_bits(regs, REG_SSI_SACNT,
  1046. SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
  1047. udelay(100);
  1048. clk_disable_unprepare(fsl_ac97_data->clk);
  1049. ret_unlock:
  1050. mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
  1051. }
  1052. static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
  1053. unsigned short reg)
  1054. {
  1055. struct regmap *regs = fsl_ac97_data->regs;
  1056. unsigned short val = 0;
  1057. u32 reg_val;
  1058. unsigned int lreg;
  1059. int ret;
  1060. mutex_lock(&fsl_ac97_data->ac97_reg_lock);
  1061. ret = clk_prepare_enable(fsl_ac97_data->clk);
  1062. if (ret) {
  1063. pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
  1064. goto ret_unlock;
  1065. }
  1066. lreg = (reg & 0x7f) << 12;
  1067. regmap_write(regs, REG_SSI_SACADD, lreg);
  1068. regmap_update_bits(regs, REG_SSI_SACNT,
  1069. SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
  1070. udelay(100);
  1071. regmap_read(regs, REG_SSI_SACDAT, &reg_val);
  1072. val = (reg_val >> 4) & 0xffff;
  1073. clk_disable_unprepare(fsl_ac97_data->clk);
  1074. ret_unlock:
  1075. mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
  1076. return val;
  1077. }
  1078. static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
  1079. .read = fsl_ssi_ac97_read,
  1080. .write = fsl_ssi_ac97_write,
  1081. };
  1082. /**
  1083. * fsl_ssi_hw_init - Initialize SSI registers
  1084. * @ssi: SSI context
  1085. */
  1086. static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
  1087. {
  1088. u32 wm = ssi->fifo_watermark;
  1089. /* Initialize regvals */
  1090. fsl_ssi_setup_regvals(ssi);
  1091. /* Set watermarks */
  1092. regmap_write(ssi->regs, REG_SSI_SFCSR,
  1093. SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
  1094. SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
  1095. /* Enable Dual FIFO mode */
  1096. if (ssi->use_dual_fifo)
  1097. regmap_update_bits(ssi->regs, REG_SSI_SCR,
  1098. SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
  1099. /* AC97 should start earlier to communicate with CODECs */
  1100. if (fsl_ssi_is_ac97(ssi)) {
  1101. _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
  1102. fsl_ssi_setup_ac97(ssi);
  1103. }
  1104. return 0;
  1105. }
  1106. /**
  1107. * fsl_ssi_hw_clean - Clear SSI registers
  1108. * @ssi: SSI context
  1109. */
  1110. static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
  1111. {
  1112. /* Disable registers for AC97 */
  1113. if (fsl_ssi_is_ac97(ssi)) {
  1114. /* Disable TE and RE bits first */
  1115. regmap_update_bits(ssi->regs, REG_SSI_SCR,
  1116. SSI_SCR_TE | SSI_SCR_RE, 0);
  1117. /* Disable AC97 mode */
  1118. regmap_write(ssi->regs, REG_SSI_SACNT, 0);
  1119. /* Unset WAIT bits */
  1120. regmap_write(ssi->regs, REG_SSI_SOR, 0);
  1121. /* Disable SSI -- software reset */
  1122. regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
  1123. }
  1124. }
  1125. /*
  1126. * Make every character in a string lower-case
  1127. */
  1128. static void make_lowercase(char *s)
  1129. {
  1130. if (!s)
  1131. return;
  1132. for (; *s; s++)
  1133. *s = tolower(*s);
  1134. }
  1135. static int fsl_ssi_imx_probe(struct platform_device *pdev,
  1136. struct fsl_ssi *ssi, void __iomem *iomem)
  1137. {
  1138. struct device *dev = &pdev->dev;
  1139. int ret;
  1140. /* Backward compatible for a DT without ipg clock name assigned */
  1141. if (ssi->has_ipg_clk_name)
  1142. ssi->clk = devm_clk_get(dev, "ipg");
  1143. else
  1144. ssi->clk = devm_clk_get(dev, NULL);
  1145. if (IS_ERR(ssi->clk)) {
  1146. ret = PTR_ERR(ssi->clk);
  1147. dev_err(dev, "failed to get clock: %d\n", ret);
  1148. return ret;
  1149. }
  1150. /* Enable the clock since regmap will not handle it in this case */
  1151. if (!ssi->has_ipg_clk_name) {
  1152. ret = clk_prepare_enable(ssi->clk);
  1153. if (ret) {
  1154. dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
  1155. return ret;
  1156. }
  1157. }
  1158. /* Do not error out for slave cases that live without a baud clock */
  1159. ssi->baudclk = devm_clk_get(dev, "baud");
  1160. if (IS_ERR(ssi->baudclk))
  1161. dev_dbg(dev, "failed to get baud clock: %ld\n",
  1162. PTR_ERR(ssi->baudclk));
  1163. ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
  1164. ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
  1165. ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
  1166. ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
  1167. /* Use even numbers to avoid channel swap due to SDMA script design */
  1168. if (ssi->use_dual_fifo) {
  1169. ssi->dma_params_tx.maxburst &= ~0x1;
  1170. ssi->dma_params_rx.maxburst &= ~0x1;
  1171. }
  1172. if (!ssi->use_dma) {
  1173. /*
  1174. * Some boards use an incompatible codec. Use imx-fiq-pcm-audio
  1175. * to get it working, as DMA is not possible in this situation.
  1176. */
  1177. ssi->fiq_params.irq = ssi->irq;
  1178. ssi->fiq_params.base = iomem;
  1179. ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
  1180. ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
  1181. ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
  1182. if (ret)
  1183. goto error_pcm;
  1184. } else {
  1185. ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
  1186. if (ret)
  1187. goto error_pcm;
  1188. }
  1189. return 0;
  1190. error_pcm:
  1191. if (!ssi->has_ipg_clk_name)
  1192. clk_disable_unprepare(ssi->clk);
  1193. return ret;
  1194. }
  1195. static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
  1196. {
  1197. if (!ssi->use_dma)
  1198. imx_pcm_fiq_exit(pdev);
  1199. if (!ssi->has_ipg_clk_name)
  1200. clk_disable_unprepare(ssi->clk);
  1201. }
  1202. static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
  1203. {
  1204. struct device *dev = ssi->dev;
  1205. struct device_node *np = dev->of_node;
  1206. const struct of_device_id *of_id;
  1207. const char *p, *sprop;
  1208. const __be32 *iprop;
  1209. u32 dmas[4];
  1210. int ret;
  1211. of_id = of_match_device(fsl_ssi_ids, dev);
  1212. if (!of_id || !of_id->data)
  1213. return -EINVAL;
  1214. ssi->soc = of_id->data;
  1215. ret = of_property_match_string(np, "clock-names", "ipg");
  1216. /* Get error code if not found */
  1217. ssi->has_ipg_clk_name = ret >= 0;
  1218. /* Check if being used in AC97 mode */
  1219. sprop = of_get_property(np, "fsl,mode", NULL);
  1220. if (sprop && !strcmp(sprop, "ac97-slave")) {
  1221. ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
  1222. ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
  1223. if (ret) {
  1224. dev_err(dev, "failed to get SSI index property\n");
  1225. return -EINVAL;
  1226. }
  1227. strcpy(ssi->card_name, "ac97-codec");
  1228. } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
  1229. /*
  1230. * In synchronous mode, STCK and STFS ports are used by RX
  1231. * as well. So the software should limit the sample rates,
  1232. * sample bits and channels to be symmetric.
  1233. *
  1234. * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
  1235. * in the SSI synchronous mode however it does not have to
  1236. * limit symmetric sample rates and sample bits.
  1237. */
  1238. ssi->synchronous = true;
  1239. }
  1240. /* Select DMA or FIQ */
  1241. ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
  1242. /* Fetch FIFO depth; Set to 8 for older DT without this property */
  1243. iprop = of_get_property(np, "fsl,fifo-depth", NULL);
  1244. if (iprop)
  1245. ssi->fifo_depth = be32_to_cpup(iprop);
  1246. else
  1247. ssi->fifo_depth = 8;
  1248. /* Use dual FIFO mode depending on the support from SDMA script */
  1249. ret = of_property_read_u32_array(np, "dmas", dmas, 4);
  1250. if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
  1251. ssi->use_dual_fifo = true;
  1252. /*
  1253. * Backward compatible for older bindings by manually triggering the
  1254. * machine driver's probe(). Use /compatible property, including the
  1255. * address of CPU DAI driver structure, as the name of machine driver
  1256. *
  1257. * If card_name is set by AC97 earlier, bypass here since it uses a
  1258. * different name to register the device.
  1259. */
  1260. if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
  1261. struct device_node *root = of_find_node_by_path("/");
  1262. sprop = of_get_property(root, "compatible", NULL);
  1263. of_node_put(root);
  1264. /* Strip "fsl," in the compatible name if applicable */
  1265. p = strrchr(sprop, ',');
  1266. if (p)
  1267. sprop = p + 1;
  1268. snprintf(ssi->card_name, sizeof(ssi->card_name),
  1269. "snd-soc-%s", sprop);
  1270. make_lowercase(ssi->card_name);
  1271. ssi->card_idx = 0;
  1272. }
  1273. return 0;
  1274. }
  1275. static int fsl_ssi_probe(struct platform_device *pdev)
  1276. {
  1277. struct regmap_config regconfig = fsl_ssi_regconfig;
  1278. struct device *dev = &pdev->dev;
  1279. struct fsl_ssi *ssi;
  1280. struct resource *res;
  1281. void __iomem *iomem;
  1282. int ret = 0;
  1283. ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
  1284. if (!ssi)
  1285. return -ENOMEM;
  1286. ssi->dev = dev;
  1287. /* Probe from DT */
  1288. ret = fsl_ssi_probe_from_dt(ssi);
  1289. if (ret)
  1290. return ret;
  1291. if (fsl_ssi_is_ac97(ssi)) {
  1292. memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
  1293. sizeof(fsl_ssi_ac97_dai));
  1294. fsl_ac97_data = ssi;
  1295. } else {
  1296. memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
  1297. sizeof(fsl_ssi_dai_template));
  1298. }
  1299. ssi->cpu_dai_drv.name = dev_name(dev);
  1300. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1301. iomem = devm_ioremap_resource(dev, res);
  1302. if (IS_ERR(iomem))
  1303. return PTR_ERR(iomem);
  1304. ssi->ssi_phys = res->start;
  1305. if (ssi->soc->imx21regs) {
  1306. /* No SACC{ST,EN,DIS} regs in imx21-class SSI */
  1307. regconfig.max_register = REG_SSI_SRMSK;
  1308. regconfig.num_reg_defaults_raw =
  1309. REG_SSI_SRMSK / sizeof(uint32_t) + 1;
  1310. }
  1311. if (ssi->has_ipg_clk_name)
  1312. ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
  1313. &regconfig);
  1314. else
  1315. ssi->regs = devm_regmap_init_mmio(dev, iomem, &regconfig);
  1316. if (IS_ERR(ssi->regs)) {
  1317. dev_err(dev, "failed to init register map\n");
  1318. return PTR_ERR(ssi->regs);
  1319. }
  1320. ssi->irq = platform_get_irq(pdev, 0);
  1321. if (ssi->irq < 0)
  1322. return ssi->irq;
  1323. /* Set software limitations for synchronous mode except AC97 */
  1324. if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
  1325. ssi->cpu_dai_drv.symmetric_rates = 1;
  1326. ssi->cpu_dai_drv.symmetric_channels = 1;
  1327. ssi->cpu_dai_drv.symmetric_samplebits = 1;
  1328. }
  1329. /*
  1330. * Configure TX and RX DMA watermarks -- when to send a DMA request
  1331. *
  1332. * Values should be tested to avoid FIFO under/over run. Set maxburst
  1333. * to fifo_watermark to maxiumize DMA transaction to reduce overhead.
  1334. */
  1335. switch (ssi->fifo_depth) {
  1336. case 15:
  1337. /*
  1338. * Set to 8 as a balanced configuration -- When TX FIFO has 8
  1339. * empty slots, send a DMA request to fill these 8 slots. The
  1340. * remaining 7 slots should be able to allow DMA to finish the
  1341. * transaction before TX FIFO underruns; Same applies to RX.
  1342. *
  1343. * Tested with cases running at 48kHz @ 16 bits x 16 channels
  1344. */
  1345. ssi->fifo_watermark = 8;
  1346. ssi->dma_maxburst = 8;
  1347. break;
  1348. case 8:
  1349. default:
  1350. /* Safely use old watermark configurations for older chips */
  1351. ssi->fifo_watermark = ssi->fifo_depth - 2;
  1352. ssi->dma_maxburst = ssi->fifo_depth - 2;
  1353. break;
  1354. }
  1355. dev_set_drvdata(dev, ssi);
  1356. if (ssi->soc->imx) {
  1357. ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
  1358. if (ret)
  1359. return ret;
  1360. }
  1361. if (fsl_ssi_is_ac97(ssi)) {
  1362. mutex_init(&ssi->ac97_reg_lock);
  1363. ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
  1364. if (ret) {
  1365. dev_err(dev, "failed to set AC'97 ops\n");
  1366. goto error_ac97_ops;
  1367. }
  1368. }
  1369. ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
  1370. &ssi->cpu_dai_drv, 1);
  1371. if (ret) {
  1372. dev_err(dev, "failed to register DAI: %d\n", ret);
  1373. goto error_asoc_register;
  1374. }
  1375. if (ssi->use_dma) {
  1376. ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
  1377. dev_name(dev), ssi);
  1378. if (ret < 0) {
  1379. dev_err(dev, "failed to claim irq %u\n", ssi->irq);
  1380. goto error_asoc_register;
  1381. }
  1382. }
  1383. fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
  1384. /* Initially configures SSI registers */
  1385. fsl_ssi_hw_init(ssi);
  1386. /* Register a platform device for older bindings or AC97 */
  1387. if (ssi->card_name[0]) {
  1388. struct device *parent = dev;
  1389. /*
  1390. * Do not set SSI dev as the parent of AC97 CODEC device since
  1391. * it does not have a DT node. Otherwise ASoC core will assume
  1392. * CODEC has the same DT node as the SSI, so it may bypass the
  1393. * dai_probe() of SSI and then cause NULL DMA data pointers.
  1394. */
  1395. if (fsl_ssi_is_ac97(ssi))
  1396. parent = NULL;
  1397. ssi->card_pdev = platform_device_register_data(parent,
  1398. ssi->card_name, ssi->card_idx, NULL, 0);
  1399. if (IS_ERR(ssi->card_pdev)) {
  1400. ret = PTR_ERR(ssi->card_pdev);
  1401. dev_err(dev, "failed to register %s: %d\n",
  1402. ssi->card_name, ret);
  1403. goto error_sound_card;
  1404. }
  1405. }
  1406. return 0;
  1407. error_sound_card:
  1408. fsl_ssi_debugfs_remove(&ssi->dbg_stats);
  1409. error_asoc_register:
  1410. if (fsl_ssi_is_ac97(ssi))
  1411. snd_soc_set_ac97_ops(NULL);
  1412. error_ac97_ops:
  1413. if (fsl_ssi_is_ac97(ssi))
  1414. mutex_destroy(&ssi->ac97_reg_lock);
  1415. if (ssi->soc->imx)
  1416. fsl_ssi_imx_clean(pdev, ssi);
  1417. return ret;
  1418. }
  1419. static int fsl_ssi_remove(struct platform_device *pdev)
  1420. {
  1421. struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
  1422. fsl_ssi_debugfs_remove(&ssi->dbg_stats);
  1423. if (ssi->card_pdev)
  1424. platform_device_unregister(ssi->card_pdev);
  1425. /* Clean up SSI registers */
  1426. fsl_ssi_hw_clean(ssi);
  1427. if (ssi->soc->imx)
  1428. fsl_ssi_imx_clean(pdev, ssi);
  1429. if (fsl_ssi_is_ac97(ssi)) {
  1430. snd_soc_set_ac97_ops(NULL);
  1431. mutex_destroy(&ssi->ac97_reg_lock);
  1432. }
  1433. return 0;
  1434. }
  1435. #ifdef CONFIG_PM_SLEEP
  1436. static int fsl_ssi_suspend(struct device *dev)
  1437. {
  1438. struct fsl_ssi *ssi = dev_get_drvdata(dev);
  1439. struct regmap *regs = ssi->regs;
  1440. regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
  1441. regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
  1442. regcache_cache_only(regs, true);
  1443. regcache_mark_dirty(regs);
  1444. return 0;
  1445. }
  1446. static int fsl_ssi_resume(struct device *dev)
  1447. {
  1448. struct fsl_ssi *ssi = dev_get_drvdata(dev);
  1449. struct regmap *regs = ssi->regs;
  1450. regcache_cache_only(regs, false);
  1451. regmap_update_bits(regs, REG_SSI_SFCSR,
  1452. SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
  1453. SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
  1454. ssi->regcache_sfcsr);
  1455. regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
  1456. return regcache_sync(regs);
  1457. }
  1458. #endif /* CONFIG_PM_SLEEP */
  1459. static const struct dev_pm_ops fsl_ssi_pm = {
  1460. SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
  1461. };
  1462. static struct platform_driver fsl_ssi_driver = {
  1463. .driver = {
  1464. .name = "fsl-ssi-dai",
  1465. .of_match_table = fsl_ssi_ids,
  1466. .pm = &fsl_ssi_pm,
  1467. },
  1468. .probe = fsl_ssi_probe,
  1469. .remove = fsl_ssi_remove,
  1470. };
  1471. module_platform_driver(fsl_ssi_driver);
  1472. MODULE_ALIAS("platform:fsl-ssi-dai");
  1473. MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
  1474. MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
  1475. MODULE_LICENSE("GPL v2");