fsl_spdif.h 7.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
  4. *
  5. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  6. *
  7. * Author: Nicolin Chen <b42378@freescale.com>
  8. *
  9. * Based on fsl_ssi.h
  10. * Author: Timur Tabi <timur@freescale.com>
  11. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  12. */
  13. #ifndef _FSL_SPDIF_DAI_H
  14. #define _FSL_SPDIF_DAI_H
  15. /* S/PDIF Register Map */
  16. #define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
  17. #define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
  18. #define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
  19. #define REG_SPDIF_SIE 0xc /* InterruptEn Register */
  20. #define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
  21. #define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
  22. #define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
  23. #define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
  24. #define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
  25. #define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
  26. #define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
  27. #define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
  28. #define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
  29. #define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
  30. #define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
  31. #define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
  32. #define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
  33. #define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
  34. /* SPDIF Configuration register */
  35. #define SCR_RXFIFO_CTL_OFFSET 23
  36. #define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
  37. #define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
  38. #define SCR_RXFIFO_OFF_OFFSET 22
  39. #define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
  40. #define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
  41. #define SCR_RXFIFO_RST_OFFSET 21
  42. #define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
  43. #define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
  44. #define SCR_RXFIFO_FSEL_OFFSET 19
  45. #define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
  46. #define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
  47. #define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
  48. #define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
  49. #define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
  50. #define SCR_RXFIFO_AUTOSYNC_OFFSET 18
  51. #define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
  52. #define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
  53. #define SCR_TXFIFO_AUTOSYNC_OFFSET 17
  54. #define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
  55. #define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
  56. #define SCR_TXFIFO_FSEL_OFFSET 15
  57. #define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
  58. #define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
  59. #define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
  60. #define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
  61. #define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
  62. #define SCR_LOW_POWER (1 << 13)
  63. #define SCR_SOFT_RESET (1 << 12)
  64. #define SCR_TXFIFO_CTRL_OFFSET 10
  65. #define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
  66. #define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
  67. #define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
  68. #define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
  69. #define SCR_DMA_RX_EN_OFFSET 9
  70. #define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
  71. #define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
  72. #define SCR_DMA_TX_EN_OFFSET 8
  73. #define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
  74. #define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
  75. #define SCR_VAL_OFFSET 5
  76. #define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
  77. #define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
  78. #define SCR_TXSEL_OFFSET 2
  79. #define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
  80. #define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
  81. #define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
  82. #define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
  83. #define SCR_USRC_SEL_OFFSET 0x0
  84. #define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
  85. #define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
  86. #define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
  87. #define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
  88. #define SCR_DMA_xX_EN(tx) (tx ? SCR_DMA_TX_EN : SCR_DMA_RX_EN)
  89. /* SPDIF CDText control */
  90. #define SRCD_CD_USER_OFFSET 1
  91. #define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
  92. /* SPDIF Phase Configuration register */
  93. #define SRPC_DPLL_LOCKED (1 << 6)
  94. #define SRPC_CLKSRC_SEL_OFFSET 7
  95. #define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
  96. #define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
  97. #define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
  98. #define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
  99. #define SRPC_GAINSEL_OFFSET 3
  100. #define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
  101. #define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
  102. #define SRPC_CLKSRC_MAX 16
  103. enum spdif_gainsel {
  104. GAINSEL_MULTI_24 = 0,
  105. GAINSEL_MULTI_16,
  106. GAINSEL_MULTI_12,
  107. GAINSEL_MULTI_8,
  108. GAINSEL_MULTI_6,
  109. GAINSEL_MULTI_4,
  110. GAINSEL_MULTI_3,
  111. };
  112. #define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
  113. #define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
  114. /* SPDIF interrupt mask define */
  115. #define INT_DPLL_LOCKED (1 << 20)
  116. #define INT_TXFIFO_UNOV (1 << 19)
  117. #define INT_TXFIFO_RESYNC (1 << 18)
  118. #define INT_CNEW (1 << 17)
  119. #define INT_VAL_NOGOOD (1 << 16)
  120. #define INT_SYM_ERR (1 << 15)
  121. #define INT_BIT_ERR (1 << 14)
  122. #define INT_URX_FUL (1 << 10)
  123. #define INT_URX_OV (1 << 9)
  124. #define INT_QRX_FUL (1 << 8)
  125. #define INT_QRX_OV (1 << 7)
  126. #define INT_UQ_SYNC (1 << 6)
  127. #define INT_UQ_ERR (1 << 5)
  128. #define INT_RXFIFO_UNOV (1 << 4)
  129. #define INT_RXFIFO_RESYNC (1 << 3)
  130. #define INT_LOSS_LOCK (1 << 2)
  131. #define INT_TX_EM (1 << 1)
  132. #define INT_RXFIFO_FUL (1 << 0)
  133. /* SPDIF Clock register */
  134. #define STC_SYSCLK_DF_OFFSET 11
  135. #define STC_SYSCLK_DF_MASK (0x1ff << STC_SYSCLK_DF_OFFSET)
  136. #define STC_SYSCLK_DF(x) ((((x) - 1) << STC_SYSCLK_DF_OFFSET) & STC_SYSCLK_DF_MASK)
  137. #define STC_TXCLK_SRC_OFFSET 8
  138. #define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
  139. #define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
  140. #define STC_TXCLK_ALL_EN_OFFSET 7
  141. #define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
  142. #define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
  143. #define STC_TXCLK_DF_OFFSET 0
  144. #define STC_TXCLK_DF_MASK (0x7f << STC_TXCLK_DF_OFFSET)
  145. #define STC_TXCLK_DF(x) ((((x) - 1) << STC_TXCLK_DF_OFFSET) & STC_TXCLK_DF_MASK)
  146. #define STC_TXCLK_SRC_MAX 8
  147. #define STC_TXCLK_SPDIF_ROOT 1
  148. /* SPDIF tx rate */
  149. enum spdif_txrate {
  150. SPDIF_TXRATE_32000 = 0,
  151. SPDIF_TXRATE_44100,
  152. SPDIF_TXRATE_48000,
  153. SPDIF_TXRATE_96000,
  154. SPDIF_TXRATE_192000,
  155. };
  156. #define SPDIF_TXRATE_MAX (SPDIF_TXRATE_192000 + 1)
  157. #define SPDIF_CSTATUS_BYTE 6
  158. #define SPDIF_UBITS_SIZE 96
  159. #define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
  160. #define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
  161. SNDRV_PCM_RATE_44100 | \
  162. SNDRV_PCM_RATE_48000 | \
  163. SNDRV_PCM_RATE_96000 | \
  164. SNDRV_PCM_RATE_192000)
  165. #define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
  166. SNDRV_PCM_RATE_32000 | \
  167. SNDRV_PCM_RATE_44100 | \
  168. SNDRV_PCM_RATE_48000 | \
  169. SNDRV_PCM_RATE_64000 | \
  170. SNDRV_PCM_RATE_96000)
  171. #define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
  172. SNDRV_PCM_FMTBIT_S20_3LE | \
  173. SNDRV_PCM_FMTBIT_S24_LE)
  174. #define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
  175. #endif /* _FSL_SPDIF_DAI_H */