fsl_sai.h 10.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2012-2013 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __FSL_SAI_H
  6. #define __FSL_SAI_H
  7. #include <sound/dmaengine_pcm.h>
  8. #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  9. SNDRV_PCM_FMTBIT_S20_3LE |\
  10. SNDRV_PCM_FMTBIT_S24_LE |\
  11. SNDRV_PCM_FMTBIT_S32_LE)
  12. /* SAI Register Map Register */
  13. #define FSL_SAI_VERID 0x00 /* SAI Version ID Register */
  14. #define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */
  15. #define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
  16. #define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
  17. #define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
  18. #define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
  19. #define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
  20. #define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
  21. #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
  22. #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
  23. #define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
  24. #define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
  25. #define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
  26. #define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
  27. #define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
  28. #define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
  29. #define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
  30. #define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
  31. #define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
  32. #define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
  33. #define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
  34. #define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
  35. #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
  36. #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
  37. #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
  38. #define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */
  39. #define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */
  40. #define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
  41. #define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */
  42. #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
  43. #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
  44. #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
  45. #define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
  46. #define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
  47. #define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
  48. #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
  49. #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
  50. #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
  51. #define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
  52. #define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
  53. #define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
  54. #define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
  55. #define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
  56. #define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
  57. #define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
  58. #define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
  59. #define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
  60. #define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
  61. #define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
  62. #define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
  63. #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
  64. #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
  65. #define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */
  66. #define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */
  67. #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
  68. #define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */
  69. #define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */
  70. #define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */
  71. #define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
  72. #define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
  73. #define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
  74. #define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
  75. #define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
  76. #define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
  77. #define FSL_SAI_xDR(tx, ofs) (tx ? FSL_SAI_TDR(ofs) : FSL_SAI_RDR(ofs))
  78. #define FSL_SAI_xFR(tx, ofs) (tx ? FSL_SAI_TFR(ofs) : FSL_SAI_RFR(ofs))
  79. #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
  80. /* SAI Transmit/Receive Control Register */
  81. #define FSL_SAI_CSR_TERE BIT(31)
  82. #define FSL_SAI_CSR_SE BIT(30)
  83. #define FSL_SAI_CSR_FR BIT(25)
  84. #define FSL_SAI_CSR_SR BIT(24)
  85. #define FSL_SAI_CSR_xF_SHIFT 16
  86. #define FSL_SAI_CSR_xF_W_SHIFT 18
  87. #define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
  88. #define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
  89. #define FSL_SAI_CSR_WSF BIT(20)
  90. #define FSL_SAI_CSR_SEF BIT(19)
  91. #define FSL_SAI_CSR_FEF BIT(18)
  92. #define FSL_SAI_CSR_FWF BIT(17)
  93. #define FSL_SAI_CSR_FRF BIT(16)
  94. #define FSL_SAI_CSR_xIE_SHIFT 8
  95. #define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
  96. #define FSL_SAI_CSR_WSIE BIT(12)
  97. #define FSL_SAI_CSR_SEIE BIT(11)
  98. #define FSL_SAI_CSR_FEIE BIT(10)
  99. #define FSL_SAI_CSR_FWIE BIT(9)
  100. #define FSL_SAI_CSR_FRIE BIT(8)
  101. #define FSL_SAI_CSR_FRDE BIT(0)
  102. /* SAI Transmit and Receive Configuration 1 Register */
  103. #define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1)
  104. /* SAI Transmit and Receive Configuration 2 Register */
  105. #define FSL_SAI_CR2_SYNC BIT(30)
  106. #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
  107. #define FSL_SAI_CR2_MSEL_BUS 0
  108. #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
  109. #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
  110. #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
  111. #define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
  112. #define FSL_SAI_CR2_BCP BIT(25)
  113. #define FSL_SAI_CR2_BCD_MSTR BIT(24)
  114. #define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */
  115. #define FSL_SAI_CR2_DIV_MASK 0xff
  116. /* SAI Transmit and Receive Configuration 3 Register */
  117. #define FSL_SAI_CR3_TRCE(x) ((x) << 16)
  118. #define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
  119. #define FSL_SAI_CR3_WDFL(x) (x)
  120. #define FSL_SAI_CR3_WDFL_MASK 0x1f
  121. /* SAI Transmit and Receive Configuration 4 Register */
  122. #define FSL_SAI_CR4_FCONT BIT(28)
  123. #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
  124. #define FSL_SAI_CR4_FCOMB_SOFT BIT(27)
  125. #define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26)
  126. #define FSL_SAI_CR4_FPACK_8 (0x2 << 24)
  127. #define FSL_SAI_CR4_FPACK_16 (0x3 << 24)
  128. #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
  129. #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
  130. #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
  131. #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
  132. #define FSL_SAI_CR4_CHMOD BIT(5)
  133. #define FSL_SAI_CR4_CHMOD_MASK BIT(5)
  134. #define FSL_SAI_CR4_MF BIT(4)
  135. #define FSL_SAI_CR4_FSE BIT(3)
  136. #define FSL_SAI_CR4_FSP BIT(1)
  137. #define FSL_SAI_CR4_FSD_MSTR BIT(0)
  138. /* SAI Transmit and Receive Configuration 5 Register */
  139. #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
  140. #define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
  141. #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
  142. #define FSL_SAI_CR5_W0W_MASK (0x1f << 16)
  143. #define FSL_SAI_CR5_FBT(x) ((x) << 8)
  144. #define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
  145. /* SAI MCLK Control Register */
  146. #define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
  147. #define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
  148. #define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
  149. #define FSL_SAI_MCTL_MSEL_BUS 0
  150. #define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
  151. #define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
  152. #define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
  153. #define FSL_SAI_MCTL_DIV_EN BIT(23)
  154. #define FSL_SAI_MCTL_DIV_MASK 0xFF
  155. /* SAI VERID Register */
  156. #define FSL_SAI_VERID_MAJOR_SHIFT 24
  157. #define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24)
  158. #define FSL_SAI_VERID_MINOR_SHIFT 16
  159. #define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16)
  160. #define FSL_SAI_VERID_FEATURE_SHIFT 0
  161. #define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0)
  162. #define FSL_SAI_VERID_EFIFO_EN BIT(0)
  163. #define FSL_SAI_VERID_TSTMP_EN BIT(1)
  164. /* SAI PARAM Register */
  165. #define FSL_SAI_PARAM_SPF_SHIFT 16
  166. #define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16)
  167. #define FSL_SAI_PARAM_WPF_SHIFT 8
  168. #define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8)
  169. #define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0)
  170. /* SAI MCLK Divide Register */
  171. #define FSL_SAI_MDIV_MASK 0xFFFFF
  172. /* SAI timestamp and bitcounter */
  173. #define FSL_SAI_xTCTL_TSEN BIT(0)
  174. #define FSL_SAI_xTCTL_TSINC BIT(1)
  175. #define FSL_SAI_xTCTL_RTSC BIT(8)
  176. #define FSL_SAI_xTCTL_RBC BIT(9)
  177. /* SAI type */
  178. #define FSL_SAI_DMA BIT(0)
  179. #define FSL_SAI_USE_AC97 BIT(1)
  180. #define FSL_SAI_NET BIT(2)
  181. #define FSL_SAI_TRA_SYN BIT(3)
  182. #define FSL_SAI_REC_SYN BIT(4)
  183. #define FSL_SAI_USE_I2S_SLAVE BIT(5)
  184. #define FSL_FMT_TRANSMITTER 0
  185. #define FSL_FMT_RECEIVER 1
  186. /* SAI clock sources */
  187. #define FSL_SAI_CLK_BUS 0
  188. #define FSL_SAI_CLK_MAST1 1
  189. #define FSL_SAI_CLK_MAST2 2
  190. #define FSL_SAI_CLK_MAST3 3
  191. #define FSL_SAI_MCLK_MAX 4
  192. /* SAI data transfer numbers per DMA request */
  193. #define FSL_SAI_MAXBURST_TX 6
  194. #define FSL_SAI_MAXBURST_RX 6
  195. struct fsl_sai_soc_data {
  196. bool use_imx_pcm;
  197. bool use_edma;
  198. unsigned int fifo_depth;
  199. unsigned int reg_offset;
  200. };
  201. /**
  202. * struct fsl_sai_verid - version id data
  203. * @major: major version number
  204. * @minor: minor version number
  205. * @feature: feature specification number
  206. * 0000000000000000b - Standard feature set
  207. * 0000000000000000b - Standard feature set
  208. */
  209. struct fsl_sai_verid {
  210. u32 major;
  211. u32 minor;
  212. u32 feature;
  213. };
  214. /**
  215. * struct fsl_sai_param - parameter data
  216. * @slot_num: The maximum number of slots per frame
  217. * @fifo_depth: The number of words in each FIFO (depth)
  218. * @dataline: The number of datalines implemented
  219. */
  220. struct fsl_sai_param {
  221. u32 slot_num;
  222. u32 fifo_depth;
  223. u32 dataline;
  224. };
  225. struct fsl_sai {
  226. struct platform_device *pdev;
  227. struct regmap *regmap;
  228. struct clk *bus_clk;
  229. struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
  230. bool is_slave_mode;
  231. bool is_lsb_first;
  232. bool is_dsp_mode;
  233. bool synchronous[2];
  234. unsigned int mclk_id[2];
  235. unsigned int mclk_streams;
  236. unsigned int slots;
  237. unsigned int slot_width;
  238. unsigned int bclk_ratio;
  239. const struct fsl_sai_soc_data *soc_data;
  240. struct snd_soc_dai_driver cpu_dai_drv;
  241. struct snd_dmaengine_dai_dma_data dma_params_rx;
  242. struct snd_dmaengine_dai_dma_data dma_params_tx;
  243. struct fsl_sai_verid verid;
  244. struct fsl_sai_param param;
  245. };
  246. #define TX 1
  247. #define RX 0
  248. #endif /* __FSL_SAI_H */