fsl_sai.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
  4. //
  5. // Copyright 2012-2015 Freescale Semiconductor, Inc.
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/dmaengine.h>
  9. #include <linux/module.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_device.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/regmap.h>
  14. #include <linux/slab.h>
  15. #include <linux/time.h>
  16. #include <sound/core.h>
  17. #include <sound/dmaengine_pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <linux/mfd/syscon.h>
  20. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  21. #include "fsl_sai.h"
  22. #include "imx-pcm.h"
  23. #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
  24. FSL_SAI_CSR_FEIE)
  25. static const unsigned int fsl_sai_rates[] = {
  26. 8000, 11025, 12000, 16000, 22050,
  27. 24000, 32000, 44100, 48000, 64000,
  28. 88200, 96000, 176400, 192000
  29. };
  30. static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
  31. .count = ARRAY_SIZE(fsl_sai_rates),
  32. .list = fsl_sai_rates,
  33. };
  34. /**
  35. * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
  36. *
  37. * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
  38. * or Receiver's for both streams. This function is used to check if clocks of
  39. * the stream's are synced by the opposite stream.
  40. *
  41. * @sai: SAI context
  42. * @dir: stream direction
  43. */
  44. static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
  45. {
  46. int adir = (dir == TX) ? RX : TX;
  47. /* current dir in async mode while opposite dir in sync mode */
  48. return !sai->synchronous[dir] && sai->synchronous[adir];
  49. }
  50. static irqreturn_t fsl_sai_isr(int irq, void *devid)
  51. {
  52. struct fsl_sai *sai = (struct fsl_sai *)devid;
  53. unsigned int ofs = sai->soc_data->reg_offset;
  54. struct device *dev = &sai->pdev->dev;
  55. u32 flags, xcsr, mask;
  56. bool irq_none = true;
  57. /*
  58. * Both IRQ status bits and IRQ mask bits are in the xCSR but
  59. * different shifts. And we here create a mask only for those
  60. * IRQs that we activated.
  61. */
  62. mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
  63. /* Tx IRQ */
  64. regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
  65. flags = xcsr & mask;
  66. if (flags)
  67. irq_none = false;
  68. else
  69. goto irq_rx;
  70. if (flags & FSL_SAI_CSR_WSF)
  71. dev_dbg(dev, "isr: Start of Tx word detected\n");
  72. if (flags & FSL_SAI_CSR_SEF)
  73. dev_dbg(dev, "isr: Tx Frame sync error detected\n");
  74. if (flags & FSL_SAI_CSR_FEF) {
  75. dev_dbg(dev, "isr: Transmit underrun detected\n");
  76. /* FIFO reset for safety */
  77. xcsr |= FSL_SAI_CSR_FR;
  78. }
  79. if (flags & FSL_SAI_CSR_FWF)
  80. dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
  81. if (flags & FSL_SAI_CSR_FRF)
  82. dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
  83. flags &= FSL_SAI_CSR_xF_W_MASK;
  84. xcsr &= ~FSL_SAI_CSR_xF_MASK;
  85. if (flags)
  86. regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
  87. irq_rx:
  88. /* Rx IRQ */
  89. regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
  90. flags = xcsr & mask;
  91. if (flags)
  92. irq_none = false;
  93. else
  94. goto out;
  95. if (flags & FSL_SAI_CSR_WSF)
  96. dev_dbg(dev, "isr: Start of Rx word detected\n");
  97. if (flags & FSL_SAI_CSR_SEF)
  98. dev_dbg(dev, "isr: Rx Frame sync error detected\n");
  99. if (flags & FSL_SAI_CSR_FEF) {
  100. dev_dbg(dev, "isr: Receive overflow detected\n");
  101. /* FIFO reset for safety */
  102. xcsr |= FSL_SAI_CSR_FR;
  103. }
  104. if (flags & FSL_SAI_CSR_FWF)
  105. dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
  106. if (flags & FSL_SAI_CSR_FRF)
  107. dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
  108. flags &= FSL_SAI_CSR_xF_W_MASK;
  109. xcsr &= ~FSL_SAI_CSR_xF_MASK;
  110. if (flags)
  111. regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
  112. out:
  113. if (irq_none)
  114. return IRQ_NONE;
  115. else
  116. return IRQ_HANDLED;
  117. }
  118. static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
  119. u32 rx_mask, int slots, int slot_width)
  120. {
  121. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  122. sai->slots = slots;
  123. sai->slot_width = slot_width;
  124. return 0;
  125. }
  126. static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
  127. unsigned int ratio)
  128. {
  129. struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
  130. sai->bclk_ratio = ratio;
  131. return 0;
  132. }
  133. static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
  134. int clk_id, unsigned int freq, int fsl_dir)
  135. {
  136. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  137. unsigned int ofs = sai->soc_data->reg_offset;
  138. bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
  139. u32 val_cr2 = 0;
  140. switch (clk_id) {
  141. case FSL_SAI_CLK_BUS:
  142. val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
  143. break;
  144. case FSL_SAI_CLK_MAST1:
  145. val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
  146. break;
  147. case FSL_SAI_CLK_MAST2:
  148. val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
  149. break;
  150. case FSL_SAI_CLK_MAST3:
  151. val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
  152. break;
  153. default:
  154. return -EINVAL;
  155. }
  156. regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
  157. FSL_SAI_CR2_MSEL_MASK, val_cr2);
  158. return 0;
  159. }
  160. static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  161. int clk_id, unsigned int freq, int dir)
  162. {
  163. int ret;
  164. if (dir == SND_SOC_CLOCK_IN)
  165. return 0;
  166. ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
  167. FSL_FMT_TRANSMITTER);
  168. if (ret) {
  169. dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
  170. return ret;
  171. }
  172. ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
  173. FSL_FMT_RECEIVER);
  174. if (ret)
  175. dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
  176. return ret;
  177. }
  178. static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
  179. unsigned int fmt, int fsl_dir)
  180. {
  181. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  182. unsigned int ofs = sai->soc_data->reg_offset;
  183. bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
  184. u32 val_cr2 = 0, val_cr4 = 0;
  185. if (!sai->is_lsb_first)
  186. val_cr4 |= FSL_SAI_CR4_MF;
  187. /* DAI mode */
  188. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  189. case SND_SOC_DAIFMT_I2S:
  190. /*
  191. * Frame low, 1clk before data, one word length for frame sync,
  192. * frame sync starts one serial clock cycle earlier,
  193. * that is, together with the last bit of the previous
  194. * data word.
  195. */
  196. val_cr2 |= FSL_SAI_CR2_BCP;
  197. val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
  198. break;
  199. case SND_SOC_DAIFMT_LEFT_J:
  200. /*
  201. * Frame high, one word length for frame sync,
  202. * frame sync asserts with the first bit of the frame.
  203. */
  204. val_cr2 |= FSL_SAI_CR2_BCP;
  205. break;
  206. case SND_SOC_DAIFMT_DSP_A:
  207. /*
  208. * Frame high, 1clk before data, one bit for frame sync,
  209. * frame sync starts one serial clock cycle earlier,
  210. * that is, together with the last bit of the previous
  211. * data word.
  212. */
  213. val_cr2 |= FSL_SAI_CR2_BCP;
  214. val_cr4 |= FSL_SAI_CR4_FSE;
  215. sai->is_dsp_mode = true;
  216. break;
  217. case SND_SOC_DAIFMT_DSP_B:
  218. /*
  219. * Frame high, one bit for frame sync,
  220. * frame sync asserts with the first bit of the frame.
  221. */
  222. val_cr2 |= FSL_SAI_CR2_BCP;
  223. sai->is_dsp_mode = true;
  224. break;
  225. case SND_SOC_DAIFMT_RIGHT_J:
  226. /* To be done */
  227. default:
  228. return -EINVAL;
  229. }
  230. /* DAI clock inversion */
  231. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  232. case SND_SOC_DAIFMT_IB_IF:
  233. /* Invert both clocks */
  234. val_cr2 ^= FSL_SAI_CR2_BCP;
  235. val_cr4 ^= FSL_SAI_CR4_FSP;
  236. break;
  237. case SND_SOC_DAIFMT_IB_NF:
  238. /* Invert bit clock */
  239. val_cr2 ^= FSL_SAI_CR2_BCP;
  240. break;
  241. case SND_SOC_DAIFMT_NB_IF:
  242. /* Invert frame clock */
  243. val_cr4 ^= FSL_SAI_CR4_FSP;
  244. break;
  245. case SND_SOC_DAIFMT_NB_NF:
  246. /* Nothing to do for both normal cases */
  247. break;
  248. default:
  249. return -EINVAL;
  250. }
  251. /* DAI clock master masks */
  252. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  253. case SND_SOC_DAIFMT_CBS_CFS:
  254. val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
  255. val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
  256. sai->is_slave_mode = false;
  257. break;
  258. case SND_SOC_DAIFMT_CBM_CFM:
  259. sai->is_slave_mode = true;
  260. break;
  261. case SND_SOC_DAIFMT_CBS_CFM:
  262. val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
  263. sai->is_slave_mode = false;
  264. break;
  265. case SND_SOC_DAIFMT_CBM_CFS:
  266. val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
  267. sai->is_slave_mode = true;
  268. break;
  269. default:
  270. return -EINVAL;
  271. }
  272. regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
  273. FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
  274. regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
  275. FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
  276. FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
  277. return 0;
  278. }
  279. static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  280. {
  281. int ret;
  282. ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
  283. if (ret) {
  284. dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
  285. return ret;
  286. }
  287. ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
  288. if (ret)
  289. dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
  290. return ret;
  291. }
  292. static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
  293. {
  294. struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
  295. unsigned int ofs = sai->soc_data->reg_offset;
  296. unsigned long clk_rate;
  297. u32 savediv = 0, ratio, savesub = freq;
  298. int adir = tx ? RX : TX;
  299. int dir = tx ? TX : RX;
  300. u32 id;
  301. int ret = 0;
  302. /* Don't apply to slave mode */
  303. if (sai->is_slave_mode)
  304. return 0;
  305. for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
  306. clk_rate = clk_get_rate(sai->mclk_clk[id]);
  307. if (!clk_rate)
  308. continue;
  309. ratio = clk_rate / freq;
  310. ret = clk_rate - ratio * freq;
  311. /*
  312. * Drop the source that can not be
  313. * divided into the required rate.
  314. */
  315. if (ret != 0 && clk_rate / ret < 1000)
  316. continue;
  317. dev_dbg(dai->dev,
  318. "ratio %d for freq %dHz based on clock %ldHz\n",
  319. ratio, freq, clk_rate);
  320. if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
  321. ratio /= 2;
  322. else
  323. continue;
  324. if (ret < savesub) {
  325. savediv = ratio;
  326. sai->mclk_id[tx] = id;
  327. savesub = ret;
  328. }
  329. if (ret == 0)
  330. break;
  331. }
  332. if (savediv == 0) {
  333. dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
  334. tx ? 'T' : 'R', freq);
  335. return -EINVAL;
  336. }
  337. /*
  338. * 1) For Asynchronous mode, we must set RCR2 register for capture, and
  339. * set TCR2 register for playback.
  340. * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
  341. * and capture.
  342. * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
  343. * and capture.
  344. * 4) For Tx and Rx are both Synchronous with another SAI, we just
  345. * ignore it.
  346. */
  347. if (fsl_sai_dir_is_synced(sai, adir)) {
  348. regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
  349. FSL_SAI_CR2_MSEL_MASK,
  350. FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
  351. regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs),
  352. FSL_SAI_CR2_DIV_MASK, savediv - 1);
  353. } else if (!sai->synchronous[dir]) {
  354. regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
  355. FSL_SAI_CR2_MSEL_MASK,
  356. FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
  357. regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
  358. FSL_SAI_CR2_DIV_MASK, savediv - 1);
  359. }
  360. dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
  361. sai->mclk_id[tx], savediv, savesub);
  362. return 0;
  363. }
  364. static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
  365. struct snd_pcm_hw_params *params,
  366. struct snd_soc_dai *cpu_dai)
  367. {
  368. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  369. unsigned int ofs = sai->soc_data->reg_offset;
  370. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  371. unsigned int channels = params_channels(params);
  372. u32 word_width = params_width(params);
  373. u32 val_cr4 = 0, val_cr5 = 0;
  374. u32 slots = (channels == 1) ? 2 : channels;
  375. u32 slot_width = word_width;
  376. int adir = tx ? RX : TX;
  377. u32 pins;
  378. int ret;
  379. if (sai->slots)
  380. slots = sai->slots;
  381. if (sai->slot_width)
  382. slot_width = sai->slot_width;
  383. pins = DIV_ROUND_UP(channels, slots);
  384. if (!sai->is_slave_mode) {
  385. if (sai->bclk_ratio)
  386. ret = fsl_sai_set_bclk(cpu_dai, tx,
  387. sai->bclk_ratio *
  388. params_rate(params));
  389. else
  390. ret = fsl_sai_set_bclk(cpu_dai, tx,
  391. slots * slot_width *
  392. params_rate(params));
  393. if (ret)
  394. return ret;
  395. /* Do not enable the clock if it is already enabled */
  396. if (!(sai->mclk_streams & BIT(substream->stream))) {
  397. ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
  398. if (ret)
  399. return ret;
  400. sai->mclk_streams |= BIT(substream->stream);
  401. }
  402. }
  403. if (!sai->is_dsp_mode)
  404. val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
  405. val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
  406. val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
  407. if (sai->is_lsb_first)
  408. val_cr5 |= FSL_SAI_CR5_FBT(0);
  409. else
  410. val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
  411. val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
  412. /* Set to output mode to avoid tri-stated data pins */
  413. if (tx)
  414. val_cr4 |= FSL_SAI_CR4_CHMOD;
  415. /*
  416. * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
  417. * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
  418. * RCR5(TCR5) for playback(capture), or there will be sync error.
  419. */
  420. if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
  421. regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
  422. FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
  423. FSL_SAI_CR4_CHMOD_MASK,
  424. val_cr4);
  425. regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
  426. FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  427. FSL_SAI_CR5_FBT_MASK, val_cr5);
  428. }
  429. regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
  430. FSL_SAI_CR3_TRCE_MASK,
  431. FSL_SAI_CR3_TRCE((1 << pins) - 1));
  432. regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
  433. FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
  434. FSL_SAI_CR4_CHMOD_MASK,
  435. val_cr4);
  436. regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
  437. FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  438. FSL_SAI_CR5_FBT_MASK, val_cr5);
  439. regmap_write(sai->regmap, FSL_SAI_xMR(tx),
  440. ~0UL - ((1 << min(channels, slots)) - 1));
  441. return 0;
  442. }
  443. static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
  444. struct snd_soc_dai *cpu_dai)
  445. {
  446. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  447. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  448. unsigned int ofs = sai->soc_data->reg_offset;
  449. regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
  450. FSL_SAI_CR3_TRCE_MASK, 0);
  451. if (!sai->is_slave_mode &&
  452. sai->mclk_streams & BIT(substream->stream)) {
  453. clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
  454. sai->mclk_streams &= ~BIT(substream->stream);
  455. }
  456. return 0;
  457. }
  458. static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
  459. {
  460. unsigned int ofs = sai->soc_data->reg_offset;
  461. bool tx = dir == TX;
  462. u32 xcsr, count = 100;
  463. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  464. FSL_SAI_CSR_TERE, 0);
  465. /* TERE will remain set till the end of current frame */
  466. do {
  467. udelay(10);
  468. regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
  469. } while (--count && xcsr & FSL_SAI_CSR_TERE);
  470. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  471. FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
  472. /*
  473. * For sai master mode, after several open/close sai,
  474. * there will be no frame clock, and can't recover
  475. * anymore. Add software reset to fix this issue.
  476. * This is a hardware bug, and will be fix in the
  477. * next sai version.
  478. */
  479. if (!sai->is_slave_mode) {
  480. /* Software Reset */
  481. regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
  482. /* Clear SR bit to finish the reset */
  483. regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
  484. }
  485. }
  486. static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
  487. struct snd_soc_dai *cpu_dai)
  488. {
  489. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  490. unsigned int ofs = sai->soc_data->reg_offset;
  491. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  492. int adir = tx ? RX : TX;
  493. int dir = tx ? TX : RX;
  494. u32 xcsr;
  495. /*
  496. * Asynchronous mode: Clear SYNC for both Tx and Rx.
  497. * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
  498. * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
  499. */
  500. regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
  501. sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
  502. regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
  503. sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
  504. /*
  505. * It is recommended that the transmitter is the last enabled
  506. * and the first disabled.
  507. */
  508. switch (cmd) {
  509. case SNDRV_PCM_TRIGGER_START:
  510. case SNDRV_PCM_TRIGGER_RESUME:
  511. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  512. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  513. FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
  514. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  515. FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
  516. /*
  517. * Enable the opposite direction for synchronous mode
  518. * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
  519. * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
  520. *
  521. * RM recommends to enable RE after TE for case 1 and to enable
  522. * TE after RE for case 2, but we here may not always guarantee
  523. * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
  524. * TE after RE, which is against what RM recommends but should
  525. * be safe to do, judging by years of testing results.
  526. */
  527. if (fsl_sai_dir_is_synced(sai, adir))
  528. regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
  529. FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
  530. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  531. FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
  532. break;
  533. case SNDRV_PCM_TRIGGER_STOP:
  534. case SNDRV_PCM_TRIGGER_SUSPEND:
  535. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  536. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  537. FSL_SAI_CSR_FRDE, 0);
  538. regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
  539. FSL_SAI_CSR_xIE_MASK, 0);
  540. /* Check if the opposite FRDE is also disabled */
  541. regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
  542. /*
  543. * If opposite stream provides clocks for synchronous mode and
  544. * it is inactive, disable it before disabling the current one
  545. */
  546. if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
  547. fsl_sai_config_disable(sai, adir);
  548. /*
  549. * Disable current stream if either of:
  550. * 1. current stream doesn't provide clocks for synchronous mode
  551. * 2. current stream provides clocks for synchronous mode but no
  552. * more stream is active.
  553. */
  554. if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
  555. fsl_sai_config_disable(sai, dir);
  556. break;
  557. default:
  558. return -EINVAL;
  559. }
  560. return 0;
  561. }
  562. static int fsl_sai_startup(struct snd_pcm_substream *substream,
  563. struct snd_soc_dai *cpu_dai)
  564. {
  565. struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  566. bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  567. int ret;
  568. /*
  569. * EDMA controller needs period size to be a multiple of
  570. * tx/rx maxburst
  571. */
  572. if (sai->soc_data->use_edma)
  573. snd_pcm_hw_constraint_step(substream->runtime, 0,
  574. SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
  575. tx ? sai->dma_params_tx.maxburst :
  576. sai->dma_params_rx.maxburst);
  577. ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
  578. SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
  579. return ret;
  580. }
  581. static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
  582. .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
  583. .set_sysclk = fsl_sai_set_dai_sysclk,
  584. .set_fmt = fsl_sai_set_dai_fmt,
  585. .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
  586. .hw_params = fsl_sai_hw_params,
  587. .hw_free = fsl_sai_hw_free,
  588. .trigger = fsl_sai_trigger,
  589. .startup = fsl_sai_startup,
  590. };
  591. static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
  592. {
  593. struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
  594. unsigned int ofs = sai->soc_data->reg_offset;
  595. /* Software Reset for both Tx and Rx */
  596. regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
  597. regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
  598. /* Clear SR bit to finish the reset */
  599. regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
  600. regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
  601. regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
  602. FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
  603. sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
  604. regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
  605. FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
  606. FSL_SAI_MAXBURST_RX - 1);
  607. snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
  608. &sai->dma_params_rx);
  609. snd_soc_dai_set_drvdata(cpu_dai, sai);
  610. return 0;
  611. }
  612. static struct snd_soc_dai_driver fsl_sai_dai_template = {
  613. .probe = fsl_sai_dai_probe,
  614. .playback = {
  615. .stream_name = "CPU-Playback",
  616. .channels_min = 1,
  617. .channels_max = 32,
  618. .rate_min = 8000,
  619. .rate_max = 192000,
  620. .rates = SNDRV_PCM_RATE_KNOT,
  621. .formats = FSL_SAI_FORMATS,
  622. },
  623. .capture = {
  624. .stream_name = "CPU-Capture",
  625. .channels_min = 1,
  626. .channels_max = 32,
  627. .rate_min = 8000,
  628. .rate_max = 192000,
  629. .rates = SNDRV_PCM_RATE_KNOT,
  630. .formats = FSL_SAI_FORMATS,
  631. },
  632. .ops = &fsl_sai_pcm_dai_ops,
  633. };
  634. static const struct snd_soc_component_driver fsl_component = {
  635. .name = "fsl-sai",
  636. };
  637. static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
  638. {FSL_SAI_TCR1(0), 0},
  639. {FSL_SAI_TCR2(0), 0},
  640. {FSL_SAI_TCR3(0), 0},
  641. {FSL_SAI_TCR4(0), 0},
  642. {FSL_SAI_TCR5(0), 0},
  643. {FSL_SAI_TDR0, 0},
  644. {FSL_SAI_TDR1, 0},
  645. {FSL_SAI_TDR2, 0},
  646. {FSL_SAI_TDR3, 0},
  647. {FSL_SAI_TDR4, 0},
  648. {FSL_SAI_TDR5, 0},
  649. {FSL_SAI_TDR6, 0},
  650. {FSL_SAI_TDR7, 0},
  651. {FSL_SAI_TMR, 0},
  652. {FSL_SAI_RCR1(0), 0},
  653. {FSL_SAI_RCR2(0), 0},
  654. {FSL_SAI_RCR3(0), 0},
  655. {FSL_SAI_RCR4(0), 0},
  656. {FSL_SAI_RCR5(0), 0},
  657. {FSL_SAI_RMR, 0},
  658. };
  659. static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
  660. {FSL_SAI_TCR1(8), 0},
  661. {FSL_SAI_TCR2(8), 0},
  662. {FSL_SAI_TCR3(8), 0},
  663. {FSL_SAI_TCR4(8), 0},
  664. {FSL_SAI_TCR5(8), 0},
  665. {FSL_SAI_TDR0, 0},
  666. {FSL_SAI_TDR1, 0},
  667. {FSL_SAI_TDR2, 0},
  668. {FSL_SAI_TDR3, 0},
  669. {FSL_SAI_TDR4, 0},
  670. {FSL_SAI_TDR5, 0},
  671. {FSL_SAI_TDR6, 0},
  672. {FSL_SAI_TDR7, 0},
  673. {FSL_SAI_TMR, 0},
  674. {FSL_SAI_RCR1(8), 0},
  675. {FSL_SAI_RCR2(8), 0},
  676. {FSL_SAI_RCR3(8), 0},
  677. {FSL_SAI_RCR4(8), 0},
  678. {FSL_SAI_RCR5(8), 0},
  679. {FSL_SAI_RMR, 0},
  680. {FSL_SAI_MCTL, 0},
  681. {FSL_SAI_MDIV, 0},
  682. };
  683. static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
  684. {
  685. struct fsl_sai *sai = dev_get_drvdata(dev);
  686. unsigned int ofs = sai->soc_data->reg_offset;
  687. if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
  688. return true;
  689. if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
  690. return true;
  691. switch (reg) {
  692. case FSL_SAI_TFR0:
  693. case FSL_SAI_TFR1:
  694. case FSL_SAI_TFR2:
  695. case FSL_SAI_TFR3:
  696. case FSL_SAI_TFR4:
  697. case FSL_SAI_TFR5:
  698. case FSL_SAI_TFR6:
  699. case FSL_SAI_TFR7:
  700. case FSL_SAI_TMR:
  701. case FSL_SAI_RDR0:
  702. case FSL_SAI_RDR1:
  703. case FSL_SAI_RDR2:
  704. case FSL_SAI_RDR3:
  705. case FSL_SAI_RDR4:
  706. case FSL_SAI_RDR5:
  707. case FSL_SAI_RDR6:
  708. case FSL_SAI_RDR7:
  709. case FSL_SAI_RFR0:
  710. case FSL_SAI_RFR1:
  711. case FSL_SAI_RFR2:
  712. case FSL_SAI_RFR3:
  713. case FSL_SAI_RFR4:
  714. case FSL_SAI_RFR5:
  715. case FSL_SAI_RFR6:
  716. case FSL_SAI_RFR7:
  717. case FSL_SAI_RMR:
  718. case FSL_SAI_MCTL:
  719. case FSL_SAI_MDIV:
  720. case FSL_SAI_VERID:
  721. case FSL_SAI_PARAM:
  722. case FSL_SAI_TTCTN:
  723. case FSL_SAI_RTCTN:
  724. case FSL_SAI_TTCTL:
  725. case FSL_SAI_TBCTN:
  726. case FSL_SAI_TTCAP:
  727. case FSL_SAI_RTCTL:
  728. case FSL_SAI_RBCTN:
  729. case FSL_SAI_RTCAP:
  730. return true;
  731. default:
  732. return false;
  733. }
  734. }
  735. static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
  736. {
  737. struct fsl_sai *sai = dev_get_drvdata(dev);
  738. unsigned int ofs = sai->soc_data->reg_offset;
  739. if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
  740. return true;
  741. /* Set VERID and PARAM be volatile for reading value in probe */
  742. if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
  743. return true;
  744. switch (reg) {
  745. case FSL_SAI_TFR0:
  746. case FSL_SAI_TFR1:
  747. case FSL_SAI_TFR2:
  748. case FSL_SAI_TFR3:
  749. case FSL_SAI_TFR4:
  750. case FSL_SAI_TFR5:
  751. case FSL_SAI_TFR6:
  752. case FSL_SAI_TFR7:
  753. case FSL_SAI_RFR0:
  754. case FSL_SAI_RFR1:
  755. case FSL_SAI_RFR2:
  756. case FSL_SAI_RFR3:
  757. case FSL_SAI_RFR4:
  758. case FSL_SAI_RFR5:
  759. case FSL_SAI_RFR6:
  760. case FSL_SAI_RFR7:
  761. case FSL_SAI_RDR0:
  762. case FSL_SAI_RDR1:
  763. case FSL_SAI_RDR2:
  764. case FSL_SAI_RDR3:
  765. case FSL_SAI_RDR4:
  766. case FSL_SAI_RDR5:
  767. case FSL_SAI_RDR6:
  768. case FSL_SAI_RDR7:
  769. return true;
  770. default:
  771. return false;
  772. }
  773. }
  774. static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
  775. {
  776. struct fsl_sai *sai = dev_get_drvdata(dev);
  777. unsigned int ofs = sai->soc_data->reg_offset;
  778. if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
  779. return true;
  780. if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
  781. return true;
  782. switch (reg) {
  783. case FSL_SAI_TDR0:
  784. case FSL_SAI_TDR1:
  785. case FSL_SAI_TDR2:
  786. case FSL_SAI_TDR3:
  787. case FSL_SAI_TDR4:
  788. case FSL_SAI_TDR5:
  789. case FSL_SAI_TDR6:
  790. case FSL_SAI_TDR7:
  791. case FSL_SAI_TMR:
  792. case FSL_SAI_RMR:
  793. case FSL_SAI_MCTL:
  794. case FSL_SAI_MDIV:
  795. case FSL_SAI_TTCTL:
  796. case FSL_SAI_RTCTL:
  797. return true;
  798. default:
  799. return false;
  800. }
  801. }
  802. static struct regmap_config fsl_sai_regmap_config = {
  803. .reg_bits = 32,
  804. .reg_stride = 4,
  805. .val_bits = 32,
  806. .fast_io = true,
  807. .max_register = FSL_SAI_RMR,
  808. .reg_defaults = fsl_sai_reg_defaults_ofs0,
  809. .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
  810. .readable_reg = fsl_sai_readable_reg,
  811. .volatile_reg = fsl_sai_volatile_reg,
  812. .writeable_reg = fsl_sai_writeable_reg,
  813. .cache_type = REGCACHE_FLAT,
  814. };
  815. static int fsl_sai_check_version(struct device *dev)
  816. {
  817. struct fsl_sai *sai = dev_get_drvdata(dev);
  818. unsigned char ofs = sai->soc_data->reg_offset;
  819. unsigned int val;
  820. int ret;
  821. if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
  822. return 0;
  823. ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
  824. if (ret < 0)
  825. return ret;
  826. dev_dbg(dev, "VERID: 0x%016X\n", val);
  827. sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >>
  828. FSL_SAI_VERID_MAJOR_SHIFT;
  829. sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >>
  830. FSL_SAI_VERID_MINOR_SHIFT;
  831. sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
  832. ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
  833. if (ret < 0)
  834. return ret;
  835. dev_dbg(dev, "PARAM: 0x%016X\n", val);
  836. /* Max slots per frame, power of 2 */
  837. sai->param.slot_num = 1 <<
  838. ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
  839. /* Words per fifo, power of 2 */
  840. sai->param.fifo_depth = 1 <<
  841. ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
  842. /* Number of datalines implemented */
  843. sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
  844. return 0;
  845. }
  846. static int fsl_sai_probe(struct platform_device *pdev)
  847. {
  848. struct device_node *np = pdev->dev.of_node;
  849. struct fsl_sai *sai;
  850. struct regmap *gpr;
  851. struct resource *res;
  852. void __iomem *base;
  853. char tmp[8];
  854. int irq, ret, i;
  855. int index;
  856. sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
  857. if (!sai)
  858. return -ENOMEM;
  859. sai->pdev = pdev;
  860. sai->soc_data = of_device_get_match_data(&pdev->dev);
  861. sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
  862. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  863. base = devm_ioremap_resource(&pdev->dev, res);
  864. if (IS_ERR(base))
  865. return PTR_ERR(base);
  866. if (sai->soc_data->reg_offset == 8) {
  867. fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
  868. fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
  869. fsl_sai_regmap_config.num_reg_defaults =
  870. ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
  871. }
  872. sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
  873. "bus", base, &fsl_sai_regmap_config);
  874. /* Compatible with old DTB cases */
  875. if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER)
  876. sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
  877. "sai", base, &fsl_sai_regmap_config);
  878. if (IS_ERR(sai->regmap)) {
  879. dev_err(&pdev->dev, "regmap init failed\n");
  880. return PTR_ERR(sai->regmap);
  881. }
  882. /* No error out for old DTB cases but only mark the clock NULL */
  883. sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
  884. if (IS_ERR(sai->bus_clk)) {
  885. dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
  886. PTR_ERR(sai->bus_clk));
  887. sai->bus_clk = NULL;
  888. }
  889. sai->mclk_clk[0] = sai->bus_clk;
  890. for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
  891. sprintf(tmp, "mclk%d", i);
  892. sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
  893. if (IS_ERR(sai->mclk_clk[i])) {
  894. dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
  895. i + 1, PTR_ERR(sai->mclk_clk[i]));
  896. sai->mclk_clk[i] = NULL;
  897. }
  898. }
  899. irq = platform_get_irq(pdev, 0);
  900. if (irq < 0)
  901. return irq;
  902. ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED,
  903. np->name, sai);
  904. if (ret) {
  905. dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
  906. return ret;
  907. }
  908. memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
  909. sizeof(fsl_sai_dai_template));
  910. /* Sync Tx with Rx as default by following old DT binding */
  911. sai->synchronous[RX] = true;
  912. sai->synchronous[TX] = false;
  913. sai->cpu_dai_drv.symmetric_rates = 1;
  914. sai->cpu_dai_drv.symmetric_channels = 1;
  915. sai->cpu_dai_drv.symmetric_samplebits = 1;
  916. if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
  917. of_find_property(np, "fsl,sai-asynchronous", NULL)) {
  918. /* error out if both synchronous and asynchronous are present */
  919. dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
  920. return -EINVAL;
  921. }
  922. if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
  923. /* Sync Rx with Tx */
  924. sai->synchronous[RX] = false;
  925. sai->synchronous[TX] = true;
  926. } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
  927. /* Discard all settings for asynchronous mode */
  928. sai->synchronous[RX] = false;
  929. sai->synchronous[TX] = false;
  930. sai->cpu_dai_drv.symmetric_rates = 0;
  931. sai->cpu_dai_drv.symmetric_channels = 0;
  932. sai->cpu_dai_drv.symmetric_samplebits = 0;
  933. }
  934. if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
  935. of_device_is_compatible(np, "fsl,imx6ul-sai")) {
  936. gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
  937. if (IS_ERR(gpr)) {
  938. dev_err(&pdev->dev, "cannot find iomuxc registers\n");
  939. return PTR_ERR(gpr);
  940. }
  941. index = of_alias_get_id(np, "sai");
  942. if (index < 0)
  943. return index;
  944. regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
  945. MCLK_DIR(index));
  946. }
  947. sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
  948. sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
  949. sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
  950. sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
  951. platform_set_drvdata(pdev, sai);
  952. /* Get sai version */
  953. ret = fsl_sai_check_version(&pdev->dev);
  954. if (ret < 0)
  955. dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret);
  956. /* Select MCLK direction */
  957. if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
  958. sai->verid.major >= 3 && sai->verid.minor >= 1) {
  959. regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
  960. FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
  961. }
  962. pm_runtime_enable(&pdev->dev);
  963. regcache_cache_only(sai->regmap, true);
  964. ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
  965. &sai->cpu_dai_drv, 1);
  966. if (ret)
  967. goto err_pm_disable;
  968. if (sai->soc_data->use_imx_pcm) {
  969. ret = imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
  970. if (ret)
  971. goto err_pm_disable;
  972. } else {
  973. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  974. if (ret)
  975. goto err_pm_disable;
  976. }
  977. return ret;
  978. err_pm_disable:
  979. pm_runtime_disable(&pdev->dev);
  980. return ret;
  981. }
  982. static int fsl_sai_remove(struct platform_device *pdev)
  983. {
  984. pm_runtime_disable(&pdev->dev);
  985. return 0;
  986. }
  987. static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
  988. .use_imx_pcm = false,
  989. .use_edma = false,
  990. .fifo_depth = 32,
  991. .reg_offset = 0,
  992. };
  993. static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
  994. .use_imx_pcm = true,
  995. .use_edma = false,
  996. .fifo_depth = 32,
  997. .reg_offset = 0,
  998. };
  999. static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
  1000. .use_imx_pcm = true,
  1001. .use_edma = false,
  1002. .fifo_depth = 16,
  1003. .reg_offset = 8,
  1004. };
  1005. static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
  1006. .use_imx_pcm = true,
  1007. .use_edma = false,
  1008. .fifo_depth = 128,
  1009. .reg_offset = 8,
  1010. };
  1011. static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
  1012. .use_imx_pcm = true,
  1013. .use_edma = true,
  1014. .fifo_depth = 64,
  1015. .reg_offset = 0,
  1016. };
  1017. static const struct of_device_id fsl_sai_ids[] = {
  1018. { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
  1019. { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
  1020. { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
  1021. { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
  1022. { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
  1023. { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
  1024. { /* sentinel */ }
  1025. };
  1026. MODULE_DEVICE_TABLE(of, fsl_sai_ids);
  1027. #ifdef CONFIG_PM
  1028. static int fsl_sai_runtime_suspend(struct device *dev)
  1029. {
  1030. struct fsl_sai *sai = dev_get_drvdata(dev);
  1031. if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
  1032. clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
  1033. if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
  1034. clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
  1035. clk_disable_unprepare(sai->bus_clk);
  1036. regcache_cache_only(sai->regmap, true);
  1037. return 0;
  1038. }
  1039. static int fsl_sai_runtime_resume(struct device *dev)
  1040. {
  1041. struct fsl_sai *sai = dev_get_drvdata(dev);
  1042. unsigned int ofs = sai->soc_data->reg_offset;
  1043. int ret;
  1044. ret = clk_prepare_enable(sai->bus_clk);
  1045. if (ret) {
  1046. dev_err(dev, "failed to enable bus clock: %d\n", ret);
  1047. return ret;
  1048. }
  1049. if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
  1050. ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
  1051. if (ret)
  1052. goto disable_bus_clk;
  1053. }
  1054. if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
  1055. ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
  1056. if (ret)
  1057. goto disable_tx_clk;
  1058. }
  1059. regcache_cache_only(sai->regmap, false);
  1060. regcache_mark_dirty(sai->regmap);
  1061. regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
  1062. regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
  1063. usleep_range(1000, 2000);
  1064. regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
  1065. regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
  1066. ret = regcache_sync(sai->regmap);
  1067. if (ret)
  1068. goto disable_rx_clk;
  1069. return 0;
  1070. disable_rx_clk:
  1071. if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
  1072. clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
  1073. disable_tx_clk:
  1074. if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
  1075. clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
  1076. disable_bus_clk:
  1077. clk_disable_unprepare(sai->bus_clk);
  1078. return ret;
  1079. }
  1080. #endif /* CONFIG_PM */
  1081. static const struct dev_pm_ops fsl_sai_pm_ops = {
  1082. SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
  1083. fsl_sai_runtime_resume, NULL)
  1084. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1085. pm_runtime_force_resume)
  1086. };
  1087. static struct platform_driver fsl_sai_driver = {
  1088. .probe = fsl_sai_probe,
  1089. .remove = fsl_sai_remove,
  1090. .driver = {
  1091. .name = "fsl-sai",
  1092. .pm = &fsl_sai_pm_ops,
  1093. .of_match_table = fsl_sai_ids,
  1094. },
  1095. };
  1096. module_platform_driver(fsl_sai_driver);
  1097. MODULE_DESCRIPTION("Freescale Soc SAI Interface");
  1098. MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
  1099. MODULE_ALIAS("platform:fsl-sai");
  1100. MODULE_LICENSE("GPL");