fsl_mqs.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // ALSA SoC IMX MQS driver
  4. //
  5. // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  6. // Copyright 2019 NXP
  7. #include <linux/clk.h>
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/of.h>
  14. #include <linux/pm.h>
  15. #include <linux/slab.h>
  16. #include <sound/soc.h>
  17. #include <sound/pcm.h>
  18. #include <sound/initval.h>
  19. #define REG_MQS_CTRL 0x00
  20. #define MQS_EN_MASK (0x1 << 28)
  21. #define MQS_EN_SHIFT (28)
  22. #define MQS_SW_RST_MASK (0x1 << 24)
  23. #define MQS_SW_RST_SHIFT (24)
  24. #define MQS_OVERSAMPLE_MASK (0x1 << 20)
  25. #define MQS_OVERSAMPLE_SHIFT (20)
  26. #define MQS_CLK_DIV_MASK (0xFF << 0)
  27. #define MQS_CLK_DIV_SHIFT (0)
  28. /* codec private data */
  29. struct fsl_mqs {
  30. struct regmap *regmap;
  31. struct clk *mclk;
  32. struct clk *ipg;
  33. unsigned int reg_iomuxc_gpr2;
  34. unsigned int reg_mqs_ctrl;
  35. bool use_gpr;
  36. };
  37. #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  38. #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  39. static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
  40. struct snd_pcm_hw_params *params,
  41. struct snd_soc_dai *dai)
  42. {
  43. struct snd_soc_component *component = dai->component;
  44. struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
  45. unsigned long mclk_rate;
  46. int div, res;
  47. int lrclk;
  48. mclk_rate = clk_get_rate(mqs_priv->mclk);
  49. lrclk = params_rate(params);
  50. /*
  51. * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
  52. * if repeat_rate is 8, mqs can achieve better quality.
  53. * oversample rate is fix to 32 currently.
  54. */
  55. div = mclk_rate / (32 * lrclk * 2 * 8);
  56. res = mclk_rate % (32 * lrclk * 2 * 8);
  57. if (res == 0 && div > 0 && div <= 256) {
  58. if (mqs_priv->use_gpr) {
  59. regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
  60. IMX6SX_GPR2_MQS_CLK_DIV_MASK,
  61. (div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT);
  62. regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
  63. IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0);
  64. } else {
  65. regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
  66. MQS_CLK_DIV_MASK,
  67. (div - 1) << MQS_CLK_DIV_SHIFT);
  68. regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
  69. MQS_OVERSAMPLE_MASK, 0);
  70. }
  71. } else {
  72. dev_err(component->dev, "can't get proper divider\n");
  73. }
  74. return 0;
  75. }
  76. static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  77. {
  78. /* Only LEFT_J & SLAVE mode is supported. */
  79. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  80. case SND_SOC_DAIFMT_LEFT_J:
  81. break;
  82. default:
  83. return -EINVAL;
  84. }
  85. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  86. case SND_SOC_DAIFMT_NB_NF:
  87. break;
  88. default:
  89. return -EINVAL;
  90. }
  91. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  92. case SND_SOC_DAIFMT_CBS_CFS:
  93. break;
  94. default:
  95. return -EINVAL;
  96. }
  97. return 0;
  98. }
  99. static int fsl_mqs_startup(struct snd_pcm_substream *substream,
  100. struct snd_soc_dai *dai)
  101. {
  102. struct snd_soc_component *component = dai->component;
  103. struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
  104. if (mqs_priv->use_gpr)
  105. regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
  106. IMX6SX_GPR2_MQS_EN_MASK,
  107. 1 << IMX6SX_GPR2_MQS_EN_SHIFT);
  108. else
  109. regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
  110. MQS_EN_MASK,
  111. 1 << MQS_EN_SHIFT);
  112. return 0;
  113. }
  114. static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
  115. struct snd_soc_dai *dai)
  116. {
  117. struct snd_soc_component *component = dai->component;
  118. struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
  119. if (mqs_priv->use_gpr)
  120. regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
  121. IMX6SX_GPR2_MQS_EN_MASK, 0);
  122. else
  123. regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
  124. MQS_EN_MASK, 0);
  125. }
  126. static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
  127. .idle_bias_on = 1,
  128. .non_legacy_dai_naming = 1,
  129. };
  130. static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {
  131. .startup = fsl_mqs_startup,
  132. .shutdown = fsl_mqs_shutdown,
  133. .hw_params = fsl_mqs_hw_params,
  134. .set_fmt = fsl_mqs_set_dai_fmt,
  135. };
  136. static struct snd_soc_dai_driver fsl_mqs_dai = {
  137. .name = "fsl-mqs-dai",
  138. .playback = {
  139. .stream_name = "Playback",
  140. .channels_min = 2,
  141. .channels_max = 2,
  142. .rates = FSL_MQS_RATES,
  143. .formats = FSL_MQS_FORMATS,
  144. },
  145. .ops = &fsl_mqs_dai_ops,
  146. };
  147. static const struct regmap_config fsl_mqs_regmap_config = {
  148. .reg_bits = 32,
  149. .reg_stride = 4,
  150. .val_bits = 32,
  151. .max_register = REG_MQS_CTRL,
  152. .cache_type = REGCACHE_NONE,
  153. };
  154. static int fsl_mqs_probe(struct platform_device *pdev)
  155. {
  156. struct device_node *np = pdev->dev.of_node;
  157. struct device_node *gpr_np = NULL;
  158. struct fsl_mqs *mqs_priv;
  159. void __iomem *regs;
  160. int ret;
  161. mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
  162. if (!mqs_priv)
  163. return -ENOMEM;
  164. /* On i.MX6sx the MQS control register is in GPR domain
  165. * But in i.MX8QM/i.MX8QXP the control register is moved
  166. * to its own domain.
  167. */
  168. if (of_device_is_compatible(np, "fsl,imx8qm-mqs"))
  169. mqs_priv->use_gpr = false;
  170. else
  171. mqs_priv->use_gpr = true;
  172. if (mqs_priv->use_gpr) {
  173. gpr_np = of_parse_phandle(np, "gpr", 0);
  174. if (!gpr_np) {
  175. dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
  176. return -EINVAL;
  177. }
  178. mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
  179. if (IS_ERR(mqs_priv->regmap)) {
  180. dev_err(&pdev->dev, "failed to get gpr regmap\n");
  181. ret = PTR_ERR(mqs_priv->regmap);
  182. goto err_free_gpr_np;
  183. }
  184. } else {
  185. regs = devm_platform_ioremap_resource(pdev, 0);
  186. if (IS_ERR(regs))
  187. return PTR_ERR(regs);
  188. mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
  189. "core",
  190. regs,
  191. &fsl_mqs_regmap_config);
  192. if (IS_ERR(mqs_priv->regmap)) {
  193. dev_err(&pdev->dev, "failed to init regmap: %ld\n",
  194. PTR_ERR(mqs_priv->regmap));
  195. return PTR_ERR(mqs_priv->regmap);
  196. }
  197. mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");
  198. if (IS_ERR(mqs_priv->ipg)) {
  199. dev_err(&pdev->dev, "failed to get the clock: %ld\n",
  200. PTR_ERR(mqs_priv->ipg));
  201. return PTR_ERR(mqs_priv->ipg);
  202. }
  203. }
  204. mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");
  205. if (IS_ERR(mqs_priv->mclk)) {
  206. dev_err(&pdev->dev, "failed to get the clock: %ld\n",
  207. PTR_ERR(mqs_priv->mclk));
  208. ret = PTR_ERR(mqs_priv->mclk);
  209. goto err_free_gpr_np;
  210. }
  211. dev_set_drvdata(&pdev->dev, mqs_priv);
  212. pm_runtime_enable(&pdev->dev);
  213. ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs,
  214. &fsl_mqs_dai, 1);
  215. if (ret)
  216. goto err_free_gpr_np;
  217. return 0;
  218. err_free_gpr_np:
  219. of_node_put(gpr_np);
  220. return ret;
  221. }
  222. static int fsl_mqs_remove(struct platform_device *pdev)
  223. {
  224. pm_runtime_disable(&pdev->dev);
  225. return 0;
  226. }
  227. #ifdef CONFIG_PM
  228. static int fsl_mqs_runtime_resume(struct device *dev)
  229. {
  230. struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
  231. int ret;
  232. ret = clk_prepare_enable(mqs_priv->ipg);
  233. if (ret) {
  234. dev_err(dev, "failed to enable ipg clock\n");
  235. return ret;
  236. }
  237. ret = clk_prepare_enable(mqs_priv->mclk);
  238. if (ret) {
  239. dev_err(dev, "failed to enable mclk clock\n");
  240. clk_disable_unprepare(mqs_priv->ipg);
  241. return ret;
  242. }
  243. if (mqs_priv->use_gpr)
  244. regmap_write(mqs_priv->regmap, IOMUXC_GPR2,
  245. mqs_priv->reg_iomuxc_gpr2);
  246. else
  247. regmap_write(mqs_priv->regmap, REG_MQS_CTRL,
  248. mqs_priv->reg_mqs_ctrl);
  249. return 0;
  250. }
  251. static int fsl_mqs_runtime_suspend(struct device *dev)
  252. {
  253. struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
  254. if (mqs_priv->use_gpr)
  255. regmap_read(mqs_priv->regmap, IOMUXC_GPR2,
  256. &mqs_priv->reg_iomuxc_gpr2);
  257. else
  258. regmap_read(mqs_priv->regmap, REG_MQS_CTRL,
  259. &mqs_priv->reg_mqs_ctrl);
  260. clk_disable_unprepare(mqs_priv->mclk);
  261. clk_disable_unprepare(mqs_priv->ipg);
  262. return 0;
  263. }
  264. #endif
  265. static const struct dev_pm_ops fsl_mqs_pm_ops = {
  266. SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
  267. fsl_mqs_runtime_resume,
  268. NULL)
  269. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  270. pm_runtime_force_resume)
  271. };
  272. static const struct of_device_id fsl_mqs_dt_ids[] = {
  273. { .compatible = "fsl,imx8qm-mqs", },
  274. { .compatible = "fsl,imx6sx-mqs", },
  275. {}
  276. };
  277. MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
  278. static struct platform_driver fsl_mqs_driver = {
  279. .probe = fsl_mqs_probe,
  280. .remove = fsl_mqs_remove,
  281. .driver = {
  282. .name = "fsl-mqs",
  283. .of_match_table = fsl_mqs_dt_ids,
  284. .pm = &fsl_mqs_pm_ops,
  285. },
  286. };
  287. module_platform_driver(fsl_mqs_driver);
  288. MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>");
  289. MODULE_DESCRIPTION("MQS codec driver");
  290. MODULE_LICENSE("GPL v2");
  291. MODULE_ALIAS("platform:fsl-mqs");