fsl_micfil.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * PDM Microphone Interface for the NXP i.MX SoC
  4. * Copyright 2018 NXP
  5. */
  6. #ifndef _FSL_MICFIL_H
  7. #define _FSL_MICFIL_H
  8. /* MICFIL Register Map */
  9. #define REG_MICFIL_CTRL1 0x00
  10. #define REG_MICFIL_CTRL2 0x04
  11. #define REG_MICFIL_STAT 0x08
  12. #define REG_MICFIL_FIFO_CTRL 0x10
  13. #define REG_MICFIL_FIFO_STAT 0x14
  14. #define REG_MICFIL_DATACH0 0x24
  15. #define REG_MICFIL_DATACH1 0x28
  16. #define REG_MICFIL_DATACH2 0x2C
  17. #define REG_MICFIL_DATACH3 0x30
  18. #define REG_MICFIL_DATACH4 0x34
  19. #define REG_MICFIL_DATACH5 0x38
  20. #define REG_MICFIL_DATACH6 0x3C
  21. #define REG_MICFIL_DATACH7 0x40
  22. #define REG_MICFIL_DC_CTRL 0x64
  23. #define REG_MICFIL_OUT_CTRL 0x74
  24. #define REG_MICFIL_OUT_STAT 0x7C
  25. #define REG_MICFIL_VAD0_CTRL1 0x90
  26. #define REG_MICFIL_VAD0_CTRL2 0x94
  27. #define REG_MICFIL_VAD0_STAT 0x98
  28. #define REG_MICFIL_VAD0_SCONFIG 0x9C
  29. #define REG_MICFIL_VAD0_NCONFIG 0xA0
  30. #define REG_MICFIL_VAD0_NDATA 0xA4
  31. #define REG_MICFIL_VAD0_ZCD 0xA8
  32. /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
  33. #define MICFIL_CTRL1_MDIS_SHIFT 31
  34. #define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
  35. #define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
  36. #define MICFIL_CTRL1_DOZEN_SHIFT 30
  37. #define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
  38. #define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
  39. #define MICFIL_CTRL1_PDMIEN_SHIFT 29
  40. #define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
  41. #define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
  42. #define MICFIL_CTRL1_DBG_SHIFT 28
  43. #define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
  44. #define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
  45. #define MICFIL_CTRL1_SRES_SHIFT 27
  46. #define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT)
  47. #define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT)
  48. #define MICFIL_CTRL1_DBGE_SHIFT 26
  49. #define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT)
  50. #define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT)
  51. #define MICFIL_CTRL1_DISEL_SHIFT 24
  52. #define MICFIL_CTRL1_DISEL_WIDTH 2
  53. #define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
  54. << MICFIL_CTRL1_DISEL_SHIFT)
  55. #define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
  56. & MICFIL_CTRL1_DISEL_MASK)
  57. #define MICFIL_CTRL1_ERREN_SHIFT 23
  58. #define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT)
  59. #define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT)
  60. #define MICFIL_CTRL1_CHEN_SHIFT 0
  61. #define MICFIL_CTRL1_CHEN_WIDTH 8
  62. #define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
  63. #define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
  64. /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
  65. #define MICFIL_CTRL2_QSEL_SHIFT 25
  66. #define MICFIL_CTRL2_QSEL_WIDTH 3
  67. #define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
  68. << MICFIL_CTRL2_QSEL_SHIFT)
  69. #define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT)
  70. #define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT)
  71. #define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT)
  72. #define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT)
  73. #define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
  74. #define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
  75. #define MICFIL_CTRL2_CICOSR_SHIFT 16
  76. #define MICFIL_CTRL2_CICOSR_WIDTH 4
  77. #define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
  78. << MICFIL_CTRL2_CICOSR_SHIFT)
  79. #define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
  80. & MICFIL_CTRL2_CICOSR_MASK)
  81. #define MICFIL_CTRL2_CLKDIV_SHIFT 0
  82. #define MICFIL_CTRL2_CLKDIV_WIDTH 8
  83. #define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
  84. << MICFIL_CTRL2_CLKDIV_SHIFT)
  85. #define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
  86. & MICFIL_CTRL2_CLKDIV_MASK)
  87. /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
  88. #define MICFIL_STAT_BSY_FIL_SHIFT 31
  89. #define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT)
  90. #define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT)
  91. #define MICFIL_STAT_FIR_RDY_SHIFT 30
  92. #define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT)
  93. #define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT)
  94. #define MICFIL_STAT_LOWFREQF_SHIFT 29
  95. #define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT)
  96. #define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT)
  97. #define MICFIL_STAT_CHXF_SHIFT(v) (v)
  98. #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
  99. #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
  100. /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
  101. #define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0
  102. #define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
  103. #define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
  104. << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
  105. #define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
  106. & MICFIL_FIFO_CTRL_FIFOWMK_MASK)
  107. /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
  108. #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v)
  109. #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
  110. #define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8)
  111. #define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
  112. /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
  113. #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24
  114. #define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3
  115. #define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
  116. << MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
  117. #define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
  118. & MICFIL_VAD0_CTRL1_CHSEL_MASK)
  119. #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16
  120. #define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4
  121. #define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
  122. << MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
  123. #define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
  124. & MICFIL_VAD0_CTRL1_CICOSR_MASK)
  125. #define MICFIL_VAD0_CTRL1_INITT_SHIFT 8
  126. #define MICFIL_VAD0_CTRL1_INITT_WIDTH 5
  127. #define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
  128. << MICFIL_VAD0_CTRL1_INITT_SHIFT)
  129. #define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
  130. & MICFIL_VAD0_CTRL1_INITT_MASK)
  131. #define MICFIL_VAD0_CTRL1_ST10_SHIFT 4
  132. #define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
  133. #define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
  134. #define MICFIL_VAD0_CTRL1_ERIE_SHIFT 3
  135. #define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
  136. #define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
  137. #define MICFIL_VAD0_CTRL1_IE_SHIFT 2
  138. #define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
  139. #define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
  140. #define MICFIL_VAD0_CTRL1_RST_SHIFT 1
  141. #define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
  142. #define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
  143. #define MICFIL_VAD0_CTRL1_EN_SHIFT 0
  144. #define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
  145. #define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
  146. /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
  147. #define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31
  148. #define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
  149. #define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
  150. #define MICFIL_VAD0_CTRL2_PREFEN_SHIFT 30
  151. #define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
  152. #define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
  153. #define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28
  154. #define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
  155. #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
  156. #define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
  157. #define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
  158. #define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
  159. << MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
  160. #define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
  161. & MICFIL_VAD0_CTRL2_FRAMET_MASK)
  162. #define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
  163. #define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
  164. #define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
  165. << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
  166. #define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
  167. & MICFIL_VAD0_CTRL2_INPGAIN_MASK)
  168. #define MICFIL_VAD0_CTRL2_HPF_SHIFT 0
  169. #define MICFIL_VAD0_CTRL2_HPF_WIDTH 2
  170. #define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
  171. << MICFIL_VAD0_CTRL2_HPF_SHIFT)
  172. #define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
  173. & MICFIL_VAD0_CTRL2_HPF_MASK)
  174. /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
  175. #define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT 31
  176. #define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
  177. #define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
  178. #define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT 30
  179. #define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
  180. #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
  181. #define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
  182. #define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
  183. #define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
  184. << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
  185. #define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
  186. & MICFIL_VAD0_SCONFIG_SGAIN_MASK)
  187. /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
  188. #define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT 31
  189. #define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
  190. #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
  191. #define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT 30
  192. #define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
  193. #define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
  194. #define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT 29
  195. #define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
  196. #define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
  197. #define MICFIL_VAD0_NCONFIG_NOREN_SHIFT 28
  198. #define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
  199. #define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
  200. #define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
  201. #define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
  202. << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
  203. #define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
  204. & MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
  205. #define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0
  206. #define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4
  207. #define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
  208. << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
  209. #define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
  210. & MICFIL_VAD0_NCONFIG_NGAIN_MASK)
  211. /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
  212. #define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16
  213. #define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10
  214. #define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
  215. << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
  216. #define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
  217. & MICFIL_VAD0_ZCD_ZCDTH_MASK)
  218. #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8
  219. #define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4
  220. #define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
  221. << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
  222. #define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
  223. & MICFIL_VAD0_ZCD_ZCDADJ_MASK)
  224. #define MICFIL_VAD0_ZCD_ZCDAND_SHIFT 4
  225. #define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
  226. #define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
  227. #define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT 2
  228. #define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
  229. #define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
  230. #define MICFIL_VAD0_ZCD_ZCDEN_SHIFT 0
  231. #define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
  232. #define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
  233. /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
  234. #define MICFIL_VAD0_STAT_INITF_SHIFT 31
  235. #define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
  236. #define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
  237. #define MICFIL_VAD0_STAT_INSATF_SHIFT 16
  238. #define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
  239. #define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
  240. #define MICFIL_VAD0_STAT_EF_SHIFT 15
  241. #define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT)
  242. #define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT)
  243. #define MICFIL_VAD0_STAT_IF_SHIFT 0
  244. #define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT)
  245. #define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT)
  246. /* MICFIL Output Control Register */
  247. #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
  248. /* Constants */
  249. #define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
  250. #define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
  251. == ((v) & MICFIL_CTRL1_DISEL_MASK))
  252. #define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
  253. == ((v) & MICFIL_CTRL1_DISEL_MASK))
  254. #define MICFIL_OUTPUT_CHANNELS 8
  255. #define MICFIL_FIFO_NUM 8
  256. #define FIFO_PTRWID 3
  257. #define FIFO_LEN BIT(FIFO_PTRWID)
  258. #define MICFIL_IRQ_LINES 2
  259. #define MICFIL_MAX_RETRY 25
  260. #define MICFIL_SLEEP_MIN 90000 /* in us */
  261. #define MICFIL_SLEEP_MAX 100000 /* in us */
  262. #define MICFIL_DMA_MAXBURST_RX 6
  263. #define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
  264. #endif /* _FSL_MICFIL_H */