fsl_micfil.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright 2018 NXP
  3. #include <linux/clk.h>
  4. #include <linux/device.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/kobject.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_irq.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/regmap.h>
  15. #include <linux/sysfs.h>
  16. #include <linux/types.h>
  17. #include <sound/dmaengine_pcm.h>
  18. #include <sound/pcm.h>
  19. #include <sound/soc.h>
  20. #include <sound/tlv.h>
  21. #include <sound/core.h>
  22. #include "fsl_micfil.h"
  23. #include "imx-pcm.h"
  24. #define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
  25. #define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
  26. struct fsl_micfil {
  27. struct platform_device *pdev;
  28. struct regmap *regmap;
  29. const struct fsl_micfil_soc_data *soc;
  30. struct clk *mclk;
  31. struct snd_dmaengine_dai_dma_data dma_params_rx;
  32. unsigned int dataline;
  33. char name[32];
  34. int irq[MICFIL_IRQ_LINES];
  35. unsigned int mclk_streams;
  36. int quality; /*QUALITY 2-0 bits */
  37. bool slave_mode;
  38. int channel_gain[8];
  39. };
  40. struct fsl_micfil_soc_data {
  41. unsigned int fifos;
  42. unsigned int fifo_depth;
  43. unsigned int dataline;
  44. bool imx;
  45. };
  46. static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
  47. .imx = true,
  48. .fifos = 8,
  49. .fifo_depth = 8,
  50. .dataline = 0xf,
  51. };
  52. static const struct of_device_id fsl_micfil_dt_ids[] = {
  53. { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
  54. {}
  55. };
  56. MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
  57. /* Table 5. Quality Modes
  58. * Medium 0 0 0
  59. * High 0 0 1
  60. * Very Low 2 1 0 0
  61. * Very Low 1 1 0 1
  62. * Very Low 0 1 1 0
  63. * Low 1 1 1
  64. */
  65. static const char * const micfil_quality_select_texts[] = {
  66. "Medium", "High",
  67. "N/A", "N/A",
  68. "VLow2", "VLow1",
  69. "VLow0", "Low",
  70. };
  71. static const struct soc_enum fsl_micfil_quality_enum =
  72. SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
  73. MICFIL_CTRL2_QSEL_SHIFT,
  74. ARRAY_SIZE(micfil_quality_select_texts),
  75. micfil_quality_select_texts);
  76. static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
  77. static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
  78. SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
  79. MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
  80. SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
  81. MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
  82. SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
  83. MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
  84. SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
  85. MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
  86. SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
  87. MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
  88. SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
  89. MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
  90. SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
  91. MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
  92. SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
  93. MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
  94. SOC_ENUM_EXT("MICFIL Quality Select",
  95. fsl_micfil_quality_enum,
  96. snd_soc_get_enum_double, snd_soc_put_enum_double),
  97. };
  98. static inline int get_pdm_clk(struct fsl_micfil *micfil,
  99. unsigned int rate)
  100. {
  101. u32 ctrl2_reg;
  102. int qsel, osr;
  103. int bclk;
  104. regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
  105. osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
  106. >> MICFIL_CTRL2_CICOSR_SHIFT);
  107. regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
  108. qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
  109. switch (qsel) {
  110. case MICFIL_HIGH_QUALITY:
  111. bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
  112. break;
  113. case MICFIL_MEDIUM_QUALITY:
  114. case MICFIL_VLOW0_QUALITY:
  115. bclk = rate * 4 * osr * 1; /* kfactor = 1 */
  116. break;
  117. case MICFIL_LOW_QUALITY:
  118. case MICFIL_VLOW1_QUALITY:
  119. bclk = rate * 2 * osr * 2; /* kfactor = 2 */
  120. break;
  121. case MICFIL_VLOW2_QUALITY:
  122. bclk = rate * osr * 4; /* kfactor = 4 */
  123. break;
  124. default:
  125. dev_err(&micfil->pdev->dev,
  126. "Please make sure you select a valid quality.\n");
  127. bclk = -1;
  128. break;
  129. }
  130. return bclk;
  131. }
  132. static inline int get_clk_div(struct fsl_micfil *micfil,
  133. unsigned int rate)
  134. {
  135. u32 ctrl2_reg;
  136. long mclk_rate;
  137. int clk_div;
  138. regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
  139. mclk_rate = clk_get_rate(micfil->mclk);
  140. clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
  141. return clk_div;
  142. }
  143. /* The SRES is a self-negated bit which provides the CPU with the
  144. * capability to initialize the PDM Interface module through the
  145. * slave-bus interface. This bit always reads as zero, and this
  146. * bit is only effective when MDIS is cleared
  147. */
  148. static int fsl_micfil_reset(struct device *dev)
  149. {
  150. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  151. int ret;
  152. ret = regmap_update_bits(micfil->regmap,
  153. REG_MICFIL_CTRL1,
  154. MICFIL_CTRL1_MDIS_MASK,
  155. 0);
  156. if (ret) {
  157. dev_err(dev, "failed to clear MDIS bit %d\n", ret);
  158. return ret;
  159. }
  160. ret = regmap_update_bits(micfil->regmap,
  161. REG_MICFIL_CTRL1,
  162. MICFIL_CTRL1_SRES_MASK,
  163. MICFIL_CTRL1_SRES);
  164. if (ret) {
  165. dev_err(dev, "failed to reset MICFIL: %d\n", ret);
  166. return ret;
  167. }
  168. return 0;
  169. }
  170. static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
  171. unsigned int freq)
  172. {
  173. struct device *dev = &micfil->pdev->dev;
  174. int ret;
  175. clk_disable_unprepare(micfil->mclk);
  176. ret = clk_set_rate(micfil->mclk, freq * 1024);
  177. if (ret)
  178. dev_warn(dev, "failed to set rate (%u): %d\n",
  179. freq * 1024, ret);
  180. clk_prepare_enable(micfil->mclk);
  181. return ret;
  182. }
  183. static int fsl_micfil_startup(struct snd_pcm_substream *substream,
  184. struct snd_soc_dai *dai)
  185. {
  186. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  187. if (!micfil) {
  188. dev_err(dai->dev, "micfil dai priv_data not set\n");
  189. return -EINVAL;
  190. }
  191. return 0;
  192. }
  193. static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
  194. struct snd_soc_dai *dai)
  195. {
  196. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  197. struct device *dev = &micfil->pdev->dev;
  198. int ret;
  199. switch (cmd) {
  200. case SNDRV_PCM_TRIGGER_START:
  201. case SNDRV_PCM_TRIGGER_RESUME:
  202. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  203. ret = fsl_micfil_reset(dev);
  204. if (ret) {
  205. dev_err(dev, "failed to soft reset\n");
  206. return ret;
  207. }
  208. /* DMA Interrupt Selection - DISEL bits
  209. * 00 - DMA and IRQ disabled
  210. * 01 - DMA req enabled
  211. * 10 - IRQ enabled
  212. * 11 - reserved
  213. */
  214. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  215. MICFIL_CTRL1_DISEL_MASK,
  216. (1 << MICFIL_CTRL1_DISEL_SHIFT));
  217. if (ret) {
  218. dev_err(dev, "failed to update DISEL bits\n");
  219. return ret;
  220. }
  221. /* Enable the module */
  222. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  223. MICFIL_CTRL1_PDMIEN_MASK,
  224. MICFIL_CTRL1_PDMIEN);
  225. if (ret) {
  226. dev_err(dev, "failed to enable the module\n");
  227. return ret;
  228. }
  229. break;
  230. case SNDRV_PCM_TRIGGER_STOP:
  231. case SNDRV_PCM_TRIGGER_SUSPEND:
  232. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  233. /* Disable the module */
  234. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  235. MICFIL_CTRL1_PDMIEN_MASK,
  236. 0);
  237. if (ret) {
  238. dev_err(dev, "failed to enable the module\n");
  239. return ret;
  240. }
  241. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  242. MICFIL_CTRL1_DISEL_MASK,
  243. (0 << MICFIL_CTRL1_DISEL_SHIFT));
  244. if (ret) {
  245. dev_err(dev, "failed to update DISEL bits\n");
  246. return ret;
  247. }
  248. break;
  249. default:
  250. return -EINVAL;
  251. }
  252. return 0;
  253. }
  254. static int fsl_set_clock_params(struct device *dev, unsigned int rate)
  255. {
  256. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  257. int clk_div;
  258. int ret;
  259. ret = fsl_micfil_set_mclk_rate(micfil, rate);
  260. if (ret < 0)
  261. dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
  262. clk_get_rate(micfil->mclk), rate);
  263. /* set CICOSR */
  264. ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
  265. MICFIL_CTRL2_CICOSR_MASK,
  266. MICFIL_CTRL2_OSR_DEFAULT);
  267. if (ret)
  268. dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
  269. REG_MICFIL_CTRL2);
  270. /* set CLK_DIV */
  271. clk_div = get_clk_div(micfil, rate);
  272. if (clk_div < 0)
  273. ret = -EINVAL;
  274. ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
  275. MICFIL_CTRL2_CLKDIV_MASK, clk_div);
  276. if (ret)
  277. dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
  278. REG_MICFIL_CTRL2);
  279. return ret;
  280. }
  281. static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
  282. struct snd_pcm_hw_params *params,
  283. struct snd_soc_dai *dai)
  284. {
  285. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  286. unsigned int channels = params_channels(params);
  287. unsigned int rate = params_rate(params);
  288. struct device *dev = &micfil->pdev->dev;
  289. int ret;
  290. /* 1. Disable the module */
  291. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  292. MICFIL_CTRL1_PDMIEN_MASK, 0);
  293. if (ret) {
  294. dev_err(dev, "failed to disable the module\n");
  295. return ret;
  296. }
  297. /* enable channels */
  298. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
  299. 0xFF, ((1 << channels) - 1));
  300. if (ret) {
  301. dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
  302. REG_MICFIL_CTRL1);
  303. return ret;
  304. }
  305. ret = fsl_set_clock_params(dev, rate);
  306. if (ret < 0) {
  307. dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
  308. return ret;
  309. }
  310. micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
  311. return 0;
  312. }
  313. static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  314. unsigned int freq, int dir)
  315. {
  316. struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
  317. struct device *dev = &micfil->pdev->dev;
  318. int ret;
  319. if (!freq)
  320. return 0;
  321. ret = fsl_micfil_set_mclk_rate(micfil, freq);
  322. if (ret < 0)
  323. dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
  324. clk_get_rate(micfil->mclk), freq);
  325. return ret;
  326. }
  327. static struct snd_soc_dai_ops fsl_micfil_dai_ops = {
  328. .startup = fsl_micfil_startup,
  329. .trigger = fsl_micfil_trigger,
  330. .hw_params = fsl_micfil_hw_params,
  331. .set_sysclk = fsl_micfil_set_dai_sysclk,
  332. };
  333. static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
  334. {
  335. struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
  336. struct device *dev = cpu_dai->dev;
  337. unsigned int val;
  338. int ret;
  339. int i;
  340. /* set qsel to medium */
  341. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
  342. MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
  343. if (ret) {
  344. dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
  345. REG_MICFIL_CTRL2);
  346. return ret;
  347. }
  348. /* set default gain to max_gain */
  349. regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
  350. for (i = 0; i < 8; i++)
  351. micfil->channel_gain[i] = 0xF;
  352. snd_soc_dai_init_dma_data(cpu_dai, NULL,
  353. &micfil->dma_params_rx);
  354. /* FIFO Watermark Control - FIFOWMK*/
  355. val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
  356. ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
  357. MICFIL_FIFO_CTRL_FIFOWMK_MASK,
  358. val);
  359. if (ret) {
  360. dev_err(dev, "failed to set FIFOWMK\n");
  361. return ret;
  362. }
  363. snd_soc_dai_set_drvdata(cpu_dai, micfil);
  364. return 0;
  365. }
  366. static struct snd_soc_dai_driver fsl_micfil_dai = {
  367. .probe = fsl_micfil_dai_probe,
  368. .capture = {
  369. .stream_name = "CPU-Capture",
  370. .channels_min = 1,
  371. .channels_max = 8,
  372. .rates = FSL_MICFIL_RATES,
  373. .formats = FSL_MICFIL_FORMATS,
  374. },
  375. .ops = &fsl_micfil_dai_ops,
  376. };
  377. static const struct snd_soc_component_driver fsl_micfil_component = {
  378. .name = "fsl-micfil-dai",
  379. .controls = fsl_micfil_snd_controls,
  380. .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
  381. };
  382. /* REGMAP */
  383. static const struct reg_default fsl_micfil_reg_defaults[] = {
  384. {REG_MICFIL_CTRL1, 0x00000000},
  385. {REG_MICFIL_CTRL2, 0x00000000},
  386. {REG_MICFIL_STAT, 0x00000000},
  387. {REG_MICFIL_FIFO_CTRL, 0x00000007},
  388. {REG_MICFIL_FIFO_STAT, 0x00000000},
  389. {REG_MICFIL_DATACH0, 0x00000000},
  390. {REG_MICFIL_DATACH1, 0x00000000},
  391. {REG_MICFIL_DATACH2, 0x00000000},
  392. {REG_MICFIL_DATACH3, 0x00000000},
  393. {REG_MICFIL_DATACH4, 0x00000000},
  394. {REG_MICFIL_DATACH5, 0x00000000},
  395. {REG_MICFIL_DATACH6, 0x00000000},
  396. {REG_MICFIL_DATACH7, 0x00000000},
  397. {REG_MICFIL_DC_CTRL, 0x00000000},
  398. {REG_MICFIL_OUT_CTRL, 0x00000000},
  399. {REG_MICFIL_OUT_STAT, 0x00000000},
  400. {REG_MICFIL_VAD0_CTRL1, 0x00000000},
  401. {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
  402. {REG_MICFIL_VAD0_STAT, 0x00000000},
  403. {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
  404. {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
  405. {REG_MICFIL_VAD0_NDATA, 0x00000000},
  406. {REG_MICFIL_VAD0_ZCD, 0x00000004},
  407. };
  408. static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
  409. {
  410. switch (reg) {
  411. case REG_MICFIL_CTRL1:
  412. case REG_MICFIL_CTRL2:
  413. case REG_MICFIL_STAT:
  414. case REG_MICFIL_FIFO_CTRL:
  415. case REG_MICFIL_FIFO_STAT:
  416. case REG_MICFIL_DATACH0:
  417. case REG_MICFIL_DATACH1:
  418. case REG_MICFIL_DATACH2:
  419. case REG_MICFIL_DATACH3:
  420. case REG_MICFIL_DATACH4:
  421. case REG_MICFIL_DATACH5:
  422. case REG_MICFIL_DATACH6:
  423. case REG_MICFIL_DATACH7:
  424. case REG_MICFIL_DC_CTRL:
  425. case REG_MICFIL_OUT_CTRL:
  426. case REG_MICFIL_OUT_STAT:
  427. case REG_MICFIL_VAD0_CTRL1:
  428. case REG_MICFIL_VAD0_CTRL2:
  429. case REG_MICFIL_VAD0_STAT:
  430. case REG_MICFIL_VAD0_SCONFIG:
  431. case REG_MICFIL_VAD0_NCONFIG:
  432. case REG_MICFIL_VAD0_NDATA:
  433. case REG_MICFIL_VAD0_ZCD:
  434. return true;
  435. default:
  436. return false;
  437. }
  438. }
  439. static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
  440. {
  441. switch (reg) {
  442. case REG_MICFIL_CTRL1:
  443. case REG_MICFIL_CTRL2:
  444. case REG_MICFIL_STAT: /* Write 1 to Clear */
  445. case REG_MICFIL_FIFO_CTRL:
  446. case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
  447. case REG_MICFIL_DC_CTRL:
  448. case REG_MICFIL_OUT_CTRL:
  449. case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
  450. case REG_MICFIL_VAD0_CTRL1:
  451. case REG_MICFIL_VAD0_CTRL2:
  452. case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
  453. case REG_MICFIL_VAD0_SCONFIG:
  454. case REG_MICFIL_VAD0_NCONFIG:
  455. case REG_MICFIL_VAD0_ZCD:
  456. return true;
  457. default:
  458. return false;
  459. }
  460. }
  461. static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
  462. {
  463. switch (reg) {
  464. case REG_MICFIL_STAT:
  465. case REG_MICFIL_DATACH0:
  466. case REG_MICFIL_DATACH1:
  467. case REG_MICFIL_DATACH2:
  468. case REG_MICFIL_DATACH3:
  469. case REG_MICFIL_DATACH4:
  470. case REG_MICFIL_DATACH5:
  471. case REG_MICFIL_DATACH6:
  472. case REG_MICFIL_DATACH7:
  473. case REG_MICFIL_VAD0_STAT:
  474. case REG_MICFIL_VAD0_NDATA:
  475. return true;
  476. default:
  477. return false;
  478. }
  479. }
  480. static const struct regmap_config fsl_micfil_regmap_config = {
  481. .reg_bits = 32,
  482. .reg_stride = 4,
  483. .val_bits = 32,
  484. .max_register = REG_MICFIL_VAD0_ZCD,
  485. .reg_defaults = fsl_micfil_reg_defaults,
  486. .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
  487. .readable_reg = fsl_micfil_readable_reg,
  488. .volatile_reg = fsl_micfil_volatile_reg,
  489. .writeable_reg = fsl_micfil_writeable_reg,
  490. .cache_type = REGCACHE_RBTREE,
  491. };
  492. /* END OF REGMAP */
  493. static irqreturn_t micfil_isr(int irq, void *devid)
  494. {
  495. struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
  496. struct platform_device *pdev = micfil->pdev;
  497. u32 stat_reg;
  498. u32 fifo_stat_reg;
  499. u32 ctrl1_reg;
  500. bool dma_enabled;
  501. int i;
  502. regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
  503. regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
  504. regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
  505. dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
  506. /* Channel 0-7 Output Data Flags */
  507. for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
  508. if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
  509. dev_dbg(&pdev->dev,
  510. "Data available in Data Channel %d\n", i);
  511. /* if DMA is not enabled, field must be written with 1
  512. * to clear
  513. */
  514. if (!dma_enabled)
  515. regmap_write_bits(micfil->regmap,
  516. REG_MICFIL_STAT,
  517. MICFIL_STAT_CHXF_MASK(i),
  518. 1);
  519. }
  520. for (i = 0; i < MICFIL_FIFO_NUM; i++) {
  521. if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
  522. dev_dbg(&pdev->dev,
  523. "FIFO Overflow Exception flag for channel %d\n",
  524. i);
  525. if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
  526. dev_dbg(&pdev->dev,
  527. "FIFO Underflow Exception flag for channel %d\n",
  528. i);
  529. }
  530. return IRQ_HANDLED;
  531. }
  532. static irqreturn_t micfil_err_isr(int irq, void *devid)
  533. {
  534. struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
  535. struct platform_device *pdev = micfil->pdev;
  536. u32 stat_reg;
  537. regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
  538. if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
  539. dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
  540. if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
  541. dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
  542. if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
  543. dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
  544. regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
  545. MICFIL_STAT_LOWFREQF_MASK, 1);
  546. }
  547. return IRQ_HANDLED;
  548. }
  549. static int fsl_micfil_probe(struct platform_device *pdev)
  550. {
  551. struct device_node *np = pdev->dev.of_node;
  552. const struct of_device_id *of_id;
  553. struct fsl_micfil *micfil;
  554. struct resource *res;
  555. void __iomem *regs;
  556. int ret, i;
  557. unsigned long irqflag = 0;
  558. micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
  559. if (!micfil)
  560. return -ENOMEM;
  561. micfil->pdev = pdev;
  562. strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
  563. of_id = of_match_device(fsl_micfil_dt_ids, &pdev->dev);
  564. if (!of_id || !of_id->data)
  565. return -EINVAL;
  566. micfil->soc = of_id->data;
  567. /* ipg_clk is used to control the registers
  568. * ipg_clk_app is used to operate the filter
  569. */
  570. micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
  571. if (IS_ERR(micfil->mclk)) {
  572. dev_err(&pdev->dev, "failed to get core clock: %ld\n",
  573. PTR_ERR(micfil->mclk));
  574. return PTR_ERR(micfil->mclk);
  575. }
  576. /* init regmap */
  577. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  578. regs = devm_ioremap_resource(&pdev->dev, res);
  579. if (IS_ERR(regs))
  580. return PTR_ERR(regs);
  581. micfil->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
  582. "ipg_clk",
  583. regs,
  584. &fsl_micfil_regmap_config);
  585. if (IS_ERR(micfil->regmap)) {
  586. dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
  587. PTR_ERR(micfil->regmap));
  588. return PTR_ERR(micfil->regmap);
  589. }
  590. /* dataline mask for RX */
  591. ret = of_property_read_u32_index(np,
  592. "fsl,dataline",
  593. 0,
  594. &micfil->dataline);
  595. if (ret)
  596. micfil->dataline = 1;
  597. if (micfil->dataline & ~micfil->soc->dataline) {
  598. dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
  599. micfil->soc->dataline);
  600. return -EINVAL;
  601. }
  602. /* get IRQs */
  603. for (i = 0; i < MICFIL_IRQ_LINES; i++) {
  604. micfil->irq[i] = platform_get_irq(pdev, i);
  605. dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
  606. if (micfil->irq[i] < 0)
  607. return micfil->irq[i];
  608. }
  609. if (of_property_read_bool(np, "fsl,shared-interrupt"))
  610. irqflag = IRQF_SHARED;
  611. /* Digital Microphone interface interrupt */
  612. ret = devm_request_irq(&pdev->dev, micfil->irq[0],
  613. micfil_isr, irqflag,
  614. micfil->name, micfil);
  615. if (ret) {
  616. dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
  617. micfil->irq[0]);
  618. return ret;
  619. }
  620. /* Digital Microphone interface error interrupt */
  621. ret = devm_request_irq(&pdev->dev, micfil->irq[1],
  622. micfil_err_isr, irqflag,
  623. micfil->name, micfil);
  624. if (ret) {
  625. dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
  626. micfil->irq[1]);
  627. return ret;
  628. }
  629. micfil->dma_params_rx.chan_name = "rx";
  630. micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
  631. micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
  632. platform_set_drvdata(pdev, micfil);
  633. pm_runtime_enable(&pdev->dev);
  634. ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
  635. &fsl_micfil_dai, 1);
  636. if (ret) {
  637. dev_err(&pdev->dev, "failed to register component %s\n",
  638. fsl_micfil_component.name);
  639. return ret;
  640. }
  641. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  642. if (ret)
  643. dev_err(&pdev->dev, "failed to pcm register\n");
  644. return ret;
  645. }
  646. static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
  647. {
  648. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  649. regcache_cache_only(micfil->regmap, true);
  650. clk_disable_unprepare(micfil->mclk);
  651. return 0;
  652. }
  653. static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
  654. {
  655. struct fsl_micfil *micfil = dev_get_drvdata(dev);
  656. int ret;
  657. ret = clk_prepare_enable(micfil->mclk);
  658. if (ret < 0)
  659. return ret;
  660. regcache_cache_only(micfil->regmap, false);
  661. regcache_mark_dirty(micfil->regmap);
  662. regcache_sync(micfil->regmap);
  663. return 0;
  664. }
  665. static int __maybe_unused fsl_micfil_suspend(struct device *dev)
  666. {
  667. pm_runtime_force_suspend(dev);
  668. return 0;
  669. }
  670. static int __maybe_unused fsl_micfil_resume(struct device *dev)
  671. {
  672. pm_runtime_force_resume(dev);
  673. return 0;
  674. }
  675. static const struct dev_pm_ops fsl_micfil_pm_ops = {
  676. SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
  677. fsl_micfil_runtime_resume,
  678. NULL)
  679. SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
  680. fsl_micfil_resume)
  681. };
  682. static struct platform_driver fsl_micfil_driver = {
  683. .probe = fsl_micfil_probe,
  684. .driver = {
  685. .name = "fsl-micfil-dai",
  686. .pm = &fsl_micfil_pm_ops,
  687. .of_match_table = fsl_micfil_dt_ids,
  688. },
  689. };
  690. module_platform_driver(fsl_micfil_driver);
  691. MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
  692. MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
  693. MODULE_LICENSE("GPL v2");