fsl_easrc.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2019 NXP
  4. */
  5. #ifndef _FSL_EASRC_H
  6. #define _FSL_EASRC_H
  7. #include <sound/asound.h>
  8. #include <linux/platform_data/dma-imx.h>
  9. #include "fsl_asrc_common.h"
  10. /* EASRC Register Map */
  11. /* ASRC Input Write FIFO */
  12. #define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
  13. /* ASRC Output Read FIFO */
  14. #define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
  15. /* ASRC Context Control */
  16. #define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
  17. /* ASRC Context Control Extended 1 */
  18. #define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
  19. /* ASRC Context Control Extended 2 */
  20. #define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
  21. /* ASRC Control Input Access */
  22. #define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
  23. /* ASRC Datapath Processor Control Slot0 */
  24. #define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
  25. #define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
  26. #define REG_EASRC_DPCS0R2(ctx) (0x080 + 4 * (ctx))
  27. #define REG_EASRC_DPCS0R3(ctx) (0x090 + 4 * (ctx))
  28. /* ASRC Datapath Processor Control Slot1 */
  29. #define REG_EASRC_DPCS1R0(ctx) (0x0A0 + 4 * (ctx))
  30. #define REG_EASRC_DPCS1R1(ctx) (0x0B0 + 4 * (ctx))
  31. #define REG_EASRC_DPCS1R2(ctx) (0x0C0 + 4 * (ctx))
  32. #define REG_EASRC_DPCS1R3(ctx) (0x0D0 + 4 * (ctx))
  33. /* ASRC Context Output Control */
  34. #define REG_EASRC_COC(ctx) (0x0E0 + 4 * (ctx))
  35. /* ASRC Control Output Access */
  36. #define REG_EASRC_COA(ctx) (0x0F0 + 4 * (ctx))
  37. /* ASRC Sample FIFO Status */
  38. #define REG_EASRC_SFS(ctx) (0x100 + 4 * (ctx))
  39. /* ASRC Resampling Ratio Low */
  40. #define REG_EASRC_RRL(ctx) (0x110 + 8 * (ctx))
  41. /* ASRC Resampling Ratio High */
  42. #define REG_EASRC_RRH(ctx) (0x114 + 8 * (ctx))
  43. /* ASRC Resampling Ratio Update Control */
  44. #define REG_EASRC_RUC(ctx) (0x130 + 4 * (ctx))
  45. /* ASRC Resampling Ratio Update Rate */
  46. #define REG_EASRC_RUR(ctx) (0x140 + 4 * (ctx))
  47. /* ASRC Resampling Center Tap Coefficient Low */
  48. #define REG_EASRC_RCTCL (0x150)
  49. /* ASRC Resampling Center Tap Coefficient High */
  50. #define REG_EASRC_RCTCH (0x154)
  51. /* ASRC Prefilter Coefficient FIFO */
  52. #define REG_EASRC_PCF(ctx) (0x160 + 4 * (ctx))
  53. /* ASRC Context Resampling Coefficient Memory */
  54. #define REG_EASRC_CRCM 0x170
  55. /* ASRC Context Resampling Coefficient Control*/
  56. #define REG_EASRC_CRCC 0x174
  57. /* ASRC Interrupt Control */
  58. #define REG_EASRC_IRQC 0x178
  59. /* ASRC Interrupt Status Flags */
  60. #define REG_EASRC_IRQF 0x17C
  61. /* ASRC Channel Status 0 */
  62. #define REG_EASRC_CS0(ctx) (0x180 + 4 * (ctx))
  63. /* ASRC Channel Status 1 */
  64. #define REG_EASRC_CS1(ctx) (0x190 + 4 * (ctx))
  65. /* ASRC Channel Status 2 */
  66. #define REG_EASRC_CS2(ctx) (0x1A0 + 4 * (ctx))
  67. /* ASRC Channel Status 3 */
  68. #define REG_EASRC_CS3(ctx) (0x1B0 + 4 * (ctx))
  69. /* ASRC Channel Status 4 */
  70. #define REG_EASRC_CS4(ctx) (0x1C0 + 4 * (ctx))
  71. /* ASRC Channel Status 5 */
  72. #define REG_EASRC_CS5(ctx) (0x1D0 + 4 * (ctx))
  73. /* ASRC Debug Control Register */
  74. #define REG_EASRC_DBGC 0x1E0
  75. /* ASRC Debug Status Register */
  76. #define REG_EASRC_DBGS 0x1E4
  77. #define REG_EASRC_FIFO(x, ctx) (x == IN ? REG_EASRC_WRFIFO(ctx) \
  78. : REG_EASRC_RDFIFO(ctx))
  79. /* ASRC Context Control (CC) */
  80. #define EASRC_CC_EN_SHIFT 31
  81. #define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
  82. #define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
  83. #define EASRC_CC_STOP_SHIFT 29
  84. #define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
  85. #define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
  86. #define EASRC_CC_FWMDE_SHIFT 28
  87. #define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
  88. #define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
  89. #define EASRC_CC_FIFO_WTMK_SHIFT 16
  90. #define EASRC_CC_FIFO_WTMK_WIDTH 7
  91. #define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
  92. << EASRC_CC_FIFO_WTMK_SHIFT)
  93. #define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \
  94. & EASRC_CC_FIFO_WTMK_MASK)
  95. #define EASRC_CC_SAMPLE_POS_SHIFT 11
  96. #define EASRC_CC_SAMPLE_POS_WIDTH 5
  97. #define EASRC_CC_SAMPLE_POS_MASK ((BIT(EASRC_CC_SAMPLE_POS_WIDTH) - 1) \
  98. << EASRC_CC_SAMPLE_POS_SHIFT)
  99. #define EASRC_CC_SAMPLE_POS(v) (((v) << EASRC_CC_SAMPLE_POS_SHIFT) \
  100. & EASRC_CC_SAMPLE_POS_MASK)
  101. #define EASRC_CC_ENDIANNESS_SHIFT 10
  102. #define EASRC_CC_ENDIANNESS_MASK BIT(EASRC_CC_ENDIANNESS_SHIFT)
  103. #define EASRC_CC_ENDIANNESS BIT(EASRC_CC_ENDIANNESS_SHIFT)
  104. #define EASRC_CC_BPS_SHIFT 8
  105. #define EASRC_CC_BPS_WIDTH 2
  106. #define EASRC_CC_BPS_MASK ((BIT(EASRC_CC_BPS_WIDTH) - 1) \
  107. << EASRC_CC_BPS_SHIFT)
  108. #define EASRC_CC_BPS(v) (((v) << EASRC_CC_BPS_SHIFT) \
  109. & EASRC_CC_BPS_MASK)
  110. #define EASRC_CC_FMT_SHIFT 7
  111. #define EASRC_CC_FMT_MASK BIT(EASRC_CC_FMT_SHIFT)
  112. #define EASRC_CC_FMT BIT(EASRC_CC_FMT_SHIFT)
  113. #define EASRC_CC_INSIGN_SHIFT 6
  114. #define EASRC_CC_INSIGN_MASK BIT(EASRC_CC_INSIGN_SHIFT)
  115. #define EASRC_CC_INSIGN BIT(EASRC_CC_INSIGN_SHIFT)
  116. #define EASRC_CC_CHEN_SHIFT 0
  117. #define EASRC_CC_CHEN_WIDTH 5
  118. #define EASRC_CC_CHEN_MASK ((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
  119. << EASRC_CC_CHEN_SHIFT)
  120. #define EASRC_CC_CHEN(v) (((v) << EASRC_CC_CHEN_SHIFT) \
  121. & EASRC_CC_CHEN_MASK)
  122. /* ASRC Context Control Extended 1 (CCE1) */
  123. #define EASRC_CCE1_COEF_WS_SHIFT 25
  124. #define EASRC_CCE1_COEF_WS_MASK BIT(EASRC_CCE1_COEF_WS_SHIFT)
  125. #define EASRC_CCE1_COEF_WS BIT(EASRC_CCE1_COEF_WS_SHIFT)
  126. #define EASRC_CCE1_COEF_MEM_RST_SHIFT 24
  127. #define EASRC_CCE1_COEF_MEM_RST_MASK BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
  128. #define EASRC_CCE1_COEF_MEM_RST BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
  129. #define EASRC_CCE1_PF_EXP_SHIFT 16
  130. #define EASRC_CCE1_PF_EXP_WIDTH 8
  131. #define EASRC_CCE1_PF_EXP_MASK ((BIT(EASRC_CCE1_PF_EXP_WIDTH) - 1) \
  132. << EASRC_CCE1_PF_EXP_SHIFT)
  133. #define EASRC_CCE1_PF_EXP(v) (((v) << EASRC_CCE1_PF_EXP_SHIFT) \
  134. & EASRC_CCE1_PF_EXP_MASK)
  135. #define EASRC_CCE1_PF_ST1_WBFP_SHIFT 9
  136. #define EASRC_CCE1_PF_ST1_WBFP_MASK BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
  137. #define EASRC_CCE1_PF_ST1_WBFP BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
  138. #define EASRC_CCE1_PF_TSEN_SHIFT 8
  139. #define EASRC_CCE1_PF_TSEN_MASK BIT(EASRC_CCE1_PF_TSEN_SHIFT)
  140. #define EASRC_CCE1_PF_TSEN BIT(EASRC_CCE1_PF_TSEN_SHIFT)
  141. #define EASRC_CCE1_RS_BYPASS_SHIFT 7
  142. #define EASRC_CCE1_RS_BYPASS_MASK BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
  143. #define EASRC_CCE1_RS_BYPASS BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
  144. #define EASRC_CCE1_PF_BYPASS_SHIFT 6
  145. #define EASRC_CCE1_PF_BYPASS_MASK BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
  146. #define EASRC_CCE1_PF_BYPASS BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
  147. #define EASRC_CCE1_RS_STOP_SHIFT 5
  148. #define EASRC_CCE1_RS_STOP_MASK BIT(EASRC_CCE1_RS_STOP_SHIFT)
  149. #define EASRC_CCE1_RS_STOP BIT(EASRC_CCE1_RS_STOP_SHIFT)
  150. #define EASRC_CCE1_PF_STOP_SHIFT 4
  151. #define EASRC_CCE1_PF_STOP_MASK BIT(EASRC_CCE1_PF_STOP_SHIFT)
  152. #define EASRC_CCE1_PF_STOP BIT(EASRC_CCE1_PF_STOP_SHIFT)
  153. #define EASRC_CCE1_RS_INIT_SHIFT 2
  154. #define EASRC_CCE1_RS_INIT_WIDTH 2
  155. #define EASRC_CCE1_RS_INIT_MASK ((BIT(EASRC_CCE1_RS_INIT_WIDTH) - 1) \
  156. << EASRC_CCE1_RS_INIT_SHIFT)
  157. #define EASRC_CCE1_RS_INIT(v) (((v) << EASRC_CCE1_RS_INIT_SHIFT) \
  158. & EASRC_CCE1_RS_INIT_MASK)
  159. #define EASRC_CCE1_PF_INIT_SHIFT 0
  160. #define EASRC_CCE1_PF_INIT_WIDTH 2
  161. #define EASRC_CCE1_PF_INIT_MASK ((BIT(EASRC_CCE1_PF_INIT_WIDTH) - 1) \
  162. << EASRC_CCE1_PF_INIT_SHIFT)
  163. #define EASRC_CCE1_PF_INIT(v) (((v) << EASRC_CCE1_PF_INIT_SHIFT) \
  164. & EASRC_CCE1_PF_INIT_MASK)
  165. /* ASRC Context Control Extended 2 (CCE2) */
  166. #define EASRC_CCE2_ST2_TAPS_SHIFT 16
  167. #define EASRC_CCE2_ST2_TAPS_WIDTH 9
  168. #define EASRC_CCE2_ST2_TAPS_MASK ((BIT(EASRC_CCE2_ST2_TAPS_WIDTH) - 1) \
  169. << EASRC_CCE2_ST2_TAPS_SHIFT)
  170. #define EASRC_CCE2_ST2_TAPS(v) (((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \
  171. & EASRC_CCE2_ST2_TAPS_MASK)
  172. #define EASRC_CCE2_ST1_TAPS_SHIFT 0
  173. #define EASRC_CCE2_ST1_TAPS_WIDTH 9
  174. #define EASRC_CCE2_ST1_TAPS_MASK ((BIT(EASRC_CCE2_ST1_TAPS_WIDTH) - 1) \
  175. << EASRC_CCE2_ST1_TAPS_SHIFT)
  176. #define EASRC_CCE2_ST1_TAPS(v) (((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \
  177. & EASRC_CCE2_ST1_TAPS_MASK)
  178. /* ASRC Control Input Access (CIA) */
  179. #define EASRC_CIA_ITER_SHIFT 16
  180. #define EASRC_CIA_ITER_WIDTH 6
  181. #define EASRC_CIA_ITER_MASK ((BIT(EASRC_CIA_ITER_WIDTH) - 1) \
  182. << EASRC_CIA_ITER_SHIFT)
  183. #define EASRC_CIA_ITER(v) (((v) << EASRC_CIA_ITER_SHIFT) \
  184. & EASRC_CIA_ITER_MASK)
  185. #define EASRC_CIA_GRLEN_SHIFT 8
  186. #define EASRC_CIA_GRLEN_WIDTH 6
  187. #define EASRC_CIA_GRLEN_MASK ((BIT(EASRC_CIA_GRLEN_WIDTH) - 1) \
  188. << EASRC_CIA_GRLEN_SHIFT)
  189. #define EASRC_CIA_GRLEN(v) (((v) << EASRC_CIA_GRLEN_SHIFT) \
  190. & EASRC_CIA_GRLEN_MASK)
  191. #define EASRC_CIA_ACCLEN_SHIFT 0
  192. #define EASRC_CIA_ACCLEN_WIDTH 6
  193. #define EASRC_CIA_ACCLEN_MASK ((BIT(EASRC_CIA_ACCLEN_WIDTH) - 1) \
  194. << EASRC_CIA_ACCLEN_SHIFT)
  195. #define EASRC_CIA_ACCLEN(v) (((v) << EASRC_CIA_ACCLEN_SHIFT) \
  196. & EASRC_CIA_ACCLEN_MASK)
  197. /* ASRC Datapath Processor Control Slot0 Register0 (DPCS0R0) */
  198. #define EASRC_DPCS0R0_MAXCH_SHIFT 24
  199. #define EASRC_DPCS0R0_MAXCH_WIDTH 5
  200. #define EASRC_DPCS0R0_MAXCH_MASK ((BIT(EASRC_DPCS0R0_MAXCH_WIDTH) - 1) \
  201. << EASRC_DPCS0R0_MAXCH_SHIFT)
  202. #define EASRC_DPCS0R0_MAXCH(v) (((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \
  203. & EASRC_DPCS0R0_MAXCH_MASK)
  204. #define EASRC_DPCS0R0_MINCH_SHIFT 16
  205. #define EASRC_DPCS0R0_MINCH_WIDTH 5
  206. #define EASRC_DPCS0R0_MINCH_MASK ((BIT(EASRC_DPCS0R0_MINCH_WIDTH) - 1) \
  207. << EASRC_DPCS0R0_MINCH_SHIFT)
  208. #define EASRC_DPCS0R0_MINCH(v) (((v) << EASRC_DPCS0R0_MINCH_SHIFT) \
  209. & EASRC_DPCS0R0_MINCH_MASK)
  210. #define EASRC_DPCS0R0_NUMCH_SHIFT 8
  211. #define EASRC_DPCS0R0_NUMCH_WIDTH 5
  212. #define EASRC_DPCS0R0_NUMCH_MASK ((BIT(EASRC_DPCS0R0_NUMCH_WIDTH) - 1) \
  213. << EASRC_DPCS0R0_NUMCH_SHIFT)
  214. #define EASRC_DPCS0R0_NUMCH(v) (((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \
  215. & EASRC_DPCS0R0_NUMCH_MASK)
  216. #define EASRC_DPCS0R0_CTXNUM_SHIFT 1
  217. #define EASRC_DPCS0R0_CTXNUM_WIDTH 2
  218. #define EASRC_DPCS0R0_CTXNUM_MASK ((BIT(EASRC_DPCS0R0_CTXNUM_WIDTH) - 1) \
  219. << EASRC_DPCS0R0_CTXNUM_SHIFT)
  220. #define EASRC_DPCS0R0_CTXNUM(v) (((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \
  221. & EASRC_DPCS0R0_CTXNUM_MASK)
  222. #define EASRC_DPCS0R0_EN_SHIFT 0
  223. #define EASRC_DPCS0R0_EN_MASK BIT(EASRC_DPCS0R0_EN_SHIFT)
  224. #define EASRC_DPCS0R0_EN BIT(EASRC_DPCS0R0_EN_SHIFT)
  225. /* ASRC Datapath Processor Control Slot0 Register1 (DPCS0R1) */
  226. #define EASRC_DPCS0R1_ST1_EXP_SHIFT 0
  227. #define EASRC_DPCS0R1_ST1_EXP_WIDTH 13
  228. #define EASRC_DPCS0R1_ST1_EXP_MASK ((BIT(EASRC_DPCS0R1_ST1_EXP_WIDTH) - 1) \
  229. << EASRC_DPCS0R1_ST1_EXP_SHIFT)
  230. #define EASRC_DPCS0R1_ST1_EXP(v) (((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \
  231. & EASRC_DPCS0R1_ST1_EXP_MASK)
  232. /* ASRC Datapath Processor Control Slot0 Register2 (DPCS0R2) */
  233. #define EASRC_DPCS0R2_ST1_MA_SHIFT 16
  234. #define EASRC_DPCS0R2_ST1_MA_WIDTH 13
  235. #define EASRC_DPCS0R2_ST1_MA_MASK ((BIT(EASRC_DPCS0R2_ST1_MA_WIDTH) - 1) \
  236. << EASRC_DPCS0R2_ST1_MA_SHIFT)
  237. #define EASRC_DPCS0R2_ST1_MA(v) (((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \
  238. & EASRC_DPCS0R2_ST1_MA_MASK)
  239. #define EASRC_DPCS0R2_ST1_SA_SHIFT 0
  240. #define EASRC_DPCS0R2_ST1_SA_WIDTH 13
  241. #define EASRC_DPCS0R2_ST1_SA_MASK ((BIT(EASRC_DPCS0R2_ST1_SA_WIDTH) - 1) \
  242. << EASRC_DPCS0R2_ST1_SA_SHIFT)
  243. #define EASRC_DPCS0R2_ST1_SA(v) (((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \
  244. & EASRC_DPCS0R2_ST1_SA_MASK)
  245. /* ASRC Datapath Processor Control Slot0 Register3 (DPCS0R3) */
  246. #define EASRC_DPCS0R3_ST2_MA_SHIFT 16
  247. #define EASRC_DPCS0R3_ST2_MA_WIDTH 13
  248. #define EASRC_DPCS0R3_ST2_MA_MASK ((BIT(EASRC_DPCS0R3_ST2_MA_WIDTH) - 1) \
  249. << EASRC_DPCS0R3_ST2_MA_SHIFT)
  250. #define EASRC_DPCS0R3_ST2_MA(v) (((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \
  251. & EASRC_DPCS0R3_ST2_MA_MASK)
  252. #define EASRC_DPCS0R3_ST2_SA_SHIFT 0
  253. #define EASRC_DPCS0R3_ST2_SA_WIDTH 13
  254. #define EASRC_DPCS0R3_ST2_SA_MASK ((BIT(EASRC_DPCS0R3_ST2_SA_WIDTH) - 1) \
  255. << EASRC_DPCS0R3_ST2_SA_SHIFT)
  256. #define EASRC_DPCS0R3_ST2_SA(v) (((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \
  257. & EASRC_DPCS0R3_ST2_SA_MASK)
  258. /* ASRC Context Output Control (COC) */
  259. #define EASRC_COC_FWMDE_SHIFT 28
  260. #define EASRC_COC_FWMDE_MASK BIT(EASRC_COC_FWMDE_SHIFT)
  261. #define EASRC_COC_FWMDE BIT(EASRC_COC_FWMDE_SHIFT)
  262. #define EASRC_COC_FIFO_WTMK_SHIFT 16
  263. #define EASRC_COC_FIFO_WTMK_WIDTH 7
  264. #define EASRC_COC_FIFO_WTMK_MASK ((BIT(EASRC_COC_FIFO_WTMK_WIDTH) - 1) \
  265. << EASRC_COC_FIFO_WTMK_SHIFT)
  266. #define EASRC_COC_FIFO_WTMK(v) (((v) << EASRC_COC_FIFO_WTMK_SHIFT) \
  267. & EASRC_COC_FIFO_WTMK_MASK)
  268. #define EASRC_COC_SAMPLE_POS_SHIFT 11
  269. #define EASRC_COC_SAMPLE_POS_WIDTH 5
  270. #define EASRC_COC_SAMPLE_POS_MASK ((BIT(EASRC_COC_SAMPLE_POS_WIDTH) - 1) \
  271. << EASRC_COC_SAMPLE_POS_SHIFT)
  272. #define EASRC_COC_SAMPLE_POS(v) (((v) << EASRC_COC_SAMPLE_POS_SHIFT) \
  273. & EASRC_COC_SAMPLE_POS_MASK)
  274. #define EASRC_COC_ENDIANNESS_SHIFT 10
  275. #define EASRC_COC_ENDIANNESS_MASK BIT(EASRC_COC_ENDIANNESS_SHIFT)
  276. #define EASRC_COC_ENDIANNESS BIT(EASRC_COC_ENDIANNESS_SHIFT)
  277. #define EASRC_COC_BPS_SHIFT 8
  278. #define EASRC_COC_BPS_WIDTH 2
  279. #define EASRC_COC_BPS_MASK ((BIT(EASRC_COC_BPS_WIDTH) - 1) \
  280. << EASRC_COC_BPS_SHIFT)
  281. #define EASRC_COC_BPS(v) (((v) << EASRC_COC_BPS_SHIFT) \
  282. & EASRC_COC_BPS_MASK)
  283. #define EASRC_COC_FMT_SHIFT 7
  284. #define EASRC_COC_FMT_MASK BIT(EASRC_COC_FMT_SHIFT)
  285. #define EASRC_COC_FMT BIT(EASRC_COC_FMT_SHIFT)
  286. #define EASRC_COC_OUTSIGN_SHIFT 6
  287. #define EASRC_COC_OUTSIGN_MASK BIT(EASRC_COC_OUTSIGN_SHIFT)
  288. #define EASRC_COC_OUTSIGN_OUT BIT(EASRC_COC_OUTSIGN_SHIFT)
  289. #define EASRC_COC_IEC_VDATA_SHIFT 2
  290. #define EASRC_COC_IEC_VDATA_MASK BIT(EASRC_COC_IEC_VDATA_SHIFT)
  291. #define EASRC_COC_IEC_VDATA BIT(EASRC_COC_IEC_VDATA_SHIFT)
  292. #define EASRC_COC_IEC_EN_SHIFT 1
  293. #define EASRC_COC_IEC_EN_MASK BIT(EASRC_COC_IEC_EN_SHIFT)
  294. #define EASRC_COC_IEC_EN BIT(EASRC_COC_IEC_EN_SHIFT)
  295. #define EASRC_COC_DITHER_EN_SHIFT 0
  296. #define EASRC_COC_DITHER_EN_MASK BIT(EASRC_COC_DITHER_EN_SHIFT)
  297. #define EASRC_COC_DITHER_EN BIT(EASRC_COC_DITHER_EN_SHIFT)
  298. /* ASRC Control Output Access (COA) */
  299. #define EASRC_COA_ITER_SHIFT 16
  300. #define EASRC_COA_ITER_WIDTH 6
  301. #define EASRC_COA_ITER_MASK ((BIT(EASRC_COA_ITER_WIDTH) - 1) \
  302. << EASRC_COA_ITER_SHIFT)
  303. #define EASRC_COA_ITER(v) (((v) << EASRC_COA_ITER_SHIFT) \
  304. & EASRC_COA_ITER_MASK)
  305. #define EASRC_COA_GRLEN_SHIFT 8
  306. #define EASRC_COA_GRLEN_WIDTH 6
  307. #define EASRC_COA_GRLEN_MASK ((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
  308. << EASRC_COA_GRLEN_SHIFT)
  309. #define EASRC_COA_GRLEN(v) (((v) << EASRC_COA_GRLEN_SHIFT) \
  310. & EASRC_COA_GRLEN_MASK)
  311. #define EASRC_COA_ACCLEN_SHIFT 0
  312. #define EASRC_COA_ACCLEN_WIDTH 6
  313. #define EASRC_COA_ACCLEN_MASK ((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
  314. << EASRC_COA_ACCLEN_SHIFT)
  315. #define EASRC_COA_ACCLEN(v) (((v) << EASRC_COA_ACCLEN_SHIFT) \
  316. & EASRC_COA_ACCLEN_MASK)
  317. /* ASRC Sample FIFO Status (SFS) */
  318. #define EASRC_SFS_IWTMK_SHIFT 23
  319. #define EASRC_SFS_IWTMK_MASK BIT(EASRC_SFS_IWTMK_SHIFT)
  320. #define EASRC_SFS_IWTMK BIT(EASRC_SFS_IWTMK_SHIFT)
  321. #define EASRC_SFS_NSGI_SHIFT 16
  322. #define EASRC_SFS_NSGI_WIDTH 7
  323. #define EASRC_SFS_NSGI_MASK ((BIT(EASRC_SFS_NSGI_WIDTH) - 1) \
  324. << EASRC_SFS_NSGI_SHIFT)
  325. #define EASRC_SFS_NSGI(v) (((v) << EASRC_SFS_NSGI_SHIFT) \
  326. & EASRC_SFS_NSGI_MASK)
  327. #define EASRC_SFS_OWTMK_SHIFT 7
  328. #define EASRC_SFS_OWTMK_MASK BIT(EASRC_SFS_OWTMK_SHIFT)
  329. #define EASRC_SFS_OWTMK BIT(EASRC_SFS_OWTMK_SHIFT)
  330. #define EASRC_SFS_NSGO_SHIFT 0
  331. #define EASRC_SFS_NSGO_WIDTH 7
  332. #define EASRC_SFS_NSGO_MASK ((BIT(EASRC_SFS_NSGO_WIDTH) - 1) \
  333. << EASRC_SFS_NSGO_SHIFT)
  334. #define EASRC_SFS_NSGO(v) (((v) << EASRC_SFS_NSGO_SHIFT) \
  335. & EASRC_SFS_NSGO_MASK)
  336. /* ASRC Resampling Ratio Low (RRL) */
  337. #define EASRC_RRL_RS_RL_SHIFT 0
  338. #define EASRC_RRL_RS_RL_WIDTH 32
  339. #define EASRC_RRL_RS_RL(v) ((v) << EASRC_RRL_RS_RL_SHIFT)
  340. /* ASRC Resampling Ratio High (RRH) */
  341. #define EASRC_RRH_RS_VLD_SHIFT 31
  342. #define EASRC_RRH_RS_VLD_MASK BIT(EASRC_RRH_RS_VLD_SHIFT)
  343. #define EASRC_RRH_RS_VLD BIT(EASRC_RRH_RS_VLD_SHIFT)
  344. #define EASRC_RRH_RS_RH_SHIFT 0
  345. #define EASRC_RRH_RS_RH_WIDTH 12
  346. #define EASRC_RRH_RS_RH_MASK ((BIT(EASRC_RRH_RS_RH_WIDTH) - 1) \
  347. << EASRC_RRH_RS_RH_SHIFT)
  348. #define EASRC_RRH_RS_RH(v) (((v) << EASRC_RRH_RS_RH_SHIFT) \
  349. & EASRC_RRH_RS_RH_MASK)
  350. /* ASRC Resampling Ratio Update Control (RSUC) */
  351. #define EASRC_RSUC_RS_RM_SHIFT 0
  352. #define EASRC_RSUC_RS_RM_WIDTH 32
  353. #define EASRC_RSUC_RS_RM(v) ((v) << EASRC_RSUC_RS_RM_SHIFT)
  354. /* ASRC Resampling Ratio Update Rate (RRUR) */
  355. #define EASRC_RRUR_RRR_SHIFT 0
  356. #define EASRC_RRUR_RRR_WIDTH 31
  357. #define EASRC_RRUR_RRR_MASK ((BIT(EASRC_RRUR_RRR_WIDTH) - 1) \
  358. << EASRC_RRUR_RRR_SHIFT)
  359. #define EASRC_RRUR_RRR(v) (((v) << EASRC_RRUR_RRR_SHIFT) \
  360. & EASRC_RRUR_RRR_MASK)
  361. /* ASRC Resampling Center Tap Coefficient Low (RCTCL) */
  362. #define EASRC_RCTCL_RS_CL_SHIFT 0
  363. #define EASRC_RCTCL_RS_CL_WIDTH 32
  364. #define EASRC_RCTCL_RS_CL(v) ((v) << EASRC_RCTCL_RS_CL_SHIFT)
  365. /* ASRC Resampling Center Tap Coefficient High (RCTCH) */
  366. #define EASRC_RCTCH_RS_CH_SHIFT 0
  367. #define EASRC_RCTCH_RS_CH_WIDTH 32
  368. #define EASRC_RCTCH_RS_CH(v) ((v) << EASRC_RCTCH_RS_CH_SHIFT)
  369. /* ASRC Prefilter Coefficient FIFO (PCF) */
  370. #define EASRC_PCF_CD_SHIFT 0
  371. #define EASRC_PCF_CD_WIDTH 32
  372. #define EASRC_PCF_CD(v) ((v) << EASRC_PCF_CD_SHIFT)
  373. /* ASRC Context Resampling Coefficient Memory (CRCM) */
  374. #define EASRC_CRCM_RS_CWD_SHIFT 0
  375. #define EASRC_CRCM_RS_CWD_WIDTH 32
  376. #define EASRC_CRCM_RS_CWD(v) ((v) << EASRC_CRCM_RS_CWD_SHIFT)
  377. /* ASRC Context Resampling Coefficient Control (CRCC) */
  378. #define EASRC_CRCC_RS_CA_SHIFT 16
  379. #define EASRC_CRCC_RS_CA_WIDTH 11
  380. #define EASRC_CRCC_RS_CA_MASK ((BIT(EASRC_CRCC_RS_CA_WIDTH) - 1) \
  381. << EASRC_CRCC_RS_CA_SHIFT)
  382. #define EASRC_CRCC_RS_CA(v) (((v) << EASRC_CRCC_RS_CA_SHIFT) \
  383. & EASRC_CRCC_RS_CA_MASK)
  384. #define EASRC_CRCC_RS_TAPS_SHIFT 1
  385. #define EASRC_CRCC_RS_TAPS_WIDTH 2
  386. #define EASRC_CRCC_RS_TAPS_MASK ((BIT(EASRC_CRCC_RS_TAPS_WIDTH) - 1) \
  387. << EASRC_CRCC_RS_TAPS_SHIFT)
  388. #define EASRC_CRCC_RS_TAPS(v) (((v) << EASRC_CRCC_RS_TAPS_SHIFT) \
  389. & EASRC_CRCC_RS_TAPS_MASK)
  390. #define EASRC_CRCC_RS_CPR_SHIFT 0
  391. #define EASRC_CRCC_RS_CPR_MASK BIT(EASRC_CRCC_RS_CPR_SHIFT)
  392. #define EASRC_CRCC_RS_CPR BIT(EASRC_CRCC_RS_CPR_SHIFT)
  393. /* ASRC Interrupt_Control (IC) */
  394. #define EASRC_IRQC_RSDM_SHIFT 8
  395. #define EASRC_IRQC_RSDM_WIDTH 4
  396. #define EASRC_IRQC_RSDM_MASK ((BIT(EASRC_IRQC_RSDM_WIDTH) - 1) \
  397. << EASRC_IRQC_RSDM_SHIFT)
  398. #define EASRC_IRQC_RSDM(v) (((v) << EASRC_IRQC_RSDM_SHIFT) \
  399. & EASRC_IRQC_RSDM_MASK)
  400. #define EASRC_IRQC_OERM_SHIFT 4
  401. #define EASRC_IRQC_OERM_WIDTH 4
  402. #define EASRC_IRQC_OERM_MASK ((BIT(EASRC_IRQC_OERM_WIDTH) - 1) \
  403. << EASRC_IRQC_OERM_SHIFT)
  404. #define EASRC_IRQC_OERM(v) (((v) << EASRC_IRQC_OERM_SHIFT) \
  405. & EASRC_IEQC_OERM_MASK)
  406. #define EASRC_IRQC_IOM_SHIFT 0
  407. #define EASRC_IRQC_IOM_WIDTH 4
  408. #define EASRC_IRQC_IOM_MASK ((BIT(EASRC_IRQC_IOM_WIDTH) - 1) \
  409. << EASRC_IRQC_IOM_SHIFT)
  410. #define EASRC_IRQC_IOM(v) (((v) << EASRC_IRQC_IOM_SHIFT) \
  411. & EASRC_IRQC_IOM_MASK)
  412. /* ASRC Interrupt Status Flags (ISF) */
  413. #define EASRC_IRQF_RSD_SHIFT 8
  414. #define EASRC_IRQF_RSD_WIDTH 4
  415. #define EASRC_IRQF_RSD_MASK ((BIT(EASRC_IRQF_RSD_WIDTH) - 1) \
  416. << EASRC_IRQF_RSD_SHIFT)
  417. #define EASRC_IRQF_RSD(v) (((v) << EASRC_IRQF_RSD_SHIFT) \
  418. & EASRC_IRQF_RSD_MASK)
  419. #define EASRC_IRQF_OER_SHIFT 4
  420. #define EASRC_IRQF_OER_WIDTH 4
  421. #define EASRC_IRQF_OER_MASK ((BIT(EASRC_IRQF_OER_WIDTH) - 1) \
  422. << EASRC_IRQF_OER_SHIFT)
  423. #define EASRC_IRQF_OER(v) (((v) << EASRC_IRQF_OER_SHIFT) \
  424. & EASRC_IRQF_OER_MASK)
  425. #define EASRC_IRQF_IFO_SHIFT 0
  426. #define EASRC_IRQF_IFO_WIDTH 4
  427. #define EASRC_IRQF_IFO_MASK ((BIT(EASRC_IRQF_IFO_WIDTH) - 1) \
  428. << EASRC_IRQF_IFO_SHIFT)
  429. #define EASRC_IRQF_IFO(v) (((v) << EASRC_IRQF_IFO_SHIFT) \
  430. & EASRC_IRQF_IFO_MASK)
  431. /* ASRC Context Channel STAT */
  432. #define EASRC_CSx_CSx_SHIFT 0
  433. #define EASRC_CSx_CSx_WIDTH 32
  434. #define EASRC_CSx_CSx(v) ((v) << EASRC_CSx_CSx_SHIFT)
  435. /* ASRC Debug Control Register */
  436. #define EASRC_DBGC_DMS_SHIFT 0
  437. #define EASRC_DBGC_DMS_WIDTH 6
  438. #define EASRC_DBGC_DMS_MASK ((BIT(EASRC_DBGC_DMS_WIDTH) - 1) \
  439. << EASRC_DBGC_DMS_SHIFT)
  440. #define EASRC_DBGC_DMS(v) (((v) << EASRC_DBGC_DMS_SHIFT) \
  441. & EASRC_DBGC_DMS_MASK)
  442. /* ASRC Debug Status Register */
  443. #define EASRC_DBGS_DS_SHIFT 0
  444. #define EASRC_DBGS_DS_WIDTH 32
  445. #define EASRC_DBGS_DS(v) ((v) << EASRC_DBGS_DS_SHIFT)
  446. /* General Constants */
  447. #define EASRC_CTX_MAX_NUM 4
  448. #define EASRC_RS_COEFF_MEM 0
  449. #define EASRC_PF_COEFF_MEM 1
  450. /* Prefilter constants */
  451. #define EASRC_PF_ST1_ONLY 0
  452. #define EASRC_PF_TWO_STAGE_MODE 1
  453. #define EASRC_PF_ST1_COEFF_WR 0
  454. #define EASRC_PF_ST2_COEFF_WR 1
  455. #define EASRC_MAX_PF_TAPS 384
  456. /* Resampling constants */
  457. #define EASRC_RS_32_TAPS 0
  458. #define EASRC_RS_64_TAPS 1
  459. #define EASRC_RS_128_TAPS 2
  460. /* Initialization mode */
  461. #define EASRC_INIT_MODE_SW_CONTROL 0
  462. #define EASRC_INIT_MODE_REPLICATE 1
  463. #define EASRC_INIT_MODE_ZERO_FILL 2
  464. /* FIFO watermarks */
  465. #define FSL_EASRC_INPUTFIFO_WML 0x4
  466. #define FSL_EASRC_OUTPUTFIFO_WML 0x1
  467. #define EASRC_INPUTFIFO_THRESHOLD_MIN 0
  468. #define EASRC_INPUTFIFO_THRESHOLD_MAX 127
  469. #define EASRC_OUTPUTFIFO_THRESHOLD_MIN 0
  470. #define EASRC_OUTPUTFIFO_THRESHOLD_MAX 63
  471. #define EASRC_DMA_BUFFER_SIZE (1024 * 48 * 9)
  472. #define EASRC_MAX_BUFFER_SIZE (1024 * 48)
  473. #define FIRMWARE_MAGIC 0xDEAD
  474. #define FIRMWARE_VERSION 1
  475. #define PREFILTER_MEM_LEN 0x1800
  476. enum easrc_word_width {
  477. EASRC_WIDTH_16_BIT = 0,
  478. EASRC_WIDTH_20_BIT = 1,
  479. EASRC_WIDTH_24_BIT = 2,
  480. EASRC_WIDTH_32_BIT = 3,
  481. };
  482. struct __attribute__((__packed__)) asrc_firmware_hdr {
  483. u32 magic;
  484. u32 interp_scen;
  485. u32 prefil_scen;
  486. u32 firmware_version;
  487. };
  488. struct __attribute__((__packed__)) interp_params {
  489. u32 magic;
  490. u32 num_taps;
  491. u32 num_phases;
  492. u64 center_tap;
  493. u64 coeff[8192];
  494. };
  495. struct __attribute__((__packed__)) prefil_params {
  496. u32 magic;
  497. u32 insr;
  498. u32 outsr;
  499. u32 st1_taps;
  500. u32 st2_taps;
  501. u32 st1_exp;
  502. u64 coeff[256];
  503. };
  504. struct dma_block {
  505. void *dma_vaddr;
  506. unsigned int length;
  507. unsigned int max_buf_size;
  508. };
  509. struct fsl_easrc_data_fmt {
  510. unsigned int width : 2;
  511. unsigned int endianness : 1;
  512. unsigned int unsign : 1;
  513. unsigned int floating_point : 1;
  514. unsigned int iec958: 1;
  515. unsigned int sample_pos: 5;
  516. unsigned int addexp;
  517. };
  518. struct fsl_easrc_io_params {
  519. struct fsl_easrc_data_fmt fmt;
  520. unsigned int group_len;
  521. unsigned int iterations;
  522. unsigned int access_len;
  523. unsigned int fifo_wtmk;
  524. unsigned int sample_rate;
  525. unsigned int sample_format;
  526. unsigned int norm_rate;
  527. };
  528. struct fsl_easrc_slot {
  529. bool busy;
  530. int ctx_index;
  531. int slot_index;
  532. int num_channel; /* maximum is 8 */
  533. int min_channel;
  534. int max_channel;
  535. int pf_mem_used;
  536. };
  537. /**
  538. * fsl_easrc_ctx_priv: EASRC context private data
  539. *
  540. * @in_params: input parameter
  541. * @out_params: output parameter
  542. * @st1_num_taps: tap number of stage 1
  543. * @st2_num_taps: tap number of stage 2
  544. * @st1_num_exp: exponent number of stage 1
  545. * @pf_init_mode: prefilter init mode
  546. * @rs_init_mode: resample filter init mode
  547. * @ctx_streams: stream flag of ctx
  548. * @rs_ratio: resampler ratio
  549. * @st1_coeff: pointer of stage 1 coeff
  550. * @st2_coeff: pointer of stage 2 coeff
  551. * @in_filled_sample: input filled sample
  552. * @out_missed_sample: sample missed in output
  553. * @st1_addexp: exponent added for stage1
  554. * @st2_addexp: exponent added for stage2
  555. */
  556. struct fsl_easrc_ctx_priv {
  557. struct fsl_easrc_io_params in_params;
  558. struct fsl_easrc_io_params out_params;
  559. unsigned int st1_num_taps;
  560. unsigned int st2_num_taps;
  561. unsigned int st1_num_exp;
  562. unsigned int pf_init_mode;
  563. unsigned int rs_init_mode;
  564. unsigned int ctx_streams;
  565. u64 rs_ratio;
  566. u64 *st1_coeff;
  567. u64 *st2_coeff;
  568. int in_filled_sample;
  569. int out_missed_sample;
  570. int st1_addexp;
  571. int st2_addexp;
  572. };
  573. /**
  574. * fsl_easrc_priv: EASRC private data
  575. *
  576. * @slot: slot setting
  577. * @firmware_hdr: the header of firmware
  578. * @interp: pointer to interpolation filter coeff
  579. * @prefil: pointer to prefilter coeff
  580. * @fw: firmware of coeff table
  581. * @fw_name: firmware name
  582. * @rs_num_taps: resample filter taps, 32, 64, or 128
  583. * @bps_iec958: bits per sample of iec958
  584. * @rs_coeff: resampler coefficient
  585. * @const_coeff: one tap prefilter coefficient
  586. * @firmware_loaded: firmware is loaded
  587. */
  588. struct fsl_easrc_priv {
  589. struct fsl_easrc_slot slot[EASRC_CTX_MAX_NUM][2];
  590. struct asrc_firmware_hdr *firmware_hdr;
  591. struct interp_params *interp;
  592. struct prefil_params *prefil;
  593. const struct firmware *fw;
  594. const char *fw_name;
  595. unsigned int rs_num_taps;
  596. unsigned int bps_iec958[EASRC_CTX_MAX_NUM];
  597. u64 *rs_coeff;
  598. u64 const_coeff;
  599. int firmware_loaded;
  600. };
  601. #endif /* _FSL_EASRC_H */