fsl_dma.h 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
  4. */
  5. #ifndef _MPC8610_PCM_H
  6. #define _MPC8610_PCM_H
  7. struct ccsr_dma {
  8. u8 res0[0x100];
  9. struct ccsr_dma_channel {
  10. __be32 mr; /* Mode register */
  11. __be32 sr; /* Status register */
  12. __be32 eclndar; /* Current link descriptor extended addr reg */
  13. __be32 clndar; /* Current link descriptor address register */
  14. __be32 satr; /* Source attributes register */
  15. __be32 sar; /* Source address register */
  16. __be32 datr; /* Destination attributes register */
  17. __be32 dar; /* Destination address register */
  18. __be32 bcr; /* Byte count register */
  19. __be32 enlndar; /* Next link descriptor extended address reg */
  20. __be32 nlndar; /* Next link descriptor address register */
  21. u8 res1[4];
  22. __be32 eclsdar; /* Current list descriptor extended addr reg */
  23. __be32 clsdar; /* Current list descriptor address register */
  24. __be32 enlsdar; /* Next list descriptor extended address reg */
  25. __be32 nlsdar; /* Next list descriptor address register */
  26. __be32 ssr; /* Source stride register */
  27. __be32 dsr; /* Destination stride register */
  28. u8 res2[0x38];
  29. } channel[4];
  30. __be32 dgsr;
  31. };
  32. #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000
  33. #define CCSR_DMA_MR_BWC_SHIFT 24
  34. #define CCSR_DMA_MR_BWC_MASK 0x0F000000
  35. #define CCSR_DMA_MR_BWC(x) \
  36. ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)
  37. #define CCSR_DMA_MR_EMP_EN 0x00200000
  38. #define CCSR_DMA_MR_EMS_EN 0x00040000
  39. #define CCSR_DMA_MR_DAHTS_MASK 0x00030000
  40. #define CCSR_DMA_MR_DAHTS_1 0x00000000
  41. #define CCSR_DMA_MR_DAHTS_2 0x00010000
  42. #define CCSR_DMA_MR_DAHTS_4 0x00020000
  43. #define CCSR_DMA_MR_DAHTS_8 0x00030000
  44. #define CCSR_DMA_MR_SAHTS_MASK 0x0000C000
  45. #define CCSR_DMA_MR_SAHTS_1 0x00000000
  46. #define CCSR_DMA_MR_SAHTS_2 0x00004000
  47. #define CCSR_DMA_MR_SAHTS_4 0x00008000
  48. #define CCSR_DMA_MR_SAHTS_8 0x0000C000
  49. #define CCSR_DMA_MR_DAHE 0x00002000
  50. #define CCSR_DMA_MR_SAHE 0x00001000
  51. #define CCSR_DMA_MR_SRW 0x00000400
  52. #define CCSR_DMA_MR_EOSIE 0x00000200
  53. #define CCSR_DMA_MR_EOLNIE 0x00000100
  54. #define CCSR_DMA_MR_EOLSIE 0x00000080
  55. #define CCSR_DMA_MR_EIE 0x00000040
  56. #define CCSR_DMA_MR_XFE 0x00000020
  57. #define CCSR_DMA_MR_CDSM_SWSM 0x00000010
  58. #define CCSR_DMA_MR_CA 0x00000008
  59. #define CCSR_DMA_MR_CTM 0x00000004
  60. #define CCSR_DMA_MR_CC 0x00000002
  61. #define CCSR_DMA_MR_CS 0x00000001
  62. #define CCSR_DMA_SR_TE 0x00000080
  63. #define CCSR_DMA_SR_CH 0x00000020
  64. #define CCSR_DMA_SR_PE 0x00000010
  65. #define CCSR_DMA_SR_EOLNI 0x00000008
  66. #define CCSR_DMA_SR_CB 0x00000004
  67. #define CCSR_DMA_SR_EOSI 0x00000002
  68. #define CCSR_DMA_SR_EOLSI 0x00000001
  69. /* ECLNDAR takes bits 32-36 of the CLNDAR register */
  70. static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)
  71. {
  72. return (x >> 32) & 0xf;
  73. }
  74. #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
  75. #define CCSR_DMA_CLNDAR_EOSIE 0x00000008
  76. /* SATR and DATR, combined */
  77. #define CCSR_DMA_ATR_PBATMU 0x20000000
  78. #define CCSR_DMA_ATR_TFLOWLVL_0 0x00000000
  79. #define CCSR_DMA_ATR_TFLOWLVL_1 0x06000000
  80. #define CCSR_DMA_ATR_TFLOWLVL_2 0x08000000
  81. #define CCSR_DMA_ATR_TFLOWLVL_3 0x0C000000
  82. #define CCSR_DMA_ATR_PCIORDER 0x02000000
  83. #define CCSR_DMA_ATR_SME 0x01000000
  84. #define CCSR_DMA_ATR_NOSNOOP 0x00040000
  85. #define CCSR_DMA_ATR_SNOOP 0x00050000
  86. #define CCSR_DMA_ATR_ESAD_MASK 0x0000000F
  87. /**
  88. * List Descriptor for extended chaining mode DMA operations.
  89. *
  90. * The CLSDAR register points to the first (in a linked-list) List
  91. * Descriptor. Each object must be aligned on a 32-byte boundary. Each
  92. * list descriptor points to a linked-list of link Descriptors.
  93. */
  94. struct fsl_dma_list_descriptor {
  95. __be64 next; /* Address of next list descriptor */
  96. __be64 first_link; /* Address of first link descriptor */
  97. __be32 source; /* Source stride */
  98. __be32 dest; /* Destination stride */
  99. u8 res[8]; /* Reserved */
  100. } __attribute__ ((aligned(32), packed));
  101. /**
  102. * Link Descriptor for basic and extended chaining mode DMA operations.
  103. *
  104. * A Link Descriptor points to a single DMA buffer. Each link descriptor
  105. * must be aligned on a 32-byte boundary.
  106. */
  107. struct fsl_dma_link_descriptor {
  108. __be32 source_attr; /* Programmed into SATR register */
  109. __be32 source_addr; /* Programmed into SAR register */
  110. __be32 dest_attr; /* Programmed into DATR register */
  111. __be32 dest_addr; /* Programmed into DAR register */
  112. __be64 next; /* Address of next link descriptor */
  113. __be32 count; /* Byte count */
  114. u8 res[4]; /* Reserved */
  115. } __attribute__ ((aligned(32), packed));
  116. #endif