fsl_dma.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale DMA ALSA SoC PCM driver
  4. //
  5. // Author: Timur Tabi <timur@freescale.com>
  6. //
  7. // Copyright 2007-2010 Freescale Semiconductor, Inc.
  8. //
  9. // This driver implements ASoC support for the Elo DMA controller, which is
  10. // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
  11. // the PCM driver is what handles the DMA buffer.
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/delay.h>
  18. #include <linux/gfp.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/list.h>
  23. #include <linux/slab.h>
  24. #include <sound/core.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/soc.h>
  28. #include <asm/io.h>
  29. #include "fsl_dma.h"
  30. #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
  31. #define DRV_NAME "fsl_dma"
  32. /*
  33. * The formats that the DMA controller supports, which is anything
  34. * that is 8, 16, or 32 bits.
  35. */
  36. #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
  37. SNDRV_PCM_FMTBIT_U8 | \
  38. SNDRV_PCM_FMTBIT_S16_LE | \
  39. SNDRV_PCM_FMTBIT_S16_BE | \
  40. SNDRV_PCM_FMTBIT_U16_LE | \
  41. SNDRV_PCM_FMTBIT_U16_BE | \
  42. SNDRV_PCM_FMTBIT_S24_LE | \
  43. SNDRV_PCM_FMTBIT_S24_BE | \
  44. SNDRV_PCM_FMTBIT_U24_LE | \
  45. SNDRV_PCM_FMTBIT_U24_BE | \
  46. SNDRV_PCM_FMTBIT_S32_LE | \
  47. SNDRV_PCM_FMTBIT_S32_BE | \
  48. SNDRV_PCM_FMTBIT_U32_LE | \
  49. SNDRV_PCM_FMTBIT_U32_BE)
  50. struct dma_object {
  51. struct snd_soc_component_driver dai;
  52. dma_addr_t ssi_stx_phys;
  53. dma_addr_t ssi_srx_phys;
  54. unsigned int ssi_fifo_depth;
  55. struct ccsr_dma_channel __iomem *channel;
  56. unsigned int irq;
  57. bool assigned;
  58. };
  59. /*
  60. * The number of DMA links to use. Two is the bare minimum, but if you
  61. * have really small links you might need more.
  62. */
  63. #define NUM_DMA_LINKS 2
  64. /** fsl_dma_private: p-substream DMA data
  65. *
  66. * Each substream has a 1-to-1 association with a DMA channel.
  67. *
  68. * The link[] array is first because it needs to be aligned on a 32-byte
  69. * boundary, so putting it first will ensure alignment without padding the
  70. * structure.
  71. *
  72. * @link[]: array of link descriptors
  73. * @dma_channel: pointer to the DMA channel's registers
  74. * @irq: IRQ for this DMA channel
  75. * @substream: pointer to the substream object, needed by the ISR
  76. * @ssi_sxx_phys: bus address of the STX or SRX register to use
  77. * @ld_buf_phys: physical address of the LD buffer
  78. * @current_link: index into link[] of the link currently being processed
  79. * @dma_buf_phys: physical address of the DMA buffer
  80. * @dma_buf_next: physical address of the next period to process
  81. * @dma_buf_end: physical address of the byte after the end of the DMA
  82. * @buffer period_size: the size of a single period
  83. * @num_periods: the number of periods in the DMA buffer
  84. */
  85. struct fsl_dma_private {
  86. struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
  87. struct ccsr_dma_channel __iomem *dma_channel;
  88. unsigned int irq;
  89. struct snd_pcm_substream *substream;
  90. dma_addr_t ssi_sxx_phys;
  91. unsigned int ssi_fifo_depth;
  92. dma_addr_t ld_buf_phys;
  93. unsigned int current_link;
  94. dma_addr_t dma_buf_phys;
  95. dma_addr_t dma_buf_next;
  96. dma_addr_t dma_buf_end;
  97. size_t period_size;
  98. unsigned int num_periods;
  99. };
  100. /**
  101. * fsl_dma_hardare: define characteristics of the PCM hardware.
  102. *
  103. * The PCM hardware is the Freescale DMA controller. This structure defines
  104. * the capabilities of that hardware.
  105. *
  106. * Since the sampling rate and data format are not controlled by the DMA
  107. * controller, we specify no limits for those values. The only exception is
  108. * period_bytes_min, which is set to a reasonably low value to prevent the
  109. * DMA controller from generating too many interrupts per second.
  110. *
  111. * Since each link descriptor has a 32-bit byte count field, we set
  112. * period_bytes_max to the largest 32-bit number. We also have no maximum
  113. * number of periods.
  114. *
  115. * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
  116. * limitation in the SSI driver requires the sample rates for playback and
  117. * capture to be the same.
  118. */
  119. static const struct snd_pcm_hardware fsl_dma_hardware = {
  120. .info = SNDRV_PCM_INFO_INTERLEAVED |
  121. SNDRV_PCM_INFO_MMAP |
  122. SNDRV_PCM_INFO_MMAP_VALID |
  123. SNDRV_PCM_INFO_JOINT_DUPLEX |
  124. SNDRV_PCM_INFO_PAUSE,
  125. .formats = FSLDMA_PCM_FORMATS,
  126. .period_bytes_min = 512, /* A reasonable limit */
  127. .period_bytes_max = (u32) -1,
  128. .periods_min = NUM_DMA_LINKS,
  129. .periods_max = (unsigned int) -1,
  130. .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
  131. };
  132. /**
  133. * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
  134. *
  135. * This function should be called by the ISR whenever the DMA controller
  136. * halts data transfer.
  137. */
  138. static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
  139. {
  140. snd_pcm_stop_xrun(substream);
  141. }
  142. /**
  143. * fsl_dma_update_pointers - update LD pointers to point to the next period
  144. *
  145. * As each period is completed, this function changes the link
  146. * descriptor pointers for that period to point to the next period.
  147. */
  148. static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
  149. {
  150. struct fsl_dma_link_descriptor *link =
  151. &dma_private->link[dma_private->current_link];
  152. /* Update our link descriptors to point to the next period. On a 36-bit
  153. * system, we also need to update the ESAD bits. We also set (keep) the
  154. * snoop bits. See the comments in fsl_dma_hw_params() about snooping.
  155. */
  156. if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  157. link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
  158. #ifdef CONFIG_PHYS_64BIT
  159. link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
  160. upper_32_bits(dma_private->dma_buf_next));
  161. #endif
  162. } else {
  163. link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
  164. #ifdef CONFIG_PHYS_64BIT
  165. link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
  166. upper_32_bits(dma_private->dma_buf_next));
  167. #endif
  168. }
  169. /* Update our variables for next time */
  170. dma_private->dma_buf_next += dma_private->period_size;
  171. if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
  172. dma_private->dma_buf_next = dma_private->dma_buf_phys;
  173. if (++dma_private->current_link >= NUM_DMA_LINKS)
  174. dma_private->current_link = 0;
  175. }
  176. /**
  177. * fsl_dma_isr: interrupt handler for the DMA controller
  178. *
  179. * @irq: IRQ of the DMA channel
  180. * @dev_id: pointer to the dma_private structure for this DMA channel
  181. */
  182. static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
  183. {
  184. struct fsl_dma_private *dma_private = dev_id;
  185. struct snd_pcm_substream *substream = dma_private->substream;
  186. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  187. struct device *dev = rtd->dev;
  188. struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
  189. irqreturn_t ret = IRQ_NONE;
  190. u32 sr, sr2 = 0;
  191. /* We got an interrupt, so read the status register to see what we
  192. were interrupted for.
  193. */
  194. sr = in_be32(&dma_channel->sr);
  195. if (sr & CCSR_DMA_SR_TE) {
  196. dev_err(dev, "dma transmit error\n");
  197. fsl_dma_abort_stream(substream);
  198. sr2 |= CCSR_DMA_SR_TE;
  199. ret = IRQ_HANDLED;
  200. }
  201. if (sr & CCSR_DMA_SR_CH)
  202. ret = IRQ_HANDLED;
  203. if (sr & CCSR_DMA_SR_PE) {
  204. dev_err(dev, "dma programming error\n");
  205. fsl_dma_abort_stream(substream);
  206. sr2 |= CCSR_DMA_SR_PE;
  207. ret = IRQ_HANDLED;
  208. }
  209. if (sr & CCSR_DMA_SR_EOLNI) {
  210. sr2 |= CCSR_DMA_SR_EOLNI;
  211. ret = IRQ_HANDLED;
  212. }
  213. if (sr & CCSR_DMA_SR_CB)
  214. ret = IRQ_HANDLED;
  215. if (sr & CCSR_DMA_SR_EOSI) {
  216. /* Tell ALSA we completed a period. */
  217. snd_pcm_period_elapsed(substream);
  218. /*
  219. * Update our link descriptors to point to the next period. We
  220. * only need to do this if the number of periods is not equal to
  221. * the number of links.
  222. */
  223. if (dma_private->num_periods != NUM_DMA_LINKS)
  224. fsl_dma_update_pointers(dma_private);
  225. sr2 |= CCSR_DMA_SR_EOSI;
  226. ret = IRQ_HANDLED;
  227. }
  228. if (sr & CCSR_DMA_SR_EOLSI) {
  229. sr2 |= CCSR_DMA_SR_EOLSI;
  230. ret = IRQ_HANDLED;
  231. }
  232. /* Clear the bits that we set */
  233. if (sr2)
  234. out_be32(&dma_channel->sr, sr2);
  235. return ret;
  236. }
  237. /**
  238. * fsl_dma_new: initialize this PCM driver.
  239. *
  240. * This function is called when the codec driver calls snd_soc_new_pcms(),
  241. * once for each .dai_link in the machine driver's snd_soc_card
  242. * structure.
  243. *
  244. * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
  245. * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
  246. * is specified. Therefore, any DMA buffers we allocate will always be in low
  247. * memory, but we support for 36-bit physical addresses anyway.
  248. *
  249. * Regardless of where the memory is actually allocated, since the device can
  250. * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
  251. */
  252. static int fsl_dma_new(struct snd_soc_component *component,
  253. struct snd_soc_pcm_runtime *rtd)
  254. {
  255. struct snd_card *card = rtd->card->snd_card;
  256. struct snd_pcm *pcm = rtd->pcm;
  257. int ret;
  258. ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
  259. if (ret)
  260. return ret;
  261. /* Some codecs have separate DAIs for playback and capture, so we
  262. * should allocate a DMA buffer only for the streams that are valid.
  263. */
  264. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
  265. ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
  266. fsl_dma_hardware.buffer_bytes_max,
  267. &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
  268. if (ret) {
  269. dev_err(card->dev, "can't alloc playback dma buffer\n");
  270. return ret;
  271. }
  272. }
  273. if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
  274. ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
  275. fsl_dma_hardware.buffer_bytes_max,
  276. &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
  277. if (ret) {
  278. dev_err(card->dev, "can't alloc capture dma buffer\n");
  279. snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
  280. return ret;
  281. }
  282. }
  283. return 0;
  284. }
  285. /**
  286. * fsl_dma_open: open a new substream.
  287. *
  288. * Each substream has its own DMA buffer.
  289. *
  290. * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
  291. * descriptors that ping-pong from one period to the next. For example, if
  292. * there are six periods and two link descriptors, this is how they look
  293. * before playback starts:
  294. *
  295. * The last link descriptor
  296. * ____________ points back to the first
  297. * | |
  298. * V |
  299. * ___ ___ |
  300. * | |->| |->|
  301. * |___| |___|
  302. * | |
  303. * | |
  304. * V V
  305. * _________________________________________
  306. * | | | | | | | The DMA buffer is
  307. * | | | | | | | divided into 6 parts
  308. * |______|______|______|______|______|______|
  309. *
  310. * and here's how they look after the first period is finished playing:
  311. *
  312. * ____________
  313. * | |
  314. * V |
  315. * ___ ___ |
  316. * | |->| |->|
  317. * |___| |___|
  318. * | |
  319. * |______________
  320. * | |
  321. * V V
  322. * _________________________________________
  323. * | | | | | | |
  324. * | | | | | | |
  325. * |______|______|______|______|______|______|
  326. *
  327. * The first link descriptor now points to the third period. The DMA
  328. * controller is currently playing the second period. When it finishes, it
  329. * will jump back to the first descriptor and play the third period.
  330. *
  331. * There are four reasons we do this:
  332. *
  333. * 1. The only way to get the DMA controller to automatically restart the
  334. * transfer when it gets to the end of the buffer is to use chaining
  335. * mode. Basic direct mode doesn't offer that feature.
  336. * 2. We need to receive an interrupt at the end of every period. The DMA
  337. * controller can generate an interrupt at the end of every link transfer
  338. * (aka segment). Making each period into a DMA segment will give us the
  339. * interrupts we need.
  340. * 3. By creating only two link descriptors, regardless of the number of
  341. * periods, we do not need to reallocate the link descriptors if the
  342. * number of periods changes.
  343. * 4. All of the audio data is still stored in a single, contiguous DMA
  344. * buffer, which is what ALSA expects. We're just dividing it into
  345. * contiguous parts, and creating a link descriptor for each one.
  346. */
  347. static int fsl_dma_open(struct snd_soc_component *component,
  348. struct snd_pcm_substream *substream)
  349. {
  350. struct snd_pcm_runtime *runtime = substream->runtime;
  351. struct device *dev = component->dev;
  352. struct dma_object *dma =
  353. container_of(component->driver, struct dma_object, dai);
  354. struct fsl_dma_private *dma_private;
  355. struct ccsr_dma_channel __iomem *dma_channel;
  356. dma_addr_t ld_buf_phys;
  357. u64 temp_link; /* Pointer to next link descriptor */
  358. u32 mr;
  359. unsigned int channel;
  360. int ret = 0;
  361. unsigned int i;
  362. /*
  363. * Reject any DMA buffer whose size is not a multiple of the period
  364. * size. We need to make sure that the DMA buffer can be evenly divided
  365. * into periods.
  366. */
  367. ret = snd_pcm_hw_constraint_integer(runtime,
  368. SNDRV_PCM_HW_PARAM_PERIODS);
  369. if (ret < 0) {
  370. dev_err(dev, "invalid buffer size\n");
  371. return ret;
  372. }
  373. channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
  374. if (dma->assigned) {
  375. dev_err(dev, "dma channel already assigned\n");
  376. return -EBUSY;
  377. }
  378. dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
  379. &ld_buf_phys, GFP_KERNEL);
  380. if (!dma_private) {
  381. dev_err(dev, "can't allocate dma private data\n");
  382. return -ENOMEM;
  383. }
  384. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  385. dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
  386. else
  387. dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
  388. dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
  389. dma_private->dma_channel = dma->channel;
  390. dma_private->irq = dma->irq;
  391. dma_private->substream = substream;
  392. dma_private->ld_buf_phys = ld_buf_phys;
  393. dma_private->dma_buf_phys = substream->dma_buffer.addr;
  394. ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
  395. dma_private);
  396. if (ret) {
  397. dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
  398. dma_private->irq, ret);
  399. dma_free_coherent(dev, sizeof(struct fsl_dma_private),
  400. dma_private, dma_private->ld_buf_phys);
  401. return ret;
  402. }
  403. dma->assigned = true;
  404. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  405. snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
  406. runtime->private_data = dma_private;
  407. /* Program the fixed DMA controller parameters */
  408. dma_channel = dma_private->dma_channel;
  409. temp_link = dma_private->ld_buf_phys +
  410. sizeof(struct fsl_dma_link_descriptor);
  411. for (i = 0; i < NUM_DMA_LINKS; i++) {
  412. dma_private->link[i].next = cpu_to_be64(temp_link);
  413. temp_link += sizeof(struct fsl_dma_link_descriptor);
  414. }
  415. /* The last link descriptor points to the first */
  416. dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
  417. /* Tell the DMA controller where the first link descriptor is */
  418. out_be32(&dma_channel->clndar,
  419. CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
  420. out_be32(&dma_channel->eclndar,
  421. CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
  422. /* The manual says the BCR must be clear before enabling EMP */
  423. out_be32(&dma_channel->bcr, 0);
  424. /*
  425. * Program the mode register for interrupts, external master control,
  426. * and source/destination hold. Also clear the Channel Abort bit.
  427. */
  428. mr = in_be32(&dma_channel->mr) &
  429. ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
  430. /*
  431. * We want External Master Start and External Master Pause enabled,
  432. * because the SSI is controlling the DMA controller. We want the DMA
  433. * controller to be set up in advance, and then we signal only the SSI
  434. * to start transferring.
  435. *
  436. * We want End-Of-Segment Interrupts enabled, because this will generate
  437. * an interrupt at the end of each segment (each link descriptor
  438. * represents one segment). Each DMA segment is the same thing as an
  439. * ALSA period, so this is how we get an interrupt at the end of every
  440. * period.
  441. *
  442. * We want Error Interrupt enabled, so that we can get an error if
  443. * the DMA controller is mis-programmed somehow.
  444. */
  445. mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
  446. CCSR_DMA_MR_EMS_EN;
  447. /* For playback, we want the destination address to be held. For
  448. capture, set the source address to be held. */
  449. mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
  450. CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
  451. out_be32(&dma_channel->mr, mr);
  452. return 0;
  453. }
  454. /**
  455. * fsl_dma_hw_params: continue initializing the DMA links
  456. *
  457. * This function obtains hardware parameters about the opened stream and
  458. * programs the DMA controller accordingly.
  459. *
  460. * One drawback of big-endian is that when copying integers of different
  461. * sizes to a fixed-sized register, the address to which the integer must be
  462. * copied is dependent on the size of the integer.
  463. *
  464. * For example, if P is the address of a 32-bit register, and X is a 32-bit
  465. * integer, then X should be copied to address P. However, if X is a 16-bit
  466. * integer, then it should be copied to P+2. If X is an 8-bit register,
  467. * then it should be copied to P+3.
  468. *
  469. * So for playback of 8-bit samples, the DMA controller must transfer single
  470. * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
  471. * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
  472. *
  473. * For 24-bit samples, the offset is 1 byte. However, the DMA controller
  474. * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
  475. * and 8 bytes at a time). So we do not support packed 24-bit samples.
  476. * 24-bit data must be padded to 32 bits.
  477. */
  478. static int fsl_dma_hw_params(struct snd_soc_component *component,
  479. struct snd_pcm_substream *substream,
  480. struct snd_pcm_hw_params *hw_params)
  481. {
  482. struct snd_pcm_runtime *runtime = substream->runtime;
  483. struct fsl_dma_private *dma_private = runtime->private_data;
  484. struct device *dev = component->dev;
  485. /* Number of bits per sample */
  486. unsigned int sample_bits =
  487. snd_pcm_format_physical_width(params_format(hw_params));
  488. /* Number of bytes per frame */
  489. unsigned int sample_bytes = sample_bits / 8;
  490. /* Bus address of SSI STX register */
  491. dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
  492. /* Size of the DMA buffer, in bytes */
  493. size_t buffer_size = params_buffer_bytes(hw_params);
  494. /* Number of bytes per period */
  495. size_t period_size = params_period_bytes(hw_params);
  496. /* Pointer to next period */
  497. dma_addr_t temp_addr = substream->dma_buffer.addr;
  498. /* Pointer to DMA controller */
  499. struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
  500. u32 mr; /* DMA Mode Register */
  501. unsigned int i;
  502. /* Initialize our DMA tracking variables */
  503. dma_private->period_size = period_size;
  504. dma_private->num_periods = params_periods(hw_params);
  505. dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
  506. dma_private->dma_buf_next = dma_private->dma_buf_phys +
  507. (NUM_DMA_LINKS * period_size);
  508. if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
  509. /* This happens if the number of periods == NUM_DMA_LINKS */
  510. dma_private->dma_buf_next = dma_private->dma_buf_phys;
  511. mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
  512. CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
  513. /* Due to a quirk of the SSI's STX register, the target address
  514. * for the DMA operations depends on the sample size. So we calculate
  515. * that offset here. While we're at it, also tell the DMA controller
  516. * how much data to transfer per sample.
  517. */
  518. switch (sample_bits) {
  519. case 8:
  520. mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
  521. ssi_sxx_phys += 3;
  522. break;
  523. case 16:
  524. mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
  525. ssi_sxx_phys += 2;
  526. break;
  527. case 32:
  528. mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
  529. break;
  530. default:
  531. /* We should never get here */
  532. dev_err(dev, "unsupported sample size %u\n", sample_bits);
  533. return -EINVAL;
  534. }
  535. /*
  536. * BWC determines how many bytes are sent/received before the DMA
  537. * controller checks the SSI to see if it needs to stop. BWC should
  538. * always be a multiple of the frame size, so that we always transmit
  539. * whole frames. Each frame occupies two slots in the FIFO. The
  540. * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
  541. * (MR[BWC] can only represent even powers of two).
  542. *
  543. * To simplify the process, we set BWC to the largest value that is
  544. * less than or equal to the FIFO watermark. For playback, this ensures
  545. * that we transfer the maximum amount without overrunning the FIFO.
  546. * For capture, this ensures that we transfer the maximum amount without
  547. * underrunning the FIFO.
  548. *
  549. * f = SSI FIFO depth
  550. * w = SSI watermark value (which equals f - 2)
  551. * b = DMA bandwidth count (in bytes)
  552. * s = sample size (in bytes, which equals frame_size * 2)
  553. *
  554. * For playback, we never transmit more than the transmit FIFO
  555. * watermark, otherwise we might write more data than the FIFO can hold.
  556. * The watermark is equal to the FIFO depth minus two.
  557. *
  558. * For capture, two equations must hold:
  559. * w > f - (b / s)
  560. * w >= b / s
  561. *
  562. * So, b > 2 * s, but b must also be <= s * w. To simplify, we set
  563. * b = s * w, which is equal to
  564. * (dma_private->ssi_fifo_depth - 2) * sample_bytes.
  565. */
  566. mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
  567. out_be32(&dma_channel->mr, mr);
  568. for (i = 0; i < NUM_DMA_LINKS; i++) {
  569. struct fsl_dma_link_descriptor *link = &dma_private->link[i];
  570. link->count = cpu_to_be32(period_size);
  571. /* The snoop bit tells the DMA controller whether it should tell
  572. * the ECM to snoop during a read or write to an address. For
  573. * audio, we use DMA to transfer data between memory and an I/O
  574. * device (the SSI's STX0 or SRX0 register). Snooping is only
  575. * needed if there is a cache, so we need to snoop memory
  576. * addresses only. For playback, that means we snoop the source
  577. * but not the destination. For capture, we snoop the
  578. * destination but not the source.
  579. *
  580. * Note that failing to snoop properly is unlikely to cause
  581. * cache incoherency if the period size is larger than the
  582. * size of L1 cache. This is because filling in one period will
  583. * flush out the data for the previous period. So if you
  584. * increased period_bytes_min to a large enough size, you might
  585. * get more performance by not snooping, and you'll still be
  586. * okay. You'll need to update fsl_dma_update_pointers() also.
  587. */
  588. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  589. link->source_addr = cpu_to_be32(temp_addr);
  590. link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
  591. upper_32_bits(temp_addr));
  592. link->dest_addr = cpu_to_be32(ssi_sxx_phys);
  593. link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
  594. upper_32_bits(ssi_sxx_phys));
  595. } else {
  596. link->source_addr = cpu_to_be32(ssi_sxx_phys);
  597. link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
  598. upper_32_bits(ssi_sxx_phys));
  599. link->dest_addr = cpu_to_be32(temp_addr);
  600. link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
  601. upper_32_bits(temp_addr));
  602. }
  603. temp_addr += period_size;
  604. }
  605. return 0;
  606. }
  607. /**
  608. * fsl_dma_pointer: determine the current position of the DMA transfer
  609. *
  610. * This function is called by ALSA when ALSA wants to know where in the
  611. * stream buffer the hardware currently is.
  612. *
  613. * For playback, the SAR register contains the physical address of the most
  614. * recent DMA transfer. For capture, the value is in the DAR register.
  615. *
  616. * The base address of the buffer is stored in the source_addr field of the
  617. * first link descriptor.
  618. */
  619. static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component,
  620. struct snd_pcm_substream *substream)
  621. {
  622. struct snd_pcm_runtime *runtime = substream->runtime;
  623. struct fsl_dma_private *dma_private = runtime->private_data;
  624. struct device *dev = component->dev;
  625. struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
  626. dma_addr_t position;
  627. snd_pcm_uframes_t frames;
  628. /* Obtain the current DMA pointer, but don't read the ESAD bits if we
  629. * only have 32-bit DMA addresses. This function is typically called
  630. * in interrupt context, so we need to optimize it.
  631. */
  632. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  633. position = in_be32(&dma_channel->sar);
  634. #ifdef CONFIG_PHYS_64BIT
  635. position |= (u64)(in_be32(&dma_channel->satr) &
  636. CCSR_DMA_ATR_ESAD_MASK) << 32;
  637. #endif
  638. } else {
  639. position = in_be32(&dma_channel->dar);
  640. #ifdef CONFIG_PHYS_64BIT
  641. position |= (u64)(in_be32(&dma_channel->datr) &
  642. CCSR_DMA_ATR_ESAD_MASK) << 32;
  643. #endif
  644. }
  645. /*
  646. * When capture is started, the SSI immediately starts to fill its FIFO.
  647. * This means that the DMA controller is not started until the FIFO is
  648. * full. However, ALSA calls this function before that happens, when
  649. * MR.DAR is still zero. In this case, just return zero to indicate
  650. * that nothing has been received yet.
  651. */
  652. if (!position)
  653. return 0;
  654. if ((position < dma_private->dma_buf_phys) ||
  655. (position > dma_private->dma_buf_end)) {
  656. dev_err(dev, "dma pointer is out of range, halting stream\n");
  657. return SNDRV_PCM_POS_XRUN;
  658. }
  659. frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
  660. /*
  661. * If the current address is just past the end of the buffer, wrap it
  662. * around.
  663. */
  664. if (frames == runtime->buffer_size)
  665. frames = 0;
  666. return frames;
  667. }
  668. /**
  669. * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
  670. *
  671. * Release the resources allocated in fsl_dma_hw_params() and de-program the
  672. * registers.
  673. *
  674. * This function can be called multiple times.
  675. */
  676. static int fsl_dma_hw_free(struct snd_soc_component *component,
  677. struct snd_pcm_substream *substream)
  678. {
  679. struct snd_pcm_runtime *runtime = substream->runtime;
  680. struct fsl_dma_private *dma_private = runtime->private_data;
  681. if (dma_private) {
  682. struct ccsr_dma_channel __iomem *dma_channel;
  683. dma_channel = dma_private->dma_channel;
  684. /* Stop the DMA */
  685. out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
  686. out_be32(&dma_channel->mr, 0);
  687. /* Reset all the other registers */
  688. out_be32(&dma_channel->sr, -1);
  689. out_be32(&dma_channel->clndar, 0);
  690. out_be32(&dma_channel->eclndar, 0);
  691. out_be32(&dma_channel->satr, 0);
  692. out_be32(&dma_channel->sar, 0);
  693. out_be32(&dma_channel->datr, 0);
  694. out_be32(&dma_channel->dar, 0);
  695. out_be32(&dma_channel->bcr, 0);
  696. out_be32(&dma_channel->nlndar, 0);
  697. out_be32(&dma_channel->enlndar, 0);
  698. }
  699. return 0;
  700. }
  701. /**
  702. * fsl_dma_close: close the stream.
  703. */
  704. static int fsl_dma_close(struct snd_soc_component *component,
  705. struct snd_pcm_substream *substream)
  706. {
  707. struct snd_pcm_runtime *runtime = substream->runtime;
  708. struct fsl_dma_private *dma_private = runtime->private_data;
  709. struct device *dev = component->dev;
  710. struct dma_object *dma =
  711. container_of(component->driver, struct dma_object, dai);
  712. if (dma_private) {
  713. if (dma_private->irq)
  714. free_irq(dma_private->irq, dma_private);
  715. /* Deallocate the fsl_dma_private structure */
  716. dma_free_coherent(dev, sizeof(struct fsl_dma_private),
  717. dma_private, dma_private->ld_buf_phys);
  718. substream->runtime->private_data = NULL;
  719. }
  720. dma->assigned = false;
  721. return 0;
  722. }
  723. /*
  724. * Remove this PCM driver.
  725. */
  726. static void fsl_dma_free_dma_buffers(struct snd_soc_component *component,
  727. struct snd_pcm *pcm)
  728. {
  729. struct snd_pcm_substream *substream;
  730. unsigned int i;
  731. for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
  732. substream = pcm->streams[i].substream;
  733. if (substream) {
  734. snd_dma_free_pages(&substream->dma_buffer);
  735. substream->dma_buffer.area = NULL;
  736. substream->dma_buffer.addr = 0;
  737. }
  738. }
  739. }
  740. /**
  741. * find_ssi_node -- returns the SSI node that points to its DMA channel node
  742. *
  743. * Although this DMA driver attempts to operate independently of the other
  744. * devices, it still needs to determine some information about the SSI device
  745. * that it's working with. Unfortunately, the device tree does not contain
  746. * a pointer from the DMA channel node to the SSI node -- the pointer goes the
  747. * other way. So we need to scan the device tree for SSI nodes until we find
  748. * the one that points to the given DMA channel node. It's ugly, but at least
  749. * it's contained in this one function.
  750. */
  751. static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
  752. {
  753. struct device_node *ssi_np, *np;
  754. for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
  755. /* Check each DMA phandle to see if it points to us. We
  756. * assume that device_node pointers are a valid comparison.
  757. */
  758. np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
  759. of_node_put(np);
  760. if (np == dma_channel_np)
  761. return ssi_np;
  762. np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
  763. of_node_put(np);
  764. if (np == dma_channel_np)
  765. return ssi_np;
  766. }
  767. return NULL;
  768. }
  769. static int fsl_soc_dma_probe(struct platform_device *pdev)
  770. {
  771. struct dma_object *dma;
  772. struct device_node *np = pdev->dev.of_node;
  773. struct device_node *ssi_np;
  774. struct resource res;
  775. const uint32_t *iprop;
  776. int ret;
  777. /* Find the SSI node that points to us. */
  778. ssi_np = find_ssi_node(np);
  779. if (!ssi_np) {
  780. dev_err(&pdev->dev, "cannot find parent SSI node\n");
  781. return -ENODEV;
  782. }
  783. ret = of_address_to_resource(ssi_np, 0, &res);
  784. if (ret) {
  785. dev_err(&pdev->dev, "could not determine resources for %pOF\n",
  786. ssi_np);
  787. of_node_put(ssi_np);
  788. return ret;
  789. }
  790. dma = kzalloc(sizeof(*dma), GFP_KERNEL);
  791. if (!dma) {
  792. of_node_put(ssi_np);
  793. return -ENOMEM;
  794. }
  795. dma->dai.name = DRV_NAME;
  796. dma->dai.open = fsl_dma_open;
  797. dma->dai.close = fsl_dma_close;
  798. dma->dai.hw_params = fsl_dma_hw_params;
  799. dma->dai.hw_free = fsl_dma_hw_free;
  800. dma->dai.pointer = fsl_dma_pointer;
  801. dma->dai.pcm_construct = fsl_dma_new;
  802. dma->dai.pcm_destruct = fsl_dma_free_dma_buffers;
  803. /* Store the SSI-specific information that we need */
  804. dma->ssi_stx_phys = res.start + REG_SSI_STX0;
  805. dma->ssi_srx_phys = res.start + REG_SSI_SRX0;
  806. iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
  807. if (iprop)
  808. dma->ssi_fifo_depth = be32_to_cpup(iprop);
  809. else
  810. /* Older 8610 DTs didn't have the fifo-depth property */
  811. dma->ssi_fifo_depth = 8;
  812. of_node_put(ssi_np);
  813. ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0);
  814. if (ret) {
  815. dev_err(&pdev->dev, "could not register platform\n");
  816. kfree(dma);
  817. return ret;
  818. }
  819. dma->channel = of_iomap(np, 0);
  820. dma->irq = irq_of_parse_and_map(np, 0);
  821. dev_set_drvdata(&pdev->dev, dma);
  822. return 0;
  823. }
  824. static int fsl_soc_dma_remove(struct platform_device *pdev)
  825. {
  826. struct dma_object *dma = dev_get_drvdata(&pdev->dev);
  827. iounmap(dma->channel);
  828. irq_dispose_mapping(dma->irq);
  829. kfree(dma);
  830. return 0;
  831. }
  832. static const struct of_device_id fsl_soc_dma_ids[] = {
  833. { .compatible = "fsl,ssi-dma-channel", },
  834. {}
  835. };
  836. MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
  837. static struct platform_driver fsl_soc_dma_driver = {
  838. .driver = {
  839. .name = "fsl-pcm-audio",
  840. .of_match_table = fsl_soc_dma_ids,
  841. },
  842. .probe = fsl_soc_dma_probe,
  843. .remove = fsl_soc_dma_remove,
  844. };
  845. module_platform_driver(fsl_soc_dma_driver);
  846. MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
  847. MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
  848. MODULE_LICENSE("GPL v2");