fsl_audmix.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
  4. *
  5. * Copyright 2017 NXP
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/module.h>
  9. #include <linux/of_platform.h>
  10. #include <linux/pm_runtime.h>
  11. #include <sound/soc.h>
  12. #include <sound/pcm_params.h>
  13. #include "fsl_audmix.h"
  14. #define SOC_ENUM_SINGLE_S(xreg, xshift, xtexts) \
  15. SOC_ENUM_SINGLE(xreg, xshift, ARRAY_SIZE(xtexts), xtexts)
  16. static const char
  17. *tdm_sel[] = { "TDM1", "TDM2", },
  18. *mode_sel[] = { "Disabled", "TDM1", "TDM2", "Mixed", },
  19. *width_sel[] = { "16b", "18b", "20b", "24b", "32b", },
  20. *endis_sel[] = { "Disabled", "Enabled", },
  21. *updn_sel[] = { "Downward", "Upward", },
  22. *mask_sel[] = { "Unmask", "Mask", };
  23. static const struct soc_enum fsl_audmix_enum[] = {
  24. /* FSL_AUDMIX_CTR enums */
  25. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MIXCLK_SHIFT, tdm_sel),
  26. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTSRC_SHIFT, mode_sel),
  27. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTWIDTH_SHIFT, width_sel),
  28. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKRTDF_SHIFT, mask_sel),
  29. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKCKDF_SHIFT, mask_sel),
  30. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCMODE_SHIFT, endis_sel),
  31. SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCSRC_SHIFT, tdm_sel),
  32. /* FSL_AUDMIX_ATCR0 enums */
  33. SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
  34. SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 1, updn_sel),
  35. /* FSL_AUDMIX_ATCR1 enums */
  36. SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
  37. SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 1, updn_sel),
  38. };
  39. struct fsl_audmix_state {
  40. u8 tdms;
  41. u8 clk;
  42. char msg[64];
  43. };
  44. static const struct fsl_audmix_state prms[4][4] = {{
  45. /* DIS->DIS, do nothing */
  46. { .tdms = 0, .clk = 0, .msg = "" },
  47. /* DIS->TDM1*/
  48. { .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" },
  49. /* DIS->TDM2*/
  50. { .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" },
  51. /* DIS->MIX */
  52. { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
  53. }, { /* TDM1->DIS */
  54. { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
  55. /* TDM1->TDM1, do nothing */
  56. { .tdms = 0, .clk = 0, .msg = "" },
  57. /* TDM1->TDM2 */
  58. { .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" },
  59. /* TDM1->MIX */
  60. { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
  61. }, { /* TDM2->DIS */
  62. { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
  63. /* TDM2->TDM1 */
  64. { .tdms = 3, .clk = 1, .msg = "TDM2->TDM1: Please start both TDMs!\n" },
  65. /* TDM2->TDM2, do nothing */
  66. { .tdms = 0, .clk = 0, .msg = "" },
  67. /* TDM2->MIX */
  68. { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
  69. }, { /* MIX->DIS */
  70. { .tdms = 3, .clk = 0, .msg = "MIX->DIS: Please start both TDMs!\n" },
  71. /* MIX->TDM1 */
  72. { .tdms = 3, .clk = 1, .msg = "MIX->TDM1: Please start both TDMs!\n" },
  73. /* MIX->TDM2 */
  74. { .tdms = 3, .clk = 2, .msg = "MIX->TDM2: Please start both TDMs!\n" },
  75. /* MIX->MIX, do nothing */
  76. { .tdms = 0, .clk = 0, .msg = "" }
  77. }, };
  78. static int fsl_audmix_state_trans(struct snd_soc_component *comp,
  79. unsigned int *mask, unsigned int *ctr,
  80. const struct fsl_audmix_state prm)
  81. {
  82. struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
  83. /* Enforce all required TDMs are started */
  84. if ((priv->tdms & prm.tdms) != prm.tdms) {
  85. dev_dbg(comp->dev, "%s", prm.msg);
  86. return -EINVAL;
  87. }
  88. switch (prm.clk) {
  89. case 1:
  90. case 2:
  91. /* Set mix clock */
  92. (*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK;
  93. (*ctr) |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1);
  94. break;
  95. default:
  96. break;
  97. }
  98. return 0;
  99. }
  100. static int fsl_audmix_put_mix_clk_src(struct snd_kcontrol *kcontrol,
  101. struct snd_ctl_elem_value *ucontrol)
  102. {
  103. struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
  104. struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
  105. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  106. unsigned int *item = ucontrol->value.enumerated.item;
  107. unsigned int reg_val, val, mix_clk;
  108. /* Get current state */
  109. reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
  110. mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
  111. >> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
  112. val = snd_soc_enum_item_to_val(e, item[0]);
  113. dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
  114. /**
  115. * Ensure the current selected mixer clock is available
  116. * for configuration propagation
  117. */
  118. if (!(priv->tdms & BIT(mix_clk))) {
  119. dev_err(comp->dev,
  120. "Started TDM%d needed for config propagation!\n",
  121. mix_clk + 1);
  122. return -EINVAL;
  123. }
  124. if (!(priv->tdms & BIT(val))) {
  125. dev_err(comp->dev,
  126. "The selected clock source has no TDM%d enabled!\n",
  127. val + 1);
  128. return -EINVAL;
  129. }
  130. return snd_soc_put_enum_double(kcontrol, ucontrol);
  131. }
  132. static int fsl_audmix_put_out_src(struct snd_kcontrol *kcontrol,
  133. struct snd_ctl_elem_value *ucontrol)
  134. {
  135. struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
  136. struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
  137. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  138. unsigned int *item = ucontrol->value.enumerated.item;
  139. u32 out_src, mix_clk;
  140. unsigned int reg_val, val, mask = 0, ctr = 0;
  141. int ret;
  142. /* Get current state */
  143. reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
  144. /* "From" state */
  145. out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK)
  146. >> FSL_AUDMIX_CTR_OUTSRC_SHIFT);
  147. mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
  148. >> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
  149. /* "To" state */
  150. val = snd_soc_enum_item_to_val(e, item[0]);
  151. dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
  152. /* Check if state is changing ... */
  153. if (out_src == val)
  154. return 0;
  155. /**
  156. * Ensure the current selected mixer clock is available
  157. * for configuration propagation
  158. */
  159. if (!(priv->tdms & BIT(mix_clk))) {
  160. dev_err(comp->dev,
  161. "Started TDM%d needed for config propagation!\n",
  162. mix_clk + 1);
  163. return -EINVAL;
  164. }
  165. /* Check state transition constraints */
  166. ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]);
  167. if (ret)
  168. return ret;
  169. /* Complete transition to new state */
  170. mask |= FSL_AUDMIX_CTR_OUTSRC_MASK;
  171. ctr |= FSL_AUDMIX_CTR_OUTSRC(val);
  172. return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
  173. }
  174. static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = {
  175. /* FSL_AUDMIX_CTR controls */
  176. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  177. .name = "Mixing Clock Source",
  178. .info = snd_soc_info_enum_double,
  179. .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
  180. .put = fsl_audmix_put_mix_clk_src,
  181. .private_value = (unsigned long)&fsl_audmix_enum[0] },
  182. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  183. .name = "Output Source",
  184. .info = snd_soc_info_enum_double,
  185. .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
  186. .put = fsl_audmix_put_out_src,
  187. .private_value = (unsigned long)&fsl_audmix_enum[1] },
  188. SOC_ENUM("Output Width", fsl_audmix_enum[2]),
  189. SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]),
  190. SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]),
  191. SOC_ENUM("Sync Mode Config", fsl_audmix_enum[5]),
  192. SOC_ENUM("Sync Mode Clk Source", fsl_audmix_enum[6]),
  193. /* TDM1 Attenuation controls */
  194. SOC_ENUM("TDM1 Attenuation", fsl_audmix_enum[7]),
  195. SOC_ENUM("TDM1 Attenuation Direction", fsl_audmix_enum[8]),
  196. SOC_SINGLE("TDM1 Attenuation Step Divider", FSL_AUDMIX_ATCR0,
  197. 2, 0x00fff, 0),
  198. SOC_SINGLE("TDM1 Attenuation Initial Value", FSL_AUDMIX_ATIVAL0,
  199. 0, 0x3ffff, 0),
  200. SOC_SINGLE("TDM1 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP0,
  201. 0, 0x3ffff, 0),
  202. SOC_SINGLE("TDM1 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN0,
  203. 0, 0x3ffff, 0),
  204. SOC_SINGLE("TDM1 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT0,
  205. 0, 0x3ffff, 0),
  206. /* TDM2 Attenuation controls */
  207. SOC_ENUM("TDM2 Attenuation", fsl_audmix_enum[9]),
  208. SOC_ENUM("TDM2 Attenuation Direction", fsl_audmix_enum[10]),
  209. SOC_SINGLE("TDM2 Attenuation Step Divider", FSL_AUDMIX_ATCR1,
  210. 2, 0x00fff, 0),
  211. SOC_SINGLE("TDM2 Attenuation Initial Value", FSL_AUDMIX_ATIVAL1,
  212. 0, 0x3ffff, 0),
  213. SOC_SINGLE("TDM2 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP1,
  214. 0, 0x3ffff, 0),
  215. SOC_SINGLE("TDM2 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN1,
  216. 0, 0x3ffff, 0),
  217. SOC_SINGLE("TDM2 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT1,
  218. 0, 0x3ffff, 0),
  219. };
  220. static int fsl_audmix_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  221. {
  222. struct snd_soc_component *comp = dai->component;
  223. u32 mask = 0, ctr = 0;
  224. /* AUDMIX is working in DSP_A format only */
  225. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  226. case SND_SOC_DAIFMT_DSP_A:
  227. break;
  228. default:
  229. return -EINVAL;
  230. }
  231. /* For playback the AUDMIX is slave, and for record is master */
  232. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  233. case SND_SOC_DAIFMT_CBM_CFM:
  234. case SND_SOC_DAIFMT_CBS_CFS:
  235. break;
  236. default:
  237. return -EINVAL;
  238. }
  239. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  240. case SND_SOC_DAIFMT_IB_NF:
  241. /* Output data will be written on positive edge of the clock */
  242. ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0);
  243. break;
  244. case SND_SOC_DAIFMT_NB_NF:
  245. /* Output data will be written on negative edge of the clock */
  246. ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1);
  247. break;
  248. default:
  249. return -EINVAL;
  250. }
  251. mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK;
  252. return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
  253. }
  254. static int fsl_audmix_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  255. struct snd_soc_dai *dai)
  256. {
  257. struct fsl_audmix *priv = snd_soc_dai_get_drvdata(dai);
  258. unsigned long lock_flags;
  259. /* Capture stream shall not be handled */
  260. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  261. return 0;
  262. switch (cmd) {
  263. case SNDRV_PCM_TRIGGER_START:
  264. case SNDRV_PCM_TRIGGER_RESUME:
  265. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  266. spin_lock_irqsave(&priv->lock, lock_flags);
  267. priv->tdms |= BIT(dai->driver->id);
  268. spin_unlock_irqrestore(&priv->lock, lock_flags);
  269. break;
  270. case SNDRV_PCM_TRIGGER_STOP:
  271. case SNDRV_PCM_TRIGGER_SUSPEND:
  272. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  273. spin_lock_irqsave(&priv->lock, lock_flags);
  274. priv->tdms &= ~BIT(dai->driver->id);
  275. spin_unlock_irqrestore(&priv->lock, lock_flags);
  276. break;
  277. default:
  278. return -EINVAL;
  279. }
  280. return 0;
  281. }
  282. static const struct snd_soc_dai_ops fsl_audmix_dai_ops = {
  283. .set_fmt = fsl_audmix_dai_set_fmt,
  284. .trigger = fsl_audmix_dai_trigger,
  285. };
  286. static struct snd_soc_dai_driver fsl_audmix_dai[] = {
  287. {
  288. .id = 0,
  289. .name = "audmix-0",
  290. .playback = {
  291. .stream_name = "AUDMIX-Playback-0",
  292. .channels_min = 8,
  293. .channels_max = 8,
  294. .rate_min = 8000,
  295. .rate_max = 96000,
  296. .rates = SNDRV_PCM_RATE_8000_96000,
  297. .formats = FSL_AUDMIX_FORMATS,
  298. },
  299. .capture = {
  300. .stream_name = "AUDMIX-Capture-0",
  301. .channels_min = 8,
  302. .channels_max = 8,
  303. .rate_min = 8000,
  304. .rate_max = 96000,
  305. .rates = SNDRV_PCM_RATE_8000_96000,
  306. .formats = FSL_AUDMIX_FORMATS,
  307. },
  308. .ops = &fsl_audmix_dai_ops,
  309. },
  310. {
  311. .id = 1,
  312. .name = "audmix-1",
  313. .playback = {
  314. .stream_name = "AUDMIX-Playback-1",
  315. .channels_min = 8,
  316. .channels_max = 8,
  317. .rate_min = 8000,
  318. .rate_max = 96000,
  319. .rates = SNDRV_PCM_RATE_8000_96000,
  320. .formats = FSL_AUDMIX_FORMATS,
  321. },
  322. .capture = {
  323. .stream_name = "AUDMIX-Capture-1",
  324. .channels_min = 8,
  325. .channels_max = 8,
  326. .rate_min = 8000,
  327. .rate_max = 96000,
  328. .rates = SNDRV_PCM_RATE_8000_96000,
  329. .formats = FSL_AUDMIX_FORMATS,
  330. },
  331. .ops = &fsl_audmix_dai_ops,
  332. },
  333. };
  334. static const struct snd_soc_component_driver fsl_audmix_component = {
  335. .name = "fsl-audmix-dai",
  336. .controls = fsl_audmix_snd_controls,
  337. .num_controls = ARRAY_SIZE(fsl_audmix_snd_controls),
  338. };
  339. static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg)
  340. {
  341. switch (reg) {
  342. case FSL_AUDMIX_CTR:
  343. case FSL_AUDMIX_STR:
  344. case FSL_AUDMIX_ATCR0:
  345. case FSL_AUDMIX_ATIVAL0:
  346. case FSL_AUDMIX_ATSTPUP0:
  347. case FSL_AUDMIX_ATSTPDN0:
  348. case FSL_AUDMIX_ATSTPTGT0:
  349. case FSL_AUDMIX_ATTNVAL0:
  350. case FSL_AUDMIX_ATSTP0:
  351. case FSL_AUDMIX_ATCR1:
  352. case FSL_AUDMIX_ATIVAL1:
  353. case FSL_AUDMIX_ATSTPUP1:
  354. case FSL_AUDMIX_ATSTPDN1:
  355. case FSL_AUDMIX_ATSTPTGT1:
  356. case FSL_AUDMIX_ATTNVAL1:
  357. case FSL_AUDMIX_ATSTP1:
  358. return true;
  359. default:
  360. return false;
  361. }
  362. }
  363. static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg)
  364. {
  365. switch (reg) {
  366. case FSL_AUDMIX_CTR:
  367. case FSL_AUDMIX_ATCR0:
  368. case FSL_AUDMIX_ATIVAL0:
  369. case FSL_AUDMIX_ATSTPUP0:
  370. case FSL_AUDMIX_ATSTPDN0:
  371. case FSL_AUDMIX_ATSTPTGT0:
  372. case FSL_AUDMIX_ATCR1:
  373. case FSL_AUDMIX_ATIVAL1:
  374. case FSL_AUDMIX_ATSTPUP1:
  375. case FSL_AUDMIX_ATSTPDN1:
  376. case FSL_AUDMIX_ATSTPTGT1:
  377. return true;
  378. default:
  379. return false;
  380. }
  381. }
  382. static const struct reg_default fsl_audmix_reg[] = {
  383. { FSL_AUDMIX_CTR, 0x00060 },
  384. { FSL_AUDMIX_STR, 0x00003 },
  385. { FSL_AUDMIX_ATCR0, 0x00000 },
  386. { FSL_AUDMIX_ATIVAL0, 0x3FFFF },
  387. { FSL_AUDMIX_ATSTPUP0, 0x2AAAA },
  388. { FSL_AUDMIX_ATSTPDN0, 0x30000 },
  389. { FSL_AUDMIX_ATSTPTGT0, 0x00010 },
  390. { FSL_AUDMIX_ATTNVAL0, 0x00000 },
  391. { FSL_AUDMIX_ATSTP0, 0x00000 },
  392. { FSL_AUDMIX_ATCR1, 0x00000 },
  393. { FSL_AUDMIX_ATIVAL1, 0x3FFFF },
  394. { FSL_AUDMIX_ATSTPUP1, 0x2AAAA },
  395. { FSL_AUDMIX_ATSTPDN1, 0x30000 },
  396. { FSL_AUDMIX_ATSTPTGT1, 0x00010 },
  397. { FSL_AUDMIX_ATTNVAL1, 0x00000 },
  398. { FSL_AUDMIX_ATSTP1, 0x00000 },
  399. };
  400. static const struct regmap_config fsl_audmix_regmap_config = {
  401. .reg_bits = 32,
  402. .reg_stride = 4,
  403. .val_bits = 32,
  404. .max_register = FSL_AUDMIX_ATSTP1,
  405. .reg_defaults = fsl_audmix_reg,
  406. .num_reg_defaults = ARRAY_SIZE(fsl_audmix_reg),
  407. .readable_reg = fsl_audmix_readable_reg,
  408. .writeable_reg = fsl_audmix_writeable_reg,
  409. .cache_type = REGCACHE_FLAT,
  410. };
  411. static const struct of_device_id fsl_audmix_ids[] = {
  412. {
  413. .compatible = "fsl,imx8qm-audmix",
  414. .data = "imx-audmix",
  415. },
  416. { /* sentinel */ }
  417. };
  418. MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
  419. static int fsl_audmix_probe(struct platform_device *pdev)
  420. {
  421. struct device *dev = &pdev->dev;
  422. struct fsl_audmix *priv;
  423. const char *mdrv;
  424. const struct of_device_id *of_id;
  425. void __iomem *regs;
  426. int ret;
  427. of_id = of_match_device(fsl_audmix_ids, dev);
  428. if (!of_id || !of_id->data)
  429. return -EINVAL;
  430. mdrv = of_id->data;
  431. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  432. if (!priv)
  433. return -ENOMEM;
  434. /* Get the addresses */
  435. regs = devm_platform_ioremap_resource(pdev, 0);
  436. if (IS_ERR(regs))
  437. return PTR_ERR(regs);
  438. priv->regmap = devm_regmap_init_mmio_clk(dev, "ipg", regs,
  439. &fsl_audmix_regmap_config);
  440. if (IS_ERR(priv->regmap)) {
  441. dev_err(dev, "failed to init regmap\n");
  442. return PTR_ERR(priv->regmap);
  443. }
  444. priv->ipg_clk = devm_clk_get(dev, "ipg");
  445. if (IS_ERR(priv->ipg_clk)) {
  446. dev_err(dev, "failed to get ipg clock\n");
  447. return PTR_ERR(priv->ipg_clk);
  448. }
  449. spin_lock_init(&priv->lock);
  450. platform_set_drvdata(pdev, priv);
  451. pm_runtime_enable(dev);
  452. ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
  453. fsl_audmix_dai,
  454. ARRAY_SIZE(fsl_audmix_dai));
  455. if (ret) {
  456. dev_err(dev, "failed to register ASoC DAI\n");
  457. goto err_disable_pm;
  458. }
  459. priv->pdev = platform_device_register_data(dev, mdrv, 0, NULL, 0);
  460. if (IS_ERR(priv->pdev)) {
  461. ret = PTR_ERR(priv->pdev);
  462. dev_err(dev, "failed to register platform %s: %d\n", mdrv, ret);
  463. goto err_disable_pm;
  464. }
  465. return 0;
  466. err_disable_pm:
  467. pm_runtime_disable(dev);
  468. return ret;
  469. }
  470. static int fsl_audmix_remove(struct platform_device *pdev)
  471. {
  472. struct fsl_audmix *priv = dev_get_drvdata(&pdev->dev);
  473. pm_runtime_disable(&pdev->dev);
  474. if (priv->pdev)
  475. platform_device_unregister(priv->pdev);
  476. return 0;
  477. }
  478. #ifdef CONFIG_PM
  479. static int fsl_audmix_runtime_resume(struct device *dev)
  480. {
  481. struct fsl_audmix *priv = dev_get_drvdata(dev);
  482. int ret;
  483. ret = clk_prepare_enable(priv->ipg_clk);
  484. if (ret) {
  485. dev_err(dev, "Failed to enable IPG clock: %d\n", ret);
  486. return ret;
  487. }
  488. regcache_cache_only(priv->regmap, false);
  489. regcache_mark_dirty(priv->regmap);
  490. return regcache_sync(priv->regmap);
  491. }
  492. static int fsl_audmix_runtime_suspend(struct device *dev)
  493. {
  494. struct fsl_audmix *priv = dev_get_drvdata(dev);
  495. regcache_cache_only(priv->regmap, true);
  496. clk_disable_unprepare(priv->ipg_clk);
  497. return 0;
  498. }
  499. #endif /* CONFIG_PM */
  500. static const struct dev_pm_ops fsl_audmix_pm = {
  501. SET_RUNTIME_PM_OPS(fsl_audmix_runtime_suspend,
  502. fsl_audmix_runtime_resume,
  503. NULL)
  504. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  505. pm_runtime_force_resume)
  506. };
  507. static struct platform_driver fsl_audmix_driver = {
  508. .probe = fsl_audmix_probe,
  509. .remove = fsl_audmix_remove,
  510. .driver = {
  511. .name = "fsl-audmix",
  512. .of_match_table = fsl_audmix_ids,
  513. .pm = &fsl_audmix_pm,
  514. },
  515. };
  516. module_platform_driver(fsl_audmix_driver);
  517. MODULE_DESCRIPTION("NXP AUDMIX ASoC DAI driver");
  518. MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
  519. MODULE_ALIAS("platform:fsl-audmix");
  520. MODULE_LICENSE("GPL v2");