fsl_asrc.h 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * fsl_asrc.h - Freescale ASRC ALSA SoC header file
  4. *
  5. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  6. *
  7. * Author: Nicolin Chen <nicoleotsuka@gmail.com>
  8. */
  9. #ifndef _FSL_ASRC_H
  10. #define _FSL_ASRC_H
  11. #include "fsl_asrc_common.h"
  12. #define ASRC_DMA_BUFFER_NUM 2
  13. #define ASRC_INPUTFIFO_THRESHOLD 32
  14. #define ASRC_OUTPUTFIFO_THRESHOLD 32
  15. #define ASRC_FIFO_THRESHOLD_MIN 0
  16. #define ASRC_FIFO_THRESHOLD_MAX 63
  17. #define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
  18. #define ASRC_MAX_BUFFER_SIZE (1024 * 48)
  19. #define ASRC_OUTPUT_LAST_SAMPLE 8
  20. #define IDEAL_RATIO_RATE 1000000
  21. #define REG_ASRCTR 0x00
  22. #define REG_ASRIER 0x04
  23. #define REG_ASRCNCR 0x0C
  24. #define REG_ASRCFG 0x10
  25. #define REG_ASRCSR 0x14
  26. #define REG_ASRCDR1 0x18
  27. #define REG_ASRCDR2 0x1C
  28. #define REG_ASRCDR(i) ((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
  29. #define REG_ASRSTR 0x20
  30. #define REG_ASRRA 0x24
  31. #define REG_ASRRB 0x28
  32. #define REG_ASRRC 0x2C
  33. #define REG_ASRPM1 0x40
  34. #define REG_ASRPM2 0x44
  35. #define REG_ASRPM3 0x48
  36. #define REG_ASRPM4 0x4C
  37. #define REG_ASRPM5 0x50
  38. #define REG_ASRTFR1 0x54
  39. #define REG_ASRCCR 0x5C
  40. #define REG_ASRDIA 0x60
  41. #define REG_ASRDOA 0x64
  42. #define REG_ASRDIB 0x68
  43. #define REG_ASRDOB 0x6C
  44. #define REG_ASRDIC 0x70
  45. #define REG_ASRDOC 0x74
  46. #define REG_ASRDI(i) (REG_ASRDIA + (i << 3))
  47. #define REG_ASRDO(i) (REG_ASRDOA + (i << 3))
  48. #define REG_ASRDx(x, i) ((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
  49. #define REG_ASRIDRHA 0x80
  50. #define REG_ASRIDRLA 0x84
  51. #define REG_ASRIDRHB 0x88
  52. #define REG_ASRIDRLB 0x8C
  53. #define REG_ASRIDRHC 0x90
  54. #define REG_ASRIDRLC 0x94
  55. #define REG_ASRIDRH(i) (REG_ASRIDRHA + (i << 3))
  56. #define REG_ASRIDRL(i) (REG_ASRIDRLA + (i << 3))
  57. #define REG_ASR76K 0x98
  58. #define REG_ASR56K 0x9C
  59. #define REG_ASRMCRA 0xA0
  60. #define REG_ASRFSTA 0xA4
  61. #define REG_ASRMCRB 0xA8
  62. #define REG_ASRFSTB 0xAC
  63. #define REG_ASRMCRC 0xB0
  64. #define REG_ASRFSTC 0xB4
  65. #define REG_ASRMCR(i) (REG_ASRMCRA + (i << 3))
  66. #define REG_ASRFST(i) (REG_ASRFSTA + (i << 3))
  67. #define REG_ASRMCR1A 0xC0
  68. #define REG_ASRMCR1B 0xC4
  69. #define REG_ASRMCR1C 0xC8
  70. #define REG_ASRMCR1(i) (REG_ASRMCR1A + (i << 2))
  71. /* REG0 0x00 REG_ASRCTR */
  72. #define ASRCTR_ATSi_SHIFT(i) (20 + i)
  73. #define ASRCTR_ATSi_MASK(i) (1 << ASRCTR_ATSi_SHIFT(i))
  74. #define ASRCTR_ATS(i) (1 << ASRCTR_ATSi_SHIFT(i))
  75. #define ASRCTR_USRi_SHIFT(i) (14 + (i << 1))
  76. #define ASRCTR_USRi_MASK(i) (1 << ASRCTR_USRi_SHIFT(i))
  77. #define ASRCTR_USR(i) (1 << ASRCTR_USRi_SHIFT(i))
  78. #define ASRCTR_IDRi_SHIFT(i) (13 + (i << 1))
  79. #define ASRCTR_IDRi_MASK(i) (1 << ASRCTR_IDRi_SHIFT(i))
  80. #define ASRCTR_IDR(i) (1 << ASRCTR_IDRi_SHIFT(i))
  81. #define ASRCTR_SRST_SHIFT 4
  82. #define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
  83. #define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
  84. #define ASRCTR_ASRCEi_SHIFT(i) (1 + i)
  85. #define ASRCTR_ASRCEi_MASK(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
  86. #define ASRCTR_ASRCE(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
  87. #define ASRCTR_ASRCEi_ALL_MASK (0x7 << ASRCTR_ASRCEi_SHIFT(0))
  88. #define ASRCTR_ASRCEN_SHIFT 0
  89. #define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
  90. #define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
  91. /* REG1 0x04 REG_ASRIER */
  92. #define ASRIER_AFPWE_SHIFT 7
  93. #define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
  94. #define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
  95. #define ASRIER_AOLIE_SHIFT 6
  96. #define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
  97. #define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
  98. #define ASRIER_ADOEi_SHIFT(i) (3 + i)
  99. #define ASRIER_ADOEi_MASK(i) (1 << ASRIER_ADOEi_SHIFT(i))
  100. #define ASRIER_ADOE(i) (1 << ASRIER_ADOEi_SHIFT(i))
  101. #define ASRIER_ADIEi_SHIFT(i) (0 + i)
  102. #define ASRIER_ADIEi_MASK(i) (1 << ASRIER_ADIEi_SHIFT(i))
  103. #define ASRIER_ADIE(i) (1 << ASRIER_ADIEi_SHIFT(i))
  104. /* REG2 0x0C REG_ASRCNCR */
  105. #define ASRCNCR_ANCi_SHIFT(i, b) (b * i)
  106. #define ASRCNCR_ANCi_MASK(i, b) (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
  107. #define ASRCNCR_ANCi(i, v, b) ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
  108. /* REG3 0x10 REG_ASRCFG */
  109. #define ASRCFG_INIRQi_SHIFT(i) (21 + i)
  110. #define ASRCFG_INIRQi_MASK(i) (1 << ASRCFG_INIRQi_SHIFT(i))
  111. #define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
  112. #define ASRCFG_NDPRi_SHIFT(i) (18 + i)
  113. #define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
  114. #define ASRCFG_NDPRi_ALL_SHIFT 18
  115. #define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
  116. #define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
  117. #define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
  118. #define ASRCFG_POSTMODi_WIDTH 2
  119. #define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
  120. #define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
  121. #define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
  122. #define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
  123. #define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
  124. #define ASRCFG_POSTMODi_DOWN(i) (2 << ASRCFG_POSTMODi_SHIFT(i))
  125. #define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
  126. #define ASRCFG_PREMODi_WIDTH 2
  127. #define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
  128. #define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
  129. #define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
  130. #define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
  131. #define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
  132. #define ASRCFG_PREMODi_DOWN(i) (2 << ASRCFG_PREMODi_SHIFT(i))
  133. #define ASRCFG_PREMODi_BYPASS(i) (3 << ASRCFG_PREMODi_SHIFT(i))
  134. /* REG4 0x14 REG_ASRCSR */
  135. #define ASRCSR_AxCSi_WIDTH 4
  136. #define ASRCSR_AxCSi_MASK ((1 << ASRCSR_AxCSi_WIDTH) - 1)
  137. #define ASRCSR_AOCSi_SHIFT(i) (12 + (i << 2))
  138. #define ASRCSR_AOCSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
  139. #define ASRCSR_AOCS(i, v) ((v) << ASRCSR_AOCSi_SHIFT(i))
  140. #define ASRCSR_AICSi_SHIFT(i) (i << 2)
  141. #define ASRCSR_AICSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
  142. #define ASRCSR_AICS(i, v) ((v) << ASRCSR_AICSi_SHIFT(i))
  143. /* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
  144. #define ASRCDRi_AxCPi_WIDTH 3
  145. #define ASRCDRi_AICPi_SHIFT(i) (0 + (i % 2) * 6)
  146. #define ASRCDRi_AICPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
  147. #define ASRCDRi_AICP(i, v) ((v) << ASRCDRi_AICPi_SHIFT(i))
  148. #define ASRCDRi_AICDi_SHIFT(i) (3 + (i % 2) * 6)
  149. #define ASRCDRi_AICDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
  150. #define ASRCDRi_AICD(i, v) ((v) << ASRCDRi_AICDi_SHIFT(i))
  151. #define ASRCDRi_AOCPi_SHIFT(i) ((i < 2) ? 12 + i * 6 : 6)
  152. #define ASRCDRi_AOCPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
  153. #define ASRCDRi_AOCP(i, v) ((v) << ASRCDRi_AOCPi_SHIFT(i))
  154. #define ASRCDRi_AOCDi_SHIFT(i) ((i < 2) ? 15 + i * 6 : 9)
  155. #define ASRCDRi_AOCDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
  156. #define ASRCDRi_AOCD(i, v) ((v) << ASRCDRi_AOCDi_SHIFT(i))
  157. /* REG7 0x20 REG_ASRSTR */
  158. #define ASRSTR_DSLCNT_SHIFT 21
  159. #define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
  160. #define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
  161. #define ASRSTR_ATQOL_SHIFT 20
  162. #define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
  163. #define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
  164. #define ASRSTR_AOOLi_SHIFT(i) (17 + i)
  165. #define ASRSTR_AOOLi_MASK(i) (1 << ASRSTR_AOOLi_SHIFT(i))
  166. #define ASRSTR_AOOL(i) (1 << ASRSTR_AOOLi_SHIFT(i))
  167. #define ASRSTR_AIOLi_SHIFT(i) (14 + i)
  168. #define ASRSTR_AIOLi_MASK(i) (1 << ASRSTR_AIOLi_SHIFT(i))
  169. #define ASRSTR_AIOL(i) (1 << ASRSTR_AIOLi_SHIFT(i))
  170. #define ASRSTR_AODOi_SHIFT(i) (11 + i)
  171. #define ASRSTR_AODOi_MASK(i) (1 << ASRSTR_AODOi_SHIFT(i))
  172. #define ASRSTR_AODO(i) (1 << ASRSTR_AODOi_SHIFT(i))
  173. #define ASRSTR_AIDUi_SHIFT(i) (8 + i)
  174. #define ASRSTR_AIDUi_MASK(i) (1 << ASRSTR_AIDUi_SHIFT(i))
  175. #define ASRSTR_AIDU(i) (1 << ASRSTR_AIDUi_SHIFT(i))
  176. #define ASRSTR_FPWT_SHIFT 7
  177. #define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
  178. #define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
  179. #define ASRSTR_AOLE_SHIFT 6
  180. #define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
  181. #define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
  182. #define ASRSTR_AODEi_SHIFT(i) (3 + i)
  183. #define ASRSTR_AODFi_MASK(i) (1 << ASRSTR_AODEi_SHIFT(i))
  184. #define ASRSTR_AODF(i) (1 << ASRSTR_AODEi_SHIFT(i))
  185. #define ASRSTR_AIDEi_SHIFT(i) (0 + i)
  186. #define ASRSTR_AIDEi_MASK(i) (1 << ASRSTR_AIDEi_SHIFT(i))
  187. #define ASRSTR_AIDE(i) (1 << ASRSTR_AIDEi_SHIFT(i))
  188. /* REG10 0x54 REG_ASRTFR1 */
  189. #define ASRTFR1_TF_BASE_WIDTH 7
  190. #define ASRTFR1_TF_BASE_SHIFT 6
  191. #define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
  192. #define ASRTFR1_TF_BASE(i) ((i) << ASRTFR1_TF_BASE_SHIFT)
  193. /*
  194. * REG22 0xA0 REG_ASRMCRA
  195. * REG24 0xA8 REG_ASRMCRB
  196. * REG26 0xB0 REG_ASRMCRC
  197. */
  198. #define ASRMCRi_ZEROBUFi_SHIFT 23
  199. #define ASRMCRi_ZEROBUFi_MASK (1 << ASRMCRi_ZEROBUFi_SHIFT)
  200. #define ASRMCRi_ZEROBUFi (1 << ASRMCRi_ZEROBUFi_SHIFT)
  201. #define ASRMCRi_EXTTHRSHi_SHIFT 22
  202. #define ASRMCRi_EXTTHRSHi_MASK (1 << ASRMCRi_EXTTHRSHi_SHIFT)
  203. #define ASRMCRi_EXTTHRSHi (1 << ASRMCRi_EXTTHRSHi_SHIFT)
  204. #define ASRMCRi_BUFSTALLi_SHIFT 21
  205. #define ASRMCRi_BUFSTALLi_MASK (1 << ASRMCRi_BUFSTALLi_SHIFT)
  206. #define ASRMCRi_BUFSTALLi (1 << ASRMCRi_BUFSTALLi_SHIFT)
  207. #define ASRMCRi_BYPASSPOLYi_SHIFT 20
  208. #define ASRMCRi_BYPASSPOLYi_MASK (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
  209. #define ASRMCRi_BYPASSPOLYi (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
  210. #define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH 6
  211. #define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT 12
  212. #define ASRMCRi_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
  213. #define ASRMCRi_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
  214. #define ASRMCRi_RSYNIFi_SHIFT 11
  215. #define ASRMCRi_RSYNIFi_MASK (1 << ASRMCRi_RSYNIFi_SHIFT)
  216. #define ASRMCRi_RSYNIFi (1 << ASRMCRi_RSYNIFi_SHIFT)
  217. #define ASRMCRi_RSYNOFi_SHIFT 10
  218. #define ASRMCRi_RSYNOFi_MASK (1 << ASRMCRi_RSYNOFi_SHIFT)
  219. #define ASRMCRi_RSYNOFi (1 << ASRMCRi_RSYNOFi_SHIFT)
  220. #define ASRMCRi_INFIFO_THRESHOLD_WIDTH 6
  221. #define ASRMCRi_INFIFO_THRESHOLD_SHIFT 0
  222. #define ASRMCRi_INFIFO_THRESHOLD_MASK (((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
  223. #define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
  224. /*
  225. * REG23 0xA4 REG_ASRFSTA
  226. * REG25 0xAC REG_ASRFSTB
  227. * REG27 0xB4 REG_ASRFSTC
  228. */
  229. #define ASRFSTi_OAFi_SHIFT 23
  230. #define ASRFSTi_OAFi_MASK (1 << ASRFSTi_OAFi_SHIFT)
  231. #define ASRFSTi_OAFi (1 << ASRFSTi_OAFi_SHIFT)
  232. #define ASRFSTi_OUTPUT_FIFO_WIDTH 7
  233. #define ASRFSTi_OUTPUT_FIFO_SHIFT 12
  234. #define ASRFSTi_OUTPUT_FIFO_MASK (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
  235. #define ASRFSTi_IAEi_SHIFT 11
  236. #define ASRFSTi_IAEi_MASK (1 << ASRFSTi_IAEi_SHIFT)
  237. #define ASRFSTi_IAEi (1 << ASRFSTi_IAEi_SHIFT)
  238. #define ASRFSTi_INPUT_FIFO_WIDTH 7
  239. #define ASRFSTi_INPUT_FIFO_SHIFT 0
  240. #define ASRFSTi_INPUT_FIFO_MASK ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
  241. /* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
  242. #define ASRMCR1i_IWD_WIDTH 3
  243. #define ASRMCR1i_IWD_SHIFT 9
  244. #define ASRMCR1i_IWD_MASK (((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
  245. #define ASRMCR1i_IWD(v) ((v) << ASRMCR1i_IWD_SHIFT)
  246. #define ASRMCR1i_IMSB_SHIFT 8
  247. #define ASRMCR1i_IMSB_MASK (1 << ASRMCR1i_IMSB_SHIFT)
  248. #define ASRMCR1i_IMSB_MSB (1 << ASRMCR1i_IMSB_SHIFT)
  249. #define ASRMCR1i_IMSB_LSB (0 << ASRMCR1i_IMSB_SHIFT)
  250. #define ASRMCR1i_OMSB_SHIFT 2
  251. #define ASRMCR1i_OMSB_MASK (1 << ASRMCR1i_OMSB_SHIFT)
  252. #define ASRMCR1i_OMSB_MSB (1 << ASRMCR1i_OMSB_SHIFT)
  253. #define ASRMCR1i_OMSB_LSB (0 << ASRMCR1i_OMSB_SHIFT)
  254. #define ASRMCR1i_OSGN_SHIFT 1
  255. #define ASRMCR1i_OSGN_MASK (1 << ASRMCR1i_OSGN_SHIFT)
  256. #define ASRMCR1i_OSGN (1 << ASRMCR1i_OSGN_SHIFT)
  257. #define ASRMCR1i_OW16_SHIFT 0
  258. #define ASRMCR1i_OW16_MASK (1 << ASRMCR1i_OW16_SHIFT)
  259. #define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT)
  260. #define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
  261. enum asrc_inclk {
  262. INCLK_NONE = 0x03,
  263. INCLK_ESAI_RX = 0x00,
  264. INCLK_SSI1_RX = 0x01,
  265. INCLK_SSI2_RX = 0x02,
  266. INCLK_SSI3_RX = 0x07,
  267. INCLK_SPDIF_RX = 0x04,
  268. INCLK_MLB_CLK = 0x05,
  269. INCLK_PAD = 0x06,
  270. INCLK_ESAI_TX = 0x08,
  271. INCLK_SSI1_TX = 0x09,
  272. INCLK_SSI2_TX = 0x0a,
  273. INCLK_SSI3_TX = 0x0b,
  274. INCLK_SPDIF_TX = 0x0c,
  275. INCLK_ASRCK1_CLK = 0x0f,
  276. /* clocks for imx8 */
  277. INCLK_AUD_PLL_DIV_CLK0 = 0x10,
  278. INCLK_AUD_PLL_DIV_CLK1 = 0x11,
  279. INCLK_AUD_CLK0 = 0x12,
  280. INCLK_AUD_CLK1 = 0x13,
  281. INCLK_ESAI0_RX_CLK = 0x14,
  282. INCLK_ESAI0_TX_CLK = 0x15,
  283. INCLK_SPDIF0_RX = 0x16,
  284. INCLK_SPDIF1_RX = 0x17,
  285. INCLK_SAI0_RX_BCLK = 0x18,
  286. INCLK_SAI0_TX_BCLK = 0x19,
  287. INCLK_SAI1_RX_BCLK = 0x1a,
  288. INCLK_SAI1_TX_BCLK = 0x1b,
  289. INCLK_SAI2_RX_BCLK = 0x1c,
  290. INCLK_SAI3_RX_BCLK = 0x1d,
  291. INCLK_ASRC0_MUX_CLK = 0x1e,
  292. INCLK_ESAI1_RX_CLK = 0x20,
  293. INCLK_ESAI1_TX_CLK = 0x21,
  294. INCLK_SAI6_TX_BCLK = 0x22,
  295. INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24,
  296. INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25,
  297. };
  298. enum asrc_outclk {
  299. OUTCLK_NONE = 0x03,
  300. OUTCLK_ESAI_TX = 0x00,
  301. OUTCLK_SSI1_TX = 0x01,
  302. OUTCLK_SSI2_TX = 0x02,
  303. OUTCLK_SSI3_TX = 0x07,
  304. OUTCLK_SPDIF_TX = 0x04,
  305. OUTCLK_MLB_CLK = 0x05,
  306. OUTCLK_PAD = 0x06,
  307. OUTCLK_ESAI_RX = 0x08,
  308. OUTCLK_SSI1_RX = 0x09,
  309. OUTCLK_SSI2_RX = 0x0a,
  310. OUTCLK_SSI3_RX = 0x0b,
  311. OUTCLK_SPDIF_RX = 0x0c,
  312. OUTCLK_ASRCK1_CLK = 0x0f,
  313. /* clocks for imx8 */
  314. OUTCLK_AUD_PLL_DIV_CLK0 = 0x10,
  315. OUTCLK_AUD_PLL_DIV_CLK1 = 0x11,
  316. OUTCLK_AUD_CLK0 = 0x12,
  317. OUTCLK_AUD_CLK1 = 0x13,
  318. OUTCLK_ESAI0_RX_CLK = 0x14,
  319. OUTCLK_ESAI0_TX_CLK = 0x15,
  320. OUTCLK_SPDIF0_RX = 0x16,
  321. OUTCLK_SPDIF1_RX = 0x17,
  322. OUTCLK_SAI0_RX_BCLK = 0x18,
  323. OUTCLK_SAI0_TX_BCLK = 0x19,
  324. OUTCLK_SAI1_RX_BCLK = 0x1a,
  325. OUTCLK_SAI1_TX_BCLK = 0x1b,
  326. OUTCLK_SAI2_RX_BCLK = 0x1c,
  327. OUTCLK_SAI3_RX_BCLK = 0x1d,
  328. OUTCLK_ASRCO_MUX_CLK = 0x1e,
  329. OUTCLK_ESAI1_RX_CLK = 0x20,
  330. OUTCLK_ESAI1_TX_CLK = 0x21,
  331. OUTCLK_SAI6_TX_BCLK = 0x22,
  332. OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24,
  333. OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25,
  334. };
  335. #define ASRC_CLK_MAX_NUM 16
  336. #define ASRC_CLK_MAP_LEN 0x30
  337. enum asrc_word_width {
  338. ASRC_WIDTH_24_BIT = 0,
  339. ASRC_WIDTH_16_BIT = 1,
  340. ASRC_WIDTH_8_BIT = 2,
  341. };
  342. struct asrc_config {
  343. enum asrc_pair_index pair;
  344. unsigned int channel_num;
  345. unsigned int buffer_num;
  346. unsigned int dma_buffer_size;
  347. unsigned int input_sample_rate;
  348. unsigned int output_sample_rate;
  349. snd_pcm_format_t input_format;
  350. snd_pcm_format_t output_format;
  351. enum asrc_inclk inclk;
  352. enum asrc_outclk outclk;
  353. };
  354. struct asrc_req {
  355. unsigned int chn_num;
  356. enum asrc_pair_index index;
  357. };
  358. struct asrc_querybuf {
  359. unsigned int buffer_index;
  360. unsigned int input_length;
  361. unsigned int output_length;
  362. unsigned long input_offset;
  363. unsigned long output_offset;
  364. };
  365. struct asrc_convert_buffer {
  366. void *input_buffer_vaddr;
  367. void *output_buffer_vaddr;
  368. unsigned int input_buffer_length;
  369. unsigned int output_buffer_length;
  370. };
  371. struct asrc_status_flags {
  372. enum asrc_pair_index index;
  373. unsigned int overload_error;
  374. };
  375. enum asrc_error_status {
  376. ASRC_TASK_Q_OVERLOAD = 0x01,
  377. ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
  378. ASRC_INPUT_TASK_OVERLOAD = 0x04,
  379. ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
  380. ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
  381. };
  382. struct dma_block {
  383. dma_addr_t dma_paddr;
  384. void *dma_vaddr;
  385. unsigned int length;
  386. };
  387. /**
  388. * fsl_asrc_soc_data: soc specific data
  389. *
  390. * @use_edma: using edma as dma device or not
  391. * @channel_bits: width of ASRCNCR register for each pair
  392. */
  393. struct fsl_asrc_soc_data {
  394. bool use_edma;
  395. unsigned int channel_bits;
  396. };
  397. /**
  398. * fsl_asrc_pair_priv: ASRC Pair private data
  399. *
  400. * @config: configuration profile
  401. */
  402. struct fsl_asrc_pair_priv {
  403. struct asrc_config *config;
  404. };
  405. /**
  406. * fsl_asrc_priv: ASRC private data
  407. *
  408. * @asrck_clk: clock sources to driver ASRC internal logic
  409. * @soc: soc specific data
  410. * @clk_map: clock map for input/output clock
  411. * @regcache_cfg: store register value of REG_ASRCFG
  412. */
  413. struct fsl_asrc_priv {
  414. struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
  415. const struct fsl_asrc_soc_data *soc;
  416. unsigned char *clk_map[2];
  417. u32 regcache_cfg;
  418. };
  419. #endif /* _FSL_ASRC_H */