zx_aud96p22.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 Sanechips Technology Co., Ltd.
  4. * Copyright 2017 Linaro Ltd.
  5. *
  6. * Author: Baoyou Xie <baoyou.xie@linaro.org>
  7. */
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <sound/pcm.h>
  13. #include <sound/pcm_params.h>
  14. #include <sound/soc.h>
  15. #include <sound/soc-dai.h>
  16. #include <sound/tlv.h>
  17. #define AUD96P22_RESET 0x00
  18. #define RST_DAC_DPZ BIT(0)
  19. #define RST_ADC_DPZ BIT(1)
  20. #define AUD96P22_I2S1_CONFIG_0 0x03
  21. #define I2S1_MS_MODE BIT(3)
  22. #define I2S1_MODE_MASK 0x7
  23. #define I2S1_MODE_RIGHT_J 0x0
  24. #define I2S1_MODE_I2S 0x1
  25. #define I2S1_MODE_LEFT_J 0x2
  26. #define AUD96P22_PD_0 0x15
  27. #define AUD96P22_PD_1 0x16
  28. #define AUD96P22_PD_3 0x18
  29. #define AUD96P22_PD_4 0x19
  30. #define AUD96P22_MUTE_0 0x1d
  31. #define AUD96P22_MUTE_2 0x1f
  32. #define AUD96P22_MUTE_4 0x21
  33. #define AUD96P22_RECVOL_0 0x24
  34. #define AUD96P22_RECVOL_1 0x25
  35. #define AUD96P22_PGA1VOL_0 0x26
  36. #define AUD96P22_PGA1VOL_1 0x27
  37. #define AUD96P22_LMVOL_0 0x34
  38. #define AUD96P22_LMVOL_1 0x35
  39. #define AUD96P22_HS1VOL_0 0x38
  40. #define AUD96P22_HS1VOL_1 0x39
  41. #define AUD96P22_PGA1SEL_0 0x47
  42. #define AUD96P22_PGA1SEL_1 0x48
  43. #define AUD96P22_LDR1SEL_0 0x59
  44. #define AUD96P22_LDR1SEL_1 0x60
  45. #define AUD96P22_LDR2SEL_0 0x5d
  46. #define AUD96P22_REG_MAX 0xfb
  47. struct aud96p22_priv {
  48. struct regmap *regmap;
  49. };
  50. static int aud96p22_adc_event(struct snd_soc_dapm_widget *w,
  51. struct snd_kcontrol *kcontrol, int event)
  52. {
  53. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  54. struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
  55. struct regmap *regmap = priv->regmap;
  56. if (event != SND_SOC_DAPM_POST_PMU)
  57. return -EINVAL;
  58. /* Assert/de-assert the bit to reset ADC data path */
  59. regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, 0);
  60. regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, RST_ADC_DPZ);
  61. return 0;
  62. }
  63. static int aud96p22_dac_event(struct snd_soc_dapm_widget *w,
  64. struct snd_kcontrol *kcontrol, int event)
  65. {
  66. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  67. struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
  68. struct regmap *regmap = priv->regmap;
  69. if (event != SND_SOC_DAPM_POST_PMU)
  70. return -EINVAL;
  71. /* Assert/de-assert the bit to reset DAC data path */
  72. regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, 0);
  73. regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, RST_DAC_DPZ);
  74. return 0;
  75. }
  76. static const DECLARE_TLV_DB_SCALE(lm_tlv, -11550, 50, 0);
  77. static const DECLARE_TLV_DB_SCALE(hs_tlv, -3900, 300, 0);
  78. static const DECLARE_TLV_DB_SCALE(rec_tlv, -9550, 50, 0);
  79. static const DECLARE_TLV_DB_SCALE(pga_tlv, -1800, 100, 0);
  80. static const struct snd_kcontrol_new aud96p22_snd_controls[] = {
  81. /* Volume control */
  82. SOC_DOUBLE_R_TLV("Master Playback Volume", AUD96P22_LMVOL_0,
  83. AUD96P22_LMVOL_1, 0, 0xff, 0, lm_tlv),
  84. SOC_DOUBLE_R_TLV("Headphone Volume", AUD96P22_HS1VOL_0,
  85. AUD96P22_HS1VOL_1, 0, 0xf, 0, hs_tlv),
  86. SOC_DOUBLE_R_TLV("Master Capture Volume", AUD96P22_RECVOL_0,
  87. AUD96P22_RECVOL_1, 0, 0xff, 0, rec_tlv),
  88. SOC_DOUBLE_R_TLV("Analogue Capture Volume", AUD96P22_PGA1VOL_0,
  89. AUD96P22_PGA1VOL_1, 0, 0x37, 0, pga_tlv),
  90. /* Mute control */
  91. SOC_DOUBLE("Master Playback Switch", AUD96P22_MUTE_2, 0, 1, 1, 1),
  92. SOC_DOUBLE("Headphone Switch", AUD96P22_MUTE_2, 4, 5, 1, 1),
  93. SOC_DOUBLE("Line Out Switch", AUD96P22_MUTE_4, 0, 1, 1, 1),
  94. SOC_DOUBLE("Speaker Switch", AUD96P22_MUTE_4, 2, 3, 1, 1),
  95. SOC_DOUBLE("Master Capture Switch", AUD96P22_MUTE_0, 0, 1, 1, 1),
  96. SOC_DOUBLE("Analogue Capture Switch", AUD96P22_MUTE_0, 2, 3, 1, 1),
  97. };
  98. /* Input mux kcontrols */
  99. static const unsigned int ain_mux_values[] = {
  100. 0, 1, 3, 4, 5,
  101. };
  102. static const char * const ainl_mux_texts[] = {
  103. "AINL1 differential",
  104. "AINL1 single-ended",
  105. "AINL3 single-ended",
  106. "AINL2 differential",
  107. "AINL2 single-ended",
  108. };
  109. static const char * const ainr_mux_texts[] = {
  110. "AINR1 differential",
  111. "AINR1 single-ended",
  112. "AINR3 single-ended",
  113. "AINR2 differential",
  114. "AINR2 single-ended",
  115. };
  116. static SOC_VALUE_ENUM_SINGLE_DECL(ainl_mux_enum, AUD96P22_PGA1SEL_0,
  117. 0, 0x7, ainl_mux_texts, ain_mux_values);
  118. static SOC_VALUE_ENUM_SINGLE_DECL(ainr_mux_enum, AUD96P22_PGA1SEL_1,
  119. 0, 0x7, ainr_mux_texts, ain_mux_values);
  120. static const struct snd_kcontrol_new ainl_mux_kcontrol =
  121. SOC_DAPM_ENUM("AINL Mux", ainl_mux_enum);
  122. static const struct snd_kcontrol_new ainr_mux_kcontrol =
  123. SOC_DAPM_ENUM("AINR Mux", ainr_mux_enum);
  124. /* Output mixer kcontrols */
  125. static const struct snd_kcontrol_new ld1_left_kcontrols[] = {
  126. SOC_DAPM_SINGLE("DACL LD1L Switch", AUD96P22_LDR1SEL_0, 0, 1, 0),
  127. SOC_DAPM_SINGLE("AINL LD1L Switch", AUD96P22_LDR1SEL_0, 1, 1, 0),
  128. SOC_DAPM_SINGLE("AINR LD1L Switch", AUD96P22_LDR1SEL_0, 2, 1, 0),
  129. };
  130. static const struct snd_kcontrol_new ld1_right_kcontrols[] = {
  131. SOC_DAPM_SINGLE("DACR LD1R Switch", AUD96P22_LDR1SEL_1, 8, 1, 0),
  132. SOC_DAPM_SINGLE("AINR LD1R Switch", AUD96P22_LDR1SEL_1, 9, 1, 0),
  133. SOC_DAPM_SINGLE("AINL LD1R Switch", AUD96P22_LDR1SEL_1, 10, 1, 0),
  134. };
  135. static const struct snd_kcontrol_new ld2_kcontrols[] = {
  136. SOC_DAPM_SINGLE("DACL LD2 Switch", AUD96P22_LDR2SEL_0, 0, 1, 0),
  137. SOC_DAPM_SINGLE("AINL LD2 Switch", AUD96P22_LDR2SEL_0, 1, 1, 0),
  138. SOC_DAPM_SINGLE("DACR LD2 Switch", AUD96P22_LDR2SEL_0, 2, 1, 0),
  139. };
  140. static const struct snd_soc_dapm_widget aud96p22_dapm_widgets[] = {
  141. /* Overall power bit */
  142. SND_SOC_DAPM_SUPPLY("POWER", AUD96P22_PD_0, 0, 0, NULL, 0),
  143. /* Input pins */
  144. SND_SOC_DAPM_INPUT("AINL1P"),
  145. SND_SOC_DAPM_INPUT("AINL2P"),
  146. SND_SOC_DAPM_INPUT("AINL3"),
  147. SND_SOC_DAPM_INPUT("AINL1N"),
  148. SND_SOC_DAPM_INPUT("AINL2N"),
  149. SND_SOC_DAPM_INPUT("AINR2N"),
  150. SND_SOC_DAPM_INPUT("AINR1N"),
  151. SND_SOC_DAPM_INPUT("AINR3"),
  152. SND_SOC_DAPM_INPUT("AINR2P"),
  153. SND_SOC_DAPM_INPUT("AINR1P"),
  154. /* Input muxes */
  155. SND_SOC_DAPM_MUX("AINLMUX", AUD96P22_PD_1, 2, 0, &ainl_mux_kcontrol),
  156. SND_SOC_DAPM_MUX("AINRMUX", AUD96P22_PD_1, 3, 0, &ainr_mux_kcontrol),
  157. /* ADCs */
  158. SND_SOC_DAPM_ADC_E("ADCL", "Capture Left", AUD96P22_PD_1, 0, 0,
  159. aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
  160. SND_SOC_DAPM_ADC_E("ADCR", "Capture Right", AUD96P22_PD_1, 1, 0,
  161. aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
  162. /* DACs */
  163. SND_SOC_DAPM_DAC_E("DACL", "Playback Left", AUD96P22_PD_3, 0, 0,
  164. aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
  165. SND_SOC_DAPM_DAC_E("DACR", "Playback Right", AUD96P22_PD_3, 1, 0,
  166. aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
  167. /* Output mixers */
  168. SND_SOC_DAPM_MIXER("LD1L", AUD96P22_PD_3, 6, 0, ld1_left_kcontrols,
  169. ARRAY_SIZE(ld1_left_kcontrols)),
  170. SND_SOC_DAPM_MIXER("LD1R", AUD96P22_PD_3, 7, 0, ld1_right_kcontrols,
  171. ARRAY_SIZE(ld1_right_kcontrols)),
  172. SND_SOC_DAPM_MIXER("LD2", AUD96P22_PD_4, 2, 0, ld2_kcontrols,
  173. ARRAY_SIZE(ld2_kcontrols)),
  174. /* Headset power switch */
  175. SND_SOC_DAPM_SUPPLY("HS1L", AUD96P22_PD_3, 4, 0, NULL, 0),
  176. SND_SOC_DAPM_SUPPLY("HS1R", AUD96P22_PD_3, 5, 0, NULL, 0),
  177. /* Output pins */
  178. SND_SOC_DAPM_OUTPUT("HSOUTL"),
  179. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  180. SND_SOC_DAPM_OUTPUT("LINEOUTMP"),
  181. SND_SOC_DAPM_OUTPUT("LINEOUTMN"),
  182. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  183. SND_SOC_DAPM_OUTPUT("HSOUTR"),
  184. };
  185. static const struct snd_soc_dapm_route aud96p22_dapm_routes[] = {
  186. { "AINLMUX", "AINL1 differential", "AINL1N" },
  187. { "AINLMUX", "AINL1 single-ended", "AINL1P" },
  188. { "AINLMUX", "AINL3 single-ended", "AINL3" },
  189. { "AINLMUX", "AINL2 differential", "AINL2N" },
  190. { "AINLMUX", "AINL2 single-ended", "AINL2P" },
  191. { "AINRMUX", "AINR1 differential", "AINR1N" },
  192. { "AINRMUX", "AINR1 single-ended", "AINR1P" },
  193. { "AINRMUX", "AINR3 single-ended", "AINR3" },
  194. { "AINRMUX", "AINR2 differential", "AINR2N" },
  195. { "AINRMUX", "AINR2 single-ended", "AINR2P" },
  196. { "ADCL", NULL, "AINLMUX" },
  197. { "ADCR", NULL, "AINRMUX" },
  198. { "ADCL", NULL, "POWER" },
  199. { "ADCR", NULL, "POWER" },
  200. { "DACL", NULL, "POWER" },
  201. { "DACR", NULL, "POWER" },
  202. { "LD1L", "DACL LD1L Switch", "DACL" },
  203. { "LD1L", "AINL LD1L Switch", "AINLMUX" },
  204. { "LD1L", "AINR LD1L Switch", "AINRMUX" },
  205. { "LD1R", "DACR LD1R Switch", "DACR" },
  206. { "LD1R", "AINR LD1R Switch", "AINRMUX" },
  207. { "LD1R", "AINL LD1R Switch", "AINLMUX" },
  208. { "LD2", "DACL LD2 Switch", "DACL" },
  209. { "LD2", "AINL LD2 Switch", "AINLMUX" },
  210. { "LD2", "DACR LD2 Switch", "DACR" },
  211. { "HSOUTL", NULL, "LD1L" },
  212. { "HSOUTR", NULL, "LD1R" },
  213. { "HSOUTL", NULL, "HS1L" },
  214. { "HSOUTR", NULL, "HS1R" },
  215. { "LINEOUTL", NULL, "LD1L" },
  216. { "LINEOUTR", NULL, "LD1R" },
  217. { "LINEOUTMP", NULL, "LD2" },
  218. { "LINEOUTMN", NULL, "LD2" },
  219. };
  220. static const struct snd_soc_component_driver aud96p22_driver = {
  221. .controls = aud96p22_snd_controls,
  222. .num_controls = ARRAY_SIZE(aud96p22_snd_controls),
  223. .dapm_widgets = aud96p22_dapm_widgets,
  224. .num_dapm_widgets = ARRAY_SIZE(aud96p22_dapm_widgets),
  225. .dapm_routes = aud96p22_dapm_routes,
  226. .num_dapm_routes = ARRAY_SIZE(aud96p22_dapm_routes),
  227. .idle_bias_on = 1,
  228. .use_pmdown_time = 1,
  229. .endianness = 1,
  230. .non_legacy_dai_naming = 1,
  231. };
  232. static int aud96p22_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  233. {
  234. struct aud96p22_priv *priv = snd_soc_component_get_drvdata(dai->component);
  235. struct regmap *regmap = priv->regmap;
  236. unsigned int val;
  237. /* Master/slave mode */
  238. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  239. case SND_SOC_DAIFMT_CBS_CFS:
  240. val = 0;
  241. break;
  242. case SND_SOC_DAIFMT_CBM_CFM:
  243. val = I2S1_MS_MODE;
  244. break;
  245. default:
  246. return -EINVAL;
  247. }
  248. regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MS_MODE, val);
  249. /* Audio format */
  250. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  251. case SND_SOC_DAIFMT_RIGHT_J:
  252. val = I2S1_MODE_RIGHT_J;
  253. break;
  254. case SND_SOC_DAIFMT_I2S:
  255. val = I2S1_MODE_I2S;
  256. break;
  257. case SND_SOC_DAIFMT_LEFT_J:
  258. val = I2S1_MODE_LEFT_J;
  259. break;
  260. default:
  261. return -EINVAL;
  262. }
  263. regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MODE_MASK, val);
  264. return 0;
  265. }
  266. static const struct snd_soc_dai_ops aud96p22_dai_ops = {
  267. .set_fmt = aud96p22_set_fmt,
  268. };
  269. #define AUD96P22_RATES SNDRV_PCM_RATE_8000_192000
  270. #define AUD96P22_FORMATS (\
  271. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
  272. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
  273. static struct snd_soc_dai_driver aud96p22_dai = {
  274. .name = "aud96p22-dai",
  275. .playback = {
  276. .stream_name = "Playback",
  277. .channels_min = 1,
  278. .channels_max = 2,
  279. .rates = AUD96P22_RATES,
  280. .formats = AUD96P22_FORMATS,
  281. },
  282. .capture = {
  283. .stream_name = "Capture",
  284. .channels_min = 1,
  285. .channels_max = 2,
  286. .rates = AUD96P22_RATES,
  287. .formats = AUD96P22_FORMATS,
  288. },
  289. .ops = &aud96p22_dai_ops,
  290. };
  291. static const struct regmap_config aud96p22_regmap = {
  292. .reg_bits = 8,
  293. .val_bits = 8,
  294. .max_register = AUD96P22_REG_MAX,
  295. .cache_type = REGCACHE_RBTREE,
  296. };
  297. static int aud96p22_i2c_probe(struct i2c_client *i2c,
  298. const struct i2c_device_id *id)
  299. {
  300. struct device *dev = &i2c->dev;
  301. struct aud96p22_priv *priv;
  302. int ret;
  303. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  304. if (priv == NULL)
  305. return -ENOMEM;
  306. priv->regmap = devm_regmap_init_i2c(i2c, &aud96p22_regmap);
  307. if (IS_ERR(priv->regmap)) {
  308. ret = PTR_ERR(priv->regmap);
  309. dev_err(dev, "failed to init i2c regmap: %d\n", ret);
  310. return ret;
  311. }
  312. i2c_set_clientdata(i2c, priv);
  313. ret = devm_snd_soc_register_component(dev, &aud96p22_driver, &aud96p22_dai, 1);
  314. if (ret) {
  315. dev_err(dev, "failed to register component: %d\n", ret);
  316. return ret;
  317. }
  318. return 0;
  319. }
  320. static int aud96p22_i2c_remove(struct i2c_client *i2c)
  321. {
  322. return 0;
  323. }
  324. static const struct of_device_id aud96p22_dt_ids[] = {
  325. { .compatible = "zte,zx-aud96p22", },
  326. { }
  327. };
  328. MODULE_DEVICE_TABLE(of, aud96p22_dt_ids);
  329. static struct i2c_driver aud96p22_i2c_driver = {
  330. .driver = {
  331. .name = "zx_aud96p22",
  332. .of_match_table = aud96p22_dt_ids,
  333. },
  334. .probe = aud96p22_i2c_probe,
  335. .remove = aud96p22_i2c_remove,
  336. };
  337. module_i2c_driver(aud96p22_i2c_driver);
  338. MODULE_DESCRIPTION("ZTE ASoC AUD96P22 CODEC driver");
  339. MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
  340. MODULE_LICENSE("GPL v2");