wm8996.c 93 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm8996.c - WM8996 audio codec interface
  4. *
  5. * Copyright 2011-2 Wolfson Microelectronics PLC.
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/init.h>
  11. #include <linux/completion.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/gcd.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/gpio.h>
  17. #include <linux/i2c.h>
  18. #include <linux/regmap.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <linux/workqueue.h>
  22. #include <sound/core.h>
  23. #include <sound/jack.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include <trace/events/asoc.h>
  30. #include <sound/wm8996.h>
  31. #include "wm8996.h"
  32. #define WM8996_AIFS 2
  33. #define HPOUT1L 1
  34. #define HPOUT1R 2
  35. #define HPOUT2L 4
  36. #define HPOUT2R 8
  37. #define WM8996_NUM_SUPPLIES 3
  38. static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
  39. "DBVDD",
  40. "AVDD1",
  41. "AVDD2",
  42. };
  43. struct wm8996_priv {
  44. struct device *dev;
  45. struct regmap *regmap;
  46. struct snd_soc_component *component;
  47. int ldo1ena;
  48. int sysclk;
  49. int sysclk_src;
  50. int fll_src;
  51. int fll_fref;
  52. int fll_fout;
  53. struct completion fll_lock;
  54. u16 dcs_pending;
  55. struct completion dcs_done;
  56. u16 hpout_ena;
  57. u16 hpout_pending;
  58. struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
  59. struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
  60. int bg_ena;
  61. struct wm8996_pdata pdata;
  62. int rx_rate[WM8996_AIFS];
  63. int bclk_rate[WM8996_AIFS];
  64. /* Platform dependant ReTune mobile configuration */
  65. int num_retune_mobile_texts;
  66. const char **retune_mobile_texts;
  67. int retune_mobile_cfg[2];
  68. struct soc_enum retune_mobile_enum;
  69. struct snd_soc_jack *jack;
  70. bool detecting;
  71. bool jack_mic;
  72. int jack_flips;
  73. wm8996_polarity_fn polarity_cb;
  74. #ifdef CONFIG_GPIOLIB
  75. struct gpio_chip gpio_chip;
  76. #endif
  77. };
  78. /* We can't use the same notifier block for more than one supply and
  79. * there's no way I can see to get from a callback to the caller
  80. * except container_of().
  81. */
  82. #define WM8996_REGULATOR_EVENT(n) \
  83. static int wm8996_regulator_event_##n(struct notifier_block *nb, \
  84. unsigned long event, void *data) \
  85. { \
  86. struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
  87. disable_nb[n]); \
  88. if (event & REGULATOR_EVENT_DISABLE) { \
  89. regcache_mark_dirty(wm8996->regmap); \
  90. } \
  91. return 0; \
  92. }
  93. WM8996_REGULATOR_EVENT(0)
  94. WM8996_REGULATOR_EVENT(1)
  95. WM8996_REGULATOR_EVENT(2)
  96. static const struct reg_default wm8996_reg[] = {
  97. { WM8996_POWER_MANAGEMENT_1, 0x0 },
  98. { WM8996_POWER_MANAGEMENT_2, 0x0 },
  99. { WM8996_POWER_MANAGEMENT_3, 0x0 },
  100. { WM8996_POWER_MANAGEMENT_4, 0x0 },
  101. { WM8996_POWER_MANAGEMENT_5, 0x0 },
  102. { WM8996_POWER_MANAGEMENT_6, 0x0 },
  103. { WM8996_POWER_MANAGEMENT_7, 0x10 },
  104. { WM8996_POWER_MANAGEMENT_8, 0x0 },
  105. { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
  106. { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
  107. { WM8996_LINE_INPUT_CONTROL, 0x0 },
  108. { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
  109. { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
  110. { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
  111. { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
  112. { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
  113. { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
  114. { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
  115. { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
  116. { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
  117. { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
  118. { WM8996_MICBIAS_1, 0x39 },
  119. { WM8996_MICBIAS_2, 0x39 },
  120. { WM8996_LDO_1, 0x3 },
  121. { WM8996_LDO_2, 0x13 },
  122. { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
  123. { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
  124. { WM8996_HEADPHONE_DETECT_1, 0x20 },
  125. { WM8996_HEADPHONE_DETECT_2, 0x0 },
  126. { WM8996_MIC_DETECT_1, 0x7600 },
  127. { WM8996_MIC_DETECT_2, 0xbf },
  128. { WM8996_CHARGE_PUMP_1, 0x1f25 },
  129. { WM8996_CHARGE_PUMP_2, 0xab19 },
  130. { WM8996_DC_SERVO_1, 0x0 },
  131. { WM8996_DC_SERVO_3, 0x0 },
  132. { WM8996_DC_SERVO_5, 0x2a2a },
  133. { WM8996_DC_SERVO_6, 0x0 },
  134. { WM8996_DC_SERVO_7, 0x0 },
  135. { WM8996_ANALOGUE_HP_1, 0x0 },
  136. { WM8996_ANALOGUE_HP_2, 0x0 },
  137. { WM8996_CONTROL_INTERFACE_1, 0x8004 },
  138. { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
  139. { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
  140. { WM8996_AIF_CLOCKING_1, 0x0 },
  141. { WM8996_AIF_CLOCKING_2, 0x0 },
  142. { WM8996_CLOCKING_1, 0x10 },
  143. { WM8996_CLOCKING_2, 0x0 },
  144. { WM8996_AIF_RATE, 0x83 },
  145. { WM8996_FLL_CONTROL_1, 0x0 },
  146. { WM8996_FLL_CONTROL_2, 0x0 },
  147. { WM8996_FLL_CONTROL_3, 0x0 },
  148. { WM8996_FLL_CONTROL_4, 0x5dc0 },
  149. { WM8996_FLL_CONTROL_5, 0xc84 },
  150. { WM8996_FLL_EFS_1, 0x0 },
  151. { WM8996_FLL_EFS_2, 0x2 },
  152. { WM8996_AIF1_CONTROL, 0x0 },
  153. { WM8996_AIF1_BCLK, 0x0 },
  154. { WM8996_AIF1_TX_LRCLK_1, 0x80 },
  155. { WM8996_AIF1_TX_LRCLK_2, 0x8 },
  156. { WM8996_AIF1_RX_LRCLK_1, 0x80 },
  157. { WM8996_AIF1_RX_LRCLK_2, 0x0 },
  158. { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
  159. { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
  160. { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
  161. { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
  162. { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
  163. { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
  164. { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
  165. { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
  166. { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
  167. { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
  168. { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
  169. { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
  170. { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
  171. { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
  172. { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
  173. { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
  174. { WM8996_AIF1TX_TEST, 0x7 },
  175. { WM8996_AIF2_CONTROL, 0x0 },
  176. { WM8996_AIF2_BCLK, 0x0 },
  177. { WM8996_AIF2_TX_LRCLK_1, 0x80 },
  178. { WM8996_AIF2_TX_LRCLK_2, 0x8 },
  179. { WM8996_AIF2_RX_LRCLK_1, 0x80 },
  180. { WM8996_AIF2_RX_LRCLK_2, 0x0 },
  181. { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
  182. { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
  183. { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
  184. { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
  185. { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
  186. { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
  187. { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
  188. { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
  189. { WM8996_AIF2TX_TEST, 0x1 },
  190. { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
  191. { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
  192. { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
  193. { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
  194. { WM8996_DSP1_TX_FILTERS, 0x2000 },
  195. { WM8996_DSP1_RX_FILTERS_1, 0x200 },
  196. { WM8996_DSP1_RX_FILTERS_2, 0x10 },
  197. { WM8996_DSP1_DRC_1, 0x98 },
  198. { WM8996_DSP1_DRC_2, 0x845 },
  199. { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
  200. { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
  201. { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
  202. { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
  203. { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
  204. { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
  205. { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
  206. { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
  207. { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
  208. { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
  209. { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
  210. { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
  211. { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
  212. { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
  213. { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
  214. { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
  215. { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
  216. { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
  217. { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
  218. { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
  219. { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
  220. { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
  221. { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
  222. { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
  223. { WM8996_DSP2_TX_FILTERS, 0x2000 },
  224. { WM8996_DSP2_RX_FILTERS_1, 0x200 },
  225. { WM8996_DSP2_RX_FILTERS_2, 0x10 },
  226. { WM8996_DSP2_DRC_1, 0x98 },
  227. { WM8996_DSP2_DRC_2, 0x845 },
  228. { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
  229. { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
  230. { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
  231. { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
  232. { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
  233. { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
  234. { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
  235. { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
  236. { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
  237. { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
  238. { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
  239. { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
  240. { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
  241. { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
  242. { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
  243. { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
  244. { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
  245. { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
  246. { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
  247. { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
  248. { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
  249. { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
  250. { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
  251. { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
  252. { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
  253. { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
  254. { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
  255. { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
  256. { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
  257. { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
  258. { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
  259. { WM8996_DAC_SOFTMUTE, 0x0 },
  260. { WM8996_OVERSAMPLING, 0xd },
  261. { WM8996_SIDETONE, 0x1040 },
  262. { WM8996_GPIO_1, 0xa101 },
  263. { WM8996_GPIO_2, 0xa101 },
  264. { WM8996_GPIO_3, 0xa101 },
  265. { WM8996_GPIO_4, 0xa101 },
  266. { WM8996_GPIO_5, 0xa101 },
  267. { WM8996_PULL_CONTROL_1, 0x0 },
  268. { WM8996_PULL_CONTROL_2, 0x140 },
  269. { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
  270. { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
  271. { WM8996_LEFT_PDM_SPEAKER, 0x0 },
  272. { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
  273. { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
  274. { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
  275. };
  276. static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
  277. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
  278. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  279. static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
  280. static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
  281. static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
  282. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  283. static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
  284. static const char *sidetone_hpf_text[] = {
  285. "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
  286. };
  287. static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
  288. WM8996_SIDETONE, 7, sidetone_hpf_text);
  289. static const char *hpf_mode_text[] = {
  290. "HiFi", "Custom", "Voice"
  291. };
  292. static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
  293. WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text);
  294. static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
  295. WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text);
  296. static const char *hpf_cutoff_text[] = {
  297. "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
  298. };
  299. static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
  300. WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text);
  301. static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
  302. WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text);
  303. static void wm8996_set_retune_mobile(struct snd_soc_component *component, int block)
  304. {
  305. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  306. struct wm8996_pdata *pdata = &wm8996->pdata;
  307. int base, best, best_val, save, i, cfg, iface;
  308. if (!wm8996->num_retune_mobile_texts)
  309. return;
  310. switch (block) {
  311. case 0:
  312. base = WM8996_DSP1_RX_EQ_GAINS_1;
  313. if (snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_8) &
  314. WM8996_DSP1RX_SRC)
  315. iface = 1;
  316. else
  317. iface = 0;
  318. break;
  319. case 1:
  320. base = WM8996_DSP1_RX_EQ_GAINS_2;
  321. if (snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_8) &
  322. WM8996_DSP2RX_SRC)
  323. iface = 1;
  324. else
  325. iface = 0;
  326. break;
  327. default:
  328. return;
  329. }
  330. /* Find the version of the currently selected configuration
  331. * with the nearest sample rate. */
  332. cfg = wm8996->retune_mobile_cfg[block];
  333. best = 0;
  334. best_val = INT_MAX;
  335. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  336. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  337. wm8996->retune_mobile_texts[cfg]) == 0 &&
  338. abs(pdata->retune_mobile_cfgs[i].rate
  339. - wm8996->rx_rate[iface]) < best_val) {
  340. best = i;
  341. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  342. - wm8996->rx_rate[iface]);
  343. }
  344. }
  345. dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
  346. block,
  347. pdata->retune_mobile_cfgs[best].name,
  348. pdata->retune_mobile_cfgs[best].rate,
  349. wm8996->rx_rate[iface]);
  350. /* The EQ will be disabled while reconfiguring it, remember the
  351. * current configuration.
  352. */
  353. save = snd_soc_component_read(component, base);
  354. save &= WM8996_DSP1RX_EQ_ENA;
  355. for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
  356. snd_soc_component_update_bits(component, base + i, 0xffff,
  357. pdata->retune_mobile_cfgs[best].regs[i]);
  358. snd_soc_component_update_bits(component, base, WM8996_DSP1RX_EQ_ENA, save);
  359. }
  360. /* Icky as hell but saves code duplication */
  361. static int wm8996_get_retune_mobile_block(const char *name)
  362. {
  363. if (strcmp(name, "DSP1 EQ Mode") == 0)
  364. return 0;
  365. if (strcmp(name, "DSP2 EQ Mode") == 0)
  366. return 1;
  367. return -EINVAL;
  368. }
  369. static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  370. struct snd_ctl_elem_value *ucontrol)
  371. {
  372. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  373. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  374. struct wm8996_pdata *pdata = &wm8996->pdata;
  375. int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
  376. int value = ucontrol->value.enumerated.item[0];
  377. if (block < 0)
  378. return block;
  379. if (value >= pdata->num_retune_mobile_cfgs)
  380. return -EINVAL;
  381. wm8996->retune_mobile_cfg[block] = value;
  382. wm8996_set_retune_mobile(component, block);
  383. return 0;
  384. }
  385. static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  386. struct snd_ctl_elem_value *ucontrol)
  387. {
  388. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  389. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  390. int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
  391. if (block < 0)
  392. return block;
  393. ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
  394. return 0;
  395. }
  396. static const struct snd_kcontrol_new wm8996_snd_controls[] = {
  397. SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
  398. WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
  399. SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
  400. WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
  401. SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
  402. 0, 5, 24, 0, sidetone_tlv),
  403. SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
  404. 0, 5, 24, 0, sidetone_tlv),
  405. SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
  406. SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
  407. SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
  408. SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
  409. WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  410. SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
  411. WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  412. SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
  413. 13, 1, 0),
  414. SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
  415. SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
  416. SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
  417. SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
  418. 13, 1, 0),
  419. SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
  420. SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
  421. SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
  422. SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
  423. WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
  424. SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
  425. SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
  426. WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
  427. SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
  428. SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
  429. WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
  430. SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
  431. WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
  432. SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
  433. WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
  434. SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
  435. WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
  436. SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
  437. SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
  438. SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
  439. SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
  440. SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
  441. SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
  442. SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
  443. SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
  444. SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
  445. 0, threedstereo_tlv),
  446. SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
  447. 0, threedstereo_tlv),
  448. SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
  449. 8, 0, out_digital_tlv),
  450. SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
  451. 8, 0, out_digital_tlv),
  452. SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
  453. WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
  454. SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
  455. WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
  456. SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
  457. WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
  458. SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
  459. WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
  460. SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
  461. spk_tlv),
  462. SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
  463. WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
  464. SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
  465. WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
  466. SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
  467. SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
  468. SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
  469. SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
  470. SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
  471. SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
  472. WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
  473. WM8996_DSP1TXR_DRC_ENA),
  474. SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
  475. SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
  476. SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
  477. SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
  478. WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
  479. WM8996_DSP2TXR_DRC_ENA),
  480. };
  481. static const struct snd_kcontrol_new wm8996_eq_controls[] = {
  482. SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
  483. eq_tlv),
  484. SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
  485. eq_tlv),
  486. SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
  487. eq_tlv),
  488. SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
  489. eq_tlv),
  490. SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
  491. eq_tlv),
  492. SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
  493. eq_tlv),
  494. SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
  495. eq_tlv),
  496. SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
  497. eq_tlv),
  498. SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
  499. eq_tlv),
  500. SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
  501. eq_tlv),
  502. };
  503. static void wm8996_bg_enable(struct snd_soc_component *component)
  504. {
  505. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  506. wm8996->bg_ena++;
  507. if (wm8996->bg_ena == 1) {
  508. snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1,
  509. WM8996_BG_ENA, WM8996_BG_ENA);
  510. msleep(2);
  511. }
  512. }
  513. static void wm8996_bg_disable(struct snd_soc_component *component)
  514. {
  515. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  516. wm8996->bg_ena--;
  517. if (!wm8996->bg_ena)
  518. snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1,
  519. WM8996_BG_ENA, 0);
  520. }
  521. static int bg_event(struct snd_soc_dapm_widget *w,
  522. struct snd_kcontrol *kcontrol, int event)
  523. {
  524. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  525. int ret = 0;
  526. switch (event) {
  527. case SND_SOC_DAPM_PRE_PMU:
  528. wm8996_bg_enable(component);
  529. break;
  530. case SND_SOC_DAPM_POST_PMD:
  531. wm8996_bg_disable(component);
  532. break;
  533. default:
  534. WARN(1, "Invalid event %d\n", event);
  535. ret = -EINVAL;
  536. }
  537. return ret;
  538. }
  539. static int cp_event(struct snd_soc_dapm_widget *w,
  540. struct snd_kcontrol *kcontrol, int event)
  541. {
  542. switch (event) {
  543. case SND_SOC_DAPM_POST_PMU:
  544. msleep(5);
  545. break;
  546. default:
  547. WARN(1, "Invalid event %d\n", event);
  548. }
  549. return 0;
  550. }
  551. static int rmv_short_event(struct snd_soc_dapm_widget *w,
  552. struct snd_kcontrol *kcontrol, int event)
  553. {
  554. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  555. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  556. /* Record which outputs we enabled */
  557. switch (event) {
  558. case SND_SOC_DAPM_PRE_PMD:
  559. wm8996->hpout_pending &= ~w->shift;
  560. break;
  561. case SND_SOC_DAPM_PRE_PMU:
  562. wm8996->hpout_pending |= w->shift;
  563. break;
  564. default:
  565. WARN(1, "Invalid event %d\n", event);
  566. return -EINVAL;
  567. }
  568. return 0;
  569. }
  570. static void wait_for_dc_servo(struct snd_soc_component *component, u16 mask)
  571. {
  572. struct i2c_client *i2c = to_i2c_client(component->dev);
  573. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  574. int ret;
  575. unsigned long timeout = 200;
  576. snd_soc_component_write(component, WM8996_DC_SERVO_2, mask);
  577. /* Use the interrupt if possible */
  578. do {
  579. if (i2c->irq) {
  580. timeout = wait_for_completion_timeout(&wm8996->dcs_done,
  581. msecs_to_jiffies(200));
  582. if (timeout == 0)
  583. dev_err(component->dev, "DC servo timed out\n");
  584. } else {
  585. msleep(1);
  586. timeout--;
  587. }
  588. ret = snd_soc_component_read(component, WM8996_DC_SERVO_2);
  589. dev_dbg(component->dev, "DC servo state: %x\n", ret);
  590. } while (timeout && ret & mask);
  591. if (timeout == 0)
  592. dev_err(component->dev, "DC servo timed out for %x\n", mask);
  593. else
  594. dev_dbg(component->dev, "DC servo complete for %x\n", mask);
  595. }
  596. static void wm8996_seq_notifier(struct snd_soc_component *component,
  597. enum snd_soc_dapm_type event, int subseq)
  598. {
  599. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  600. u16 val, mask;
  601. /* Complete any pending DC servo starts */
  602. if (wm8996->dcs_pending) {
  603. dev_dbg(component->dev, "Starting DC servo for %x\n",
  604. wm8996->dcs_pending);
  605. /* Trigger a startup sequence */
  606. wait_for_dc_servo(component, wm8996->dcs_pending
  607. << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
  608. wm8996->dcs_pending = 0;
  609. }
  610. if (wm8996->hpout_pending != wm8996->hpout_ena) {
  611. dev_dbg(component->dev, "Applying RMV_SHORTs %x->%x\n",
  612. wm8996->hpout_ena, wm8996->hpout_pending);
  613. val = 0;
  614. mask = 0;
  615. if (wm8996->hpout_pending & HPOUT1L) {
  616. val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
  617. mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
  618. } else {
  619. mask |= WM8996_HPOUT1L_RMV_SHORT |
  620. WM8996_HPOUT1L_OUTP |
  621. WM8996_HPOUT1L_DLY;
  622. }
  623. if (wm8996->hpout_pending & HPOUT1R) {
  624. val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
  625. mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
  626. } else {
  627. mask |= WM8996_HPOUT1R_RMV_SHORT |
  628. WM8996_HPOUT1R_OUTP |
  629. WM8996_HPOUT1R_DLY;
  630. }
  631. snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, mask, val);
  632. val = 0;
  633. mask = 0;
  634. if (wm8996->hpout_pending & HPOUT2L) {
  635. val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
  636. mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
  637. } else {
  638. mask |= WM8996_HPOUT2L_RMV_SHORT |
  639. WM8996_HPOUT2L_OUTP |
  640. WM8996_HPOUT2L_DLY;
  641. }
  642. if (wm8996->hpout_pending & HPOUT2R) {
  643. val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
  644. mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
  645. } else {
  646. mask |= WM8996_HPOUT2R_RMV_SHORT |
  647. WM8996_HPOUT2R_OUTP |
  648. WM8996_HPOUT2R_DLY;
  649. }
  650. snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_2, mask, val);
  651. wm8996->hpout_ena = wm8996->hpout_pending;
  652. }
  653. }
  654. static int dcs_start(struct snd_soc_dapm_widget *w,
  655. struct snd_kcontrol *kcontrol, int event)
  656. {
  657. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  658. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  659. switch (event) {
  660. case SND_SOC_DAPM_POST_PMU:
  661. wm8996->dcs_pending |= 1 << w->shift;
  662. break;
  663. default:
  664. WARN(1, "Invalid event %d\n", event);
  665. return -EINVAL;
  666. }
  667. return 0;
  668. }
  669. static const char *sidetone_text[] = {
  670. "IN1", "IN2",
  671. };
  672. static SOC_ENUM_SINGLE_DECL(left_sidetone_enum,
  673. WM8996_SIDETONE, 0, sidetone_text);
  674. static const struct snd_kcontrol_new left_sidetone =
  675. SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
  676. static SOC_ENUM_SINGLE_DECL(right_sidetone_enum,
  677. WM8996_SIDETONE, 1, sidetone_text);
  678. static const struct snd_kcontrol_new right_sidetone =
  679. SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
  680. static const char *spk_text[] = {
  681. "DAC1L", "DAC1R", "DAC2L", "DAC2R"
  682. };
  683. static SOC_ENUM_SINGLE_DECL(spkl_enum,
  684. WM8996_LEFT_PDM_SPEAKER, 0, spk_text);
  685. static const struct snd_kcontrol_new spkl_mux =
  686. SOC_DAPM_ENUM("SPKL", spkl_enum);
  687. static SOC_ENUM_SINGLE_DECL(spkr_enum,
  688. WM8996_RIGHT_PDM_SPEAKER, 0, spk_text);
  689. static const struct snd_kcontrol_new spkr_mux =
  690. SOC_DAPM_ENUM("SPKR", spkr_enum);
  691. static const char *dsp1rx_text[] = {
  692. "AIF1", "AIF2"
  693. };
  694. static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
  695. WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text);
  696. static const struct snd_kcontrol_new dsp1rx =
  697. SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
  698. static const char *dsp2rx_text[] = {
  699. "AIF2", "AIF1"
  700. };
  701. static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
  702. WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text);
  703. static const struct snd_kcontrol_new dsp2rx =
  704. SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
  705. static const char *aif2tx_text[] = {
  706. "DSP2", "DSP1", "AIF1"
  707. };
  708. static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
  709. WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text);
  710. static const struct snd_kcontrol_new aif2tx =
  711. SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
  712. static const char *inmux_text[] = {
  713. "ADC", "DMIC1", "DMIC2"
  714. };
  715. static SOC_ENUM_SINGLE_DECL(in1_enum,
  716. WM8996_POWER_MANAGEMENT_7, 0, inmux_text);
  717. static const struct snd_kcontrol_new in1_mux =
  718. SOC_DAPM_ENUM("IN1 Mux", in1_enum);
  719. static SOC_ENUM_SINGLE_DECL(in2_enum,
  720. WM8996_POWER_MANAGEMENT_7, 4, inmux_text);
  721. static const struct snd_kcontrol_new in2_mux =
  722. SOC_DAPM_ENUM("IN2 Mux", in2_enum);
  723. static const struct snd_kcontrol_new dac2r_mix[] = {
  724. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
  725. 5, 1, 0),
  726. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
  727. 4, 1, 0),
  728. SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
  729. SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
  730. };
  731. static const struct snd_kcontrol_new dac2l_mix[] = {
  732. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
  733. 5, 1, 0),
  734. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
  735. 4, 1, 0),
  736. SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
  737. SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
  738. };
  739. static const struct snd_kcontrol_new dac1r_mix[] = {
  740. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
  741. 5, 1, 0),
  742. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
  743. 4, 1, 0),
  744. SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
  745. SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
  746. };
  747. static const struct snd_kcontrol_new dac1l_mix[] = {
  748. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
  749. 5, 1, 0),
  750. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
  751. 4, 1, 0),
  752. SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
  753. SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
  754. };
  755. static const struct snd_kcontrol_new dsp1txl[] = {
  756. SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
  757. 1, 1, 0),
  758. SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
  759. 0, 1, 0),
  760. };
  761. static const struct snd_kcontrol_new dsp1txr[] = {
  762. SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
  763. 1, 1, 0),
  764. SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
  765. 0, 1, 0),
  766. };
  767. static const struct snd_kcontrol_new dsp2txl[] = {
  768. SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
  769. 1, 1, 0),
  770. SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
  771. 0, 1, 0),
  772. };
  773. static const struct snd_kcontrol_new dsp2txr[] = {
  774. SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
  775. 1, 1, 0),
  776. SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
  777. 0, 1, 0),
  778. };
  779. static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
  780. SND_SOC_DAPM_INPUT("IN1LN"),
  781. SND_SOC_DAPM_INPUT("IN1LP"),
  782. SND_SOC_DAPM_INPUT("IN1RN"),
  783. SND_SOC_DAPM_INPUT("IN1RP"),
  784. SND_SOC_DAPM_INPUT("IN2LN"),
  785. SND_SOC_DAPM_INPUT("IN2LP"),
  786. SND_SOC_DAPM_INPUT("IN2RN"),
  787. SND_SOC_DAPM_INPUT("IN2RP"),
  788. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  789. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  790. SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
  791. SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
  792. SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
  793. SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
  794. SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
  795. SND_SOC_DAPM_POST_PMU),
  796. SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
  797. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  798. SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
  799. SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
  800. SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
  801. SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
  802. SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
  803. SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
  804. SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
  805. SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
  806. SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
  807. SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
  808. SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
  809. SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
  810. SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
  811. SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
  812. SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
  813. SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
  814. SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
  815. SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
  816. SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
  817. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
  818. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
  819. SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
  820. SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
  821. SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
  822. SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
  823. SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
  824. dsp2txl, ARRAY_SIZE(dsp2txl)),
  825. SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
  826. dsp2txr, ARRAY_SIZE(dsp2txr)),
  827. SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
  828. dsp1txl, ARRAY_SIZE(dsp1txl)),
  829. SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
  830. dsp1txr, ARRAY_SIZE(dsp1txr)),
  831. SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
  832. dac2l_mix, ARRAY_SIZE(dac2l_mix)),
  833. SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
  834. dac2r_mix, ARRAY_SIZE(dac2r_mix)),
  835. SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
  836. dac1l_mix, ARRAY_SIZE(dac1l_mix)),
  837. SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
  838. dac1r_mix, ARRAY_SIZE(dac1r_mix)),
  839. SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
  840. SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
  841. SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
  842. SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
  843. SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
  844. SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
  845. SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
  846. SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
  847. SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
  848. SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
  849. SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
  850. SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
  851. SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
  852. SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
  853. SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
  854. SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
  855. SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
  856. SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
  857. SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
  858. SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
  859. /* We route as stereo pairs so define some dummy widgets to squash
  860. * things down for now. RXA = 0,1, RXB = 2,3 and so on */
  861. SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
  862. SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
  863. SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
  864. SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
  865. SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
  866. SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
  867. SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
  868. SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
  869. SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
  870. SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
  871. SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
  872. SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
  873. SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
  874. SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
  875. SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
  876. SND_SOC_DAPM_POST_PMU),
  877. SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
  878. rmv_short_event,
  879. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  880. SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
  881. SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
  882. SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
  883. SND_SOC_DAPM_POST_PMU),
  884. SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
  885. rmv_short_event,
  886. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  887. SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
  888. SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
  889. SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
  890. SND_SOC_DAPM_POST_PMU),
  891. SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
  892. rmv_short_event,
  893. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  894. SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
  895. SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
  896. SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
  897. SND_SOC_DAPM_POST_PMU),
  898. SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
  899. rmv_short_event,
  900. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
  901. SND_SOC_DAPM_OUTPUT("HPOUT1L"),
  902. SND_SOC_DAPM_OUTPUT("HPOUT1R"),
  903. SND_SOC_DAPM_OUTPUT("HPOUT2L"),
  904. SND_SOC_DAPM_OUTPUT("HPOUT2R"),
  905. SND_SOC_DAPM_OUTPUT("SPKDAT"),
  906. };
  907. static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
  908. { "AIFCLK", NULL, "SYSCLK" },
  909. { "SYSDSPCLK", NULL, "SYSCLK" },
  910. { "Charge Pump", NULL, "SYSCLK" },
  911. { "Charge Pump", NULL, "CPVDD" },
  912. { "MICB1", NULL, "LDO2" },
  913. { "MICB1", NULL, "MICB1 Audio" },
  914. { "MICB1", NULL, "Bandgap" },
  915. { "MICB2", NULL, "LDO2" },
  916. { "MICB2", NULL, "MICB2 Audio" },
  917. { "MICB2", NULL, "Bandgap" },
  918. { "AIF1RX0", NULL, "AIF1 Playback" },
  919. { "AIF1RX1", NULL, "AIF1 Playback" },
  920. { "AIF1RX2", NULL, "AIF1 Playback" },
  921. { "AIF1RX3", NULL, "AIF1 Playback" },
  922. { "AIF1RX4", NULL, "AIF1 Playback" },
  923. { "AIF1RX5", NULL, "AIF1 Playback" },
  924. { "AIF2RX0", NULL, "AIF2 Playback" },
  925. { "AIF2RX1", NULL, "AIF2 Playback" },
  926. { "AIF1 Capture", NULL, "AIF1TX0" },
  927. { "AIF1 Capture", NULL, "AIF1TX1" },
  928. { "AIF1 Capture", NULL, "AIF1TX2" },
  929. { "AIF1 Capture", NULL, "AIF1TX3" },
  930. { "AIF1 Capture", NULL, "AIF1TX4" },
  931. { "AIF1 Capture", NULL, "AIF1TX5" },
  932. { "AIF2 Capture", NULL, "AIF2TX0" },
  933. { "AIF2 Capture", NULL, "AIF2TX1" },
  934. { "IN1L PGA", NULL, "IN2LN" },
  935. { "IN1L PGA", NULL, "IN2LP" },
  936. { "IN1L PGA", NULL, "IN1LN" },
  937. { "IN1L PGA", NULL, "IN1LP" },
  938. { "IN1L PGA", NULL, "Bandgap" },
  939. { "IN1R PGA", NULL, "IN2RN" },
  940. { "IN1R PGA", NULL, "IN2RP" },
  941. { "IN1R PGA", NULL, "IN1RN" },
  942. { "IN1R PGA", NULL, "IN1RP" },
  943. { "IN1R PGA", NULL, "Bandgap" },
  944. { "ADCL", NULL, "IN1L PGA" },
  945. { "ADCR", NULL, "IN1R PGA" },
  946. { "DMIC1L", NULL, "DMIC1DAT" },
  947. { "DMIC1R", NULL, "DMIC1DAT" },
  948. { "DMIC2L", NULL, "DMIC2DAT" },
  949. { "DMIC2R", NULL, "DMIC2DAT" },
  950. { "DMIC2L", NULL, "DMIC2" },
  951. { "DMIC2R", NULL, "DMIC2" },
  952. { "DMIC1L", NULL, "DMIC1" },
  953. { "DMIC1R", NULL, "DMIC1" },
  954. { "IN1L Mux", "ADC", "ADCL" },
  955. { "IN1L Mux", "DMIC1", "DMIC1L" },
  956. { "IN1L Mux", "DMIC2", "DMIC2L" },
  957. { "IN1R Mux", "ADC", "ADCR" },
  958. { "IN1R Mux", "DMIC1", "DMIC1R" },
  959. { "IN1R Mux", "DMIC2", "DMIC2R" },
  960. { "IN2L Mux", "ADC", "ADCL" },
  961. { "IN2L Mux", "DMIC1", "DMIC1L" },
  962. { "IN2L Mux", "DMIC2", "DMIC2L" },
  963. { "IN2R Mux", "ADC", "ADCR" },
  964. { "IN2R Mux", "DMIC1", "DMIC1R" },
  965. { "IN2R Mux", "DMIC2", "DMIC2R" },
  966. { "Left Sidetone", "IN1", "IN1L Mux" },
  967. { "Left Sidetone", "IN2", "IN2L Mux" },
  968. { "Right Sidetone", "IN1", "IN1R Mux" },
  969. { "Right Sidetone", "IN2", "IN2R Mux" },
  970. { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
  971. { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
  972. { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
  973. { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
  974. { "AIF1TX0", NULL, "DSP1TXL" },
  975. { "AIF1TX1", NULL, "DSP1TXR" },
  976. { "AIF1TX2", NULL, "DSP2TXL" },
  977. { "AIF1TX3", NULL, "DSP2TXR" },
  978. { "AIF1TX4", NULL, "AIF2RX0" },
  979. { "AIF1TX5", NULL, "AIF2RX1" },
  980. { "AIF1RX0", NULL, "AIFCLK" },
  981. { "AIF1RX1", NULL, "AIFCLK" },
  982. { "AIF1RX2", NULL, "AIFCLK" },
  983. { "AIF1RX3", NULL, "AIFCLK" },
  984. { "AIF1RX4", NULL, "AIFCLK" },
  985. { "AIF1RX5", NULL, "AIFCLK" },
  986. { "AIF2RX0", NULL, "AIFCLK" },
  987. { "AIF2RX1", NULL, "AIFCLK" },
  988. { "AIF1TX0", NULL, "AIFCLK" },
  989. { "AIF1TX1", NULL, "AIFCLK" },
  990. { "AIF1TX2", NULL, "AIFCLK" },
  991. { "AIF1TX3", NULL, "AIFCLK" },
  992. { "AIF1TX4", NULL, "AIFCLK" },
  993. { "AIF1TX5", NULL, "AIFCLK" },
  994. { "AIF2TX0", NULL, "AIFCLK" },
  995. { "AIF2TX1", NULL, "AIFCLK" },
  996. { "DSP1RXL", NULL, "SYSDSPCLK" },
  997. { "DSP1RXR", NULL, "SYSDSPCLK" },
  998. { "DSP2RXL", NULL, "SYSDSPCLK" },
  999. { "DSP2RXR", NULL, "SYSDSPCLK" },
  1000. { "DSP1TXL", NULL, "SYSDSPCLK" },
  1001. { "DSP1TXR", NULL, "SYSDSPCLK" },
  1002. { "DSP2TXL", NULL, "SYSDSPCLK" },
  1003. { "DSP2TXR", NULL, "SYSDSPCLK" },
  1004. { "AIF1RXA", NULL, "AIF1RX0" },
  1005. { "AIF1RXA", NULL, "AIF1RX1" },
  1006. { "AIF1RXB", NULL, "AIF1RX2" },
  1007. { "AIF1RXB", NULL, "AIF1RX3" },
  1008. { "AIF1RXC", NULL, "AIF1RX4" },
  1009. { "AIF1RXC", NULL, "AIF1RX5" },
  1010. { "AIF2RX", NULL, "AIF2RX0" },
  1011. { "AIF2RX", NULL, "AIF2RX1" },
  1012. { "AIF2TX", "DSP2", "DSP2TX" },
  1013. { "AIF2TX", "DSP1", "DSP1RX" },
  1014. { "AIF2TX", "AIF1", "AIF1RXC" },
  1015. { "DSP1RXL", NULL, "DSP1RX" },
  1016. { "DSP1RXR", NULL, "DSP1RX" },
  1017. { "DSP2RXL", NULL, "DSP2RX" },
  1018. { "DSP2RXR", NULL, "DSP2RX" },
  1019. { "DSP2TX", NULL, "DSP2TXL" },
  1020. { "DSP2TX", NULL, "DSP2TXR" },
  1021. { "DSP1RX", "AIF1", "AIF1RXA" },
  1022. { "DSP1RX", "AIF2", "AIF2RX" },
  1023. { "DSP2RX", "AIF1", "AIF1RXB" },
  1024. { "DSP2RX", "AIF2", "AIF2RX" },
  1025. { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
  1026. { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
  1027. { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1028. { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1029. { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
  1030. { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
  1031. { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1032. { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1033. { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
  1034. { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
  1035. { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1036. { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1037. { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
  1038. { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
  1039. { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1040. { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1041. { "DAC1L", NULL, "DAC1L Mixer" },
  1042. { "DAC1R", NULL, "DAC1R Mixer" },
  1043. { "DAC2L", NULL, "DAC2L Mixer" },
  1044. { "DAC2R", NULL, "DAC2R Mixer" },
  1045. { "HPOUT2L PGA", NULL, "Charge Pump" },
  1046. { "HPOUT2L PGA", NULL, "Bandgap" },
  1047. { "HPOUT2L PGA", NULL, "DAC2L" },
  1048. { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
  1049. { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
  1050. { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
  1051. { "HPOUT2R PGA", NULL, "Charge Pump" },
  1052. { "HPOUT2R PGA", NULL, "Bandgap" },
  1053. { "HPOUT2R PGA", NULL, "DAC2R" },
  1054. { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
  1055. { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
  1056. { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
  1057. { "HPOUT1L PGA", NULL, "Charge Pump" },
  1058. { "HPOUT1L PGA", NULL, "Bandgap" },
  1059. { "HPOUT1L PGA", NULL, "DAC1L" },
  1060. { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
  1061. { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
  1062. { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
  1063. { "HPOUT1R PGA", NULL, "Charge Pump" },
  1064. { "HPOUT1R PGA", NULL, "Bandgap" },
  1065. { "HPOUT1R PGA", NULL, "DAC1R" },
  1066. { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
  1067. { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
  1068. { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
  1069. { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
  1070. { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
  1071. { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
  1072. { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
  1073. { "SPKL", "DAC1L", "DAC1L" },
  1074. { "SPKL", "DAC1R", "DAC1R" },
  1075. { "SPKL", "DAC2L", "DAC2L" },
  1076. { "SPKL", "DAC2R", "DAC2R" },
  1077. { "SPKR", "DAC1L", "DAC1L" },
  1078. { "SPKR", "DAC1R", "DAC1R" },
  1079. { "SPKR", "DAC2L", "DAC2L" },
  1080. { "SPKR", "DAC2R", "DAC2R" },
  1081. { "SPKL PGA", NULL, "SPKL" },
  1082. { "SPKR PGA", NULL, "SPKR" },
  1083. { "SPKDAT", NULL, "SPKL PGA" },
  1084. { "SPKDAT", NULL, "SPKR PGA" },
  1085. };
  1086. static bool wm8996_readable_register(struct device *dev, unsigned int reg)
  1087. {
  1088. /* Due to the sparseness of the register map the compiler
  1089. * output from an explicit switch statement ends up being much
  1090. * more efficient than a table.
  1091. */
  1092. switch (reg) {
  1093. case WM8996_SOFTWARE_RESET:
  1094. case WM8996_POWER_MANAGEMENT_1:
  1095. case WM8996_POWER_MANAGEMENT_2:
  1096. case WM8996_POWER_MANAGEMENT_3:
  1097. case WM8996_POWER_MANAGEMENT_4:
  1098. case WM8996_POWER_MANAGEMENT_5:
  1099. case WM8996_POWER_MANAGEMENT_6:
  1100. case WM8996_POWER_MANAGEMENT_7:
  1101. case WM8996_POWER_MANAGEMENT_8:
  1102. case WM8996_LEFT_LINE_INPUT_VOLUME:
  1103. case WM8996_RIGHT_LINE_INPUT_VOLUME:
  1104. case WM8996_LINE_INPUT_CONTROL:
  1105. case WM8996_DAC1_HPOUT1_VOLUME:
  1106. case WM8996_DAC2_HPOUT2_VOLUME:
  1107. case WM8996_DAC1_LEFT_VOLUME:
  1108. case WM8996_DAC1_RIGHT_VOLUME:
  1109. case WM8996_DAC2_LEFT_VOLUME:
  1110. case WM8996_DAC2_RIGHT_VOLUME:
  1111. case WM8996_OUTPUT1_LEFT_VOLUME:
  1112. case WM8996_OUTPUT1_RIGHT_VOLUME:
  1113. case WM8996_OUTPUT2_LEFT_VOLUME:
  1114. case WM8996_OUTPUT2_RIGHT_VOLUME:
  1115. case WM8996_MICBIAS_1:
  1116. case WM8996_MICBIAS_2:
  1117. case WM8996_LDO_1:
  1118. case WM8996_LDO_2:
  1119. case WM8996_ACCESSORY_DETECT_MODE_1:
  1120. case WM8996_ACCESSORY_DETECT_MODE_2:
  1121. case WM8996_HEADPHONE_DETECT_1:
  1122. case WM8996_HEADPHONE_DETECT_2:
  1123. case WM8996_MIC_DETECT_1:
  1124. case WM8996_MIC_DETECT_2:
  1125. case WM8996_MIC_DETECT_3:
  1126. case WM8996_CHARGE_PUMP_1:
  1127. case WM8996_CHARGE_PUMP_2:
  1128. case WM8996_DC_SERVO_1:
  1129. case WM8996_DC_SERVO_2:
  1130. case WM8996_DC_SERVO_3:
  1131. case WM8996_DC_SERVO_5:
  1132. case WM8996_DC_SERVO_6:
  1133. case WM8996_DC_SERVO_7:
  1134. case WM8996_DC_SERVO_READBACK_0:
  1135. case WM8996_ANALOGUE_HP_1:
  1136. case WM8996_ANALOGUE_HP_2:
  1137. case WM8996_CHIP_REVISION:
  1138. case WM8996_CONTROL_INTERFACE_1:
  1139. case WM8996_WRITE_SEQUENCER_CTRL_1:
  1140. case WM8996_WRITE_SEQUENCER_CTRL_2:
  1141. case WM8996_AIF_CLOCKING_1:
  1142. case WM8996_AIF_CLOCKING_2:
  1143. case WM8996_CLOCKING_1:
  1144. case WM8996_CLOCKING_2:
  1145. case WM8996_AIF_RATE:
  1146. case WM8996_FLL_CONTROL_1:
  1147. case WM8996_FLL_CONTROL_2:
  1148. case WM8996_FLL_CONTROL_3:
  1149. case WM8996_FLL_CONTROL_4:
  1150. case WM8996_FLL_CONTROL_5:
  1151. case WM8996_FLL_CONTROL_6:
  1152. case WM8996_FLL_EFS_1:
  1153. case WM8996_FLL_EFS_2:
  1154. case WM8996_AIF1_CONTROL:
  1155. case WM8996_AIF1_BCLK:
  1156. case WM8996_AIF1_TX_LRCLK_1:
  1157. case WM8996_AIF1_TX_LRCLK_2:
  1158. case WM8996_AIF1_RX_LRCLK_1:
  1159. case WM8996_AIF1_RX_LRCLK_2:
  1160. case WM8996_AIF1TX_DATA_CONFIGURATION_1:
  1161. case WM8996_AIF1TX_DATA_CONFIGURATION_2:
  1162. case WM8996_AIF1RX_DATA_CONFIGURATION:
  1163. case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
  1164. case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
  1165. case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
  1166. case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
  1167. case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
  1168. case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
  1169. case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
  1170. case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
  1171. case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
  1172. case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
  1173. case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
  1174. case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
  1175. case WM8996_AIF1RX_MONO_CONFIGURATION:
  1176. case WM8996_AIF1TX_TEST:
  1177. case WM8996_AIF2_CONTROL:
  1178. case WM8996_AIF2_BCLK:
  1179. case WM8996_AIF2_TX_LRCLK_1:
  1180. case WM8996_AIF2_TX_LRCLK_2:
  1181. case WM8996_AIF2_RX_LRCLK_1:
  1182. case WM8996_AIF2_RX_LRCLK_2:
  1183. case WM8996_AIF2TX_DATA_CONFIGURATION_1:
  1184. case WM8996_AIF2TX_DATA_CONFIGURATION_2:
  1185. case WM8996_AIF2RX_DATA_CONFIGURATION:
  1186. case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
  1187. case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
  1188. case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
  1189. case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
  1190. case WM8996_AIF2RX_MONO_CONFIGURATION:
  1191. case WM8996_AIF2TX_TEST:
  1192. case WM8996_DSP1_TX_LEFT_VOLUME:
  1193. case WM8996_DSP1_TX_RIGHT_VOLUME:
  1194. case WM8996_DSP1_RX_LEFT_VOLUME:
  1195. case WM8996_DSP1_RX_RIGHT_VOLUME:
  1196. case WM8996_DSP1_TX_FILTERS:
  1197. case WM8996_DSP1_RX_FILTERS_1:
  1198. case WM8996_DSP1_RX_FILTERS_2:
  1199. case WM8996_DSP1_DRC_1:
  1200. case WM8996_DSP1_DRC_2:
  1201. case WM8996_DSP1_DRC_3:
  1202. case WM8996_DSP1_DRC_4:
  1203. case WM8996_DSP1_DRC_5:
  1204. case WM8996_DSP1_RX_EQ_GAINS_1:
  1205. case WM8996_DSP1_RX_EQ_GAINS_2:
  1206. case WM8996_DSP1_RX_EQ_BAND_1_A:
  1207. case WM8996_DSP1_RX_EQ_BAND_1_B:
  1208. case WM8996_DSP1_RX_EQ_BAND_1_PG:
  1209. case WM8996_DSP1_RX_EQ_BAND_2_A:
  1210. case WM8996_DSP1_RX_EQ_BAND_2_B:
  1211. case WM8996_DSP1_RX_EQ_BAND_2_C:
  1212. case WM8996_DSP1_RX_EQ_BAND_2_PG:
  1213. case WM8996_DSP1_RX_EQ_BAND_3_A:
  1214. case WM8996_DSP1_RX_EQ_BAND_3_B:
  1215. case WM8996_DSP1_RX_EQ_BAND_3_C:
  1216. case WM8996_DSP1_RX_EQ_BAND_3_PG:
  1217. case WM8996_DSP1_RX_EQ_BAND_4_A:
  1218. case WM8996_DSP1_RX_EQ_BAND_4_B:
  1219. case WM8996_DSP1_RX_EQ_BAND_4_C:
  1220. case WM8996_DSP1_RX_EQ_BAND_4_PG:
  1221. case WM8996_DSP1_RX_EQ_BAND_5_A:
  1222. case WM8996_DSP1_RX_EQ_BAND_5_B:
  1223. case WM8996_DSP1_RX_EQ_BAND_5_PG:
  1224. case WM8996_DSP2_TX_LEFT_VOLUME:
  1225. case WM8996_DSP2_TX_RIGHT_VOLUME:
  1226. case WM8996_DSP2_RX_LEFT_VOLUME:
  1227. case WM8996_DSP2_RX_RIGHT_VOLUME:
  1228. case WM8996_DSP2_TX_FILTERS:
  1229. case WM8996_DSP2_RX_FILTERS_1:
  1230. case WM8996_DSP2_RX_FILTERS_2:
  1231. case WM8996_DSP2_DRC_1:
  1232. case WM8996_DSP2_DRC_2:
  1233. case WM8996_DSP2_DRC_3:
  1234. case WM8996_DSP2_DRC_4:
  1235. case WM8996_DSP2_DRC_5:
  1236. case WM8996_DSP2_RX_EQ_GAINS_1:
  1237. case WM8996_DSP2_RX_EQ_GAINS_2:
  1238. case WM8996_DSP2_RX_EQ_BAND_1_A:
  1239. case WM8996_DSP2_RX_EQ_BAND_1_B:
  1240. case WM8996_DSP2_RX_EQ_BAND_1_PG:
  1241. case WM8996_DSP2_RX_EQ_BAND_2_A:
  1242. case WM8996_DSP2_RX_EQ_BAND_2_B:
  1243. case WM8996_DSP2_RX_EQ_BAND_2_C:
  1244. case WM8996_DSP2_RX_EQ_BAND_2_PG:
  1245. case WM8996_DSP2_RX_EQ_BAND_3_A:
  1246. case WM8996_DSP2_RX_EQ_BAND_3_B:
  1247. case WM8996_DSP2_RX_EQ_BAND_3_C:
  1248. case WM8996_DSP2_RX_EQ_BAND_3_PG:
  1249. case WM8996_DSP2_RX_EQ_BAND_4_A:
  1250. case WM8996_DSP2_RX_EQ_BAND_4_B:
  1251. case WM8996_DSP2_RX_EQ_BAND_4_C:
  1252. case WM8996_DSP2_RX_EQ_BAND_4_PG:
  1253. case WM8996_DSP2_RX_EQ_BAND_5_A:
  1254. case WM8996_DSP2_RX_EQ_BAND_5_B:
  1255. case WM8996_DSP2_RX_EQ_BAND_5_PG:
  1256. case WM8996_DAC1_MIXER_VOLUMES:
  1257. case WM8996_DAC1_LEFT_MIXER_ROUTING:
  1258. case WM8996_DAC1_RIGHT_MIXER_ROUTING:
  1259. case WM8996_DAC2_MIXER_VOLUMES:
  1260. case WM8996_DAC2_LEFT_MIXER_ROUTING:
  1261. case WM8996_DAC2_RIGHT_MIXER_ROUTING:
  1262. case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
  1263. case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
  1264. case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
  1265. case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
  1266. case WM8996_DSP_TX_MIXER_SELECT:
  1267. case WM8996_DAC_SOFTMUTE:
  1268. case WM8996_OVERSAMPLING:
  1269. case WM8996_SIDETONE:
  1270. case WM8996_GPIO_1:
  1271. case WM8996_GPIO_2:
  1272. case WM8996_GPIO_3:
  1273. case WM8996_GPIO_4:
  1274. case WM8996_GPIO_5:
  1275. case WM8996_PULL_CONTROL_1:
  1276. case WM8996_PULL_CONTROL_2:
  1277. case WM8996_INTERRUPT_STATUS_1:
  1278. case WM8996_INTERRUPT_STATUS_2:
  1279. case WM8996_INTERRUPT_RAW_STATUS_2:
  1280. case WM8996_INTERRUPT_STATUS_1_MASK:
  1281. case WM8996_INTERRUPT_STATUS_2_MASK:
  1282. case WM8996_INTERRUPT_CONTROL:
  1283. case WM8996_LEFT_PDM_SPEAKER:
  1284. case WM8996_RIGHT_PDM_SPEAKER:
  1285. case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
  1286. case WM8996_PDM_SPEAKER_VOLUME:
  1287. return true;
  1288. default:
  1289. return false;
  1290. }
  1291. }
  1292. static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
  1293. {
  1294. switch (reg) {
  1295. case WM8996_SOFTWARE_RESET:
  1296. case WM8996_CHIP_REVISION:
  1297. case WM8996_LDO_1:
  1298. case WM8996_LDO_2:
  1299. case WM8996_INTERRUPT_STATUS_1:
  1300. case WM8996_INTERRUPT_STATUS_2:
  1301. case WM8996_INTERRUPT_RAW_STATUS_2:
  1302. case WM8996_DC_SERVO_READBACK_0:
  1303. case WM8996_DC_SERVO_2:
  1304. case WM8996_DC_SERVO_6:
  1305. case WM8996_DC_SERVO_7:
  1306. case WM8996_FLL_CONTROL_6:
  1307. case WM8996_MIC_DETECT_3:
  1308. case WM8996_HEADPHONE_DETECT_1:
  1309. case WM8996_HEADPHONE_DETECT_2:
  1310. return true;
  1311. default:
  1312. return false;
  1313. }
  1314. }
  1315. static const int bclk_divs[] = {
  1316. 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
  1317. };
  1318. static void wm8996_update_bclk(struct snd_soc_component *component)
  1319. {
  1320. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1321. int aif, best, cur_val, bclk_rate, bclk_reg, i;
  1322. /* Don't bother if we're in a low frequency idle mode that
  1323. * can't support audio.
  1324. */
  1325. if (wm8996->sysclk < 64000)
  1326. return;
  1327. for (aif = 0; aif < WM8996_AIFS; aif++) {
  1328. switch (aif) {
  1329. case 0:
  1330. bclk_reg = WM8996_AIF1_BCLK;
  1331. break;
  1332. case 1:
  1333. bclk_reg = WM8996_AIF2_BCLK;
  1334. break;
  1335. }
  1336. bclk_rate = wm8996->bclk_rate[aif];
  1337. /* Pick a divisor for BCLK as close as we can get to ideal */
  1338. best = 0;
  1339. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1340. cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
  1341. if (cur_val < 0) /* BCLK table is sorted */
  1342. break;
  1343. best = i;
  1344. }
  1345. bclk_rate = wm8996->sysclk / bclk_divs[best];
  1346. dev_dbg(component->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
  1347. bclk_divs[best], bclk_rate);
  1348. snd_soc_component_update_bits(component, bclk_reg,
  1349. WM8996_AIF1_BCLK_DIV_MASK, best);
  1350. }
  1351. }
  1352. static int wm8996_set_bias_level(struct snd_soc_component *component,
  1353. enum snd_soc_bias_level level)
  1354. {
  1355. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1356. int ret;
  1357. switch (level) {
  1358. case SND_SOC_BIAS_ON:
  1359. break;
  1360. case SND_SOC_BIAS_PREPARE:
  1361. /* Put the MICBIASes into regulating mode */
  1362. snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
  1363. WM8996_MICB1_MODE, 0);
  1364. snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
  1365. WM8996_MICB2_MODE, 0);
  1366. break;
  1367. case SND_SOC_BIAS_STANDBY:
  1368. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  1369. ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
  1370. wm8996->supplies);
  1371. if (ret != 0) {
  1372. dev_err(component->dev,
  1373. "Failed to enable supplies: %d\n",
  1374. ret);
  1375. return ret;
  1376. }
  1377. if (wm8996->pdata.ldo_ena >= 0) {
  1378. gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
  1379. 1);
  1380. msleep(5);
  1381. }
  1382. regcache_cache_only(wm8996->regmap, false);
  1383. regcache_sync(wm8996->regmap);
  1384. }
  1385. /* Bypass the MICBIASes for lowest power */
  1386. snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
  1387. WM8996_MICB1_MODE, WM8996_MICB1_MODE);
  1388. snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
  1389. WM8996_MICB2_MODE, WM8996_MICB2_MODE);
  1390. break;
  1391. case SND_SOC_BIAS_OFF:
  1392. regcache_cache_only(wm8996->regmap, true);
  1393. if (wm8996->pdata.ldo_ena >= 0) {
  1394. gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
  1395. regcache_cache_only(wm8996->regmap, true);
  1396. }
  1397. regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
  1398. wm8996->supplies);
  1399. break;
  1400. }
  1401. return 0;
  1402. }
  1403. static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1404. {
  1405. struct snd_soc_component *component = dai->component;
  1406. int aifctrl = 0;
  1407. int bclk = 0;
  1408. int lrclk_tx = 0;
  1409. int lrclk_rx = 0;
  1410. int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
  1411. switch (dai->id) {
  1412. case 0:
  1413. aifctrl_reg = WM8996_AIF1_CONTROL;
  1414. bclk_reg = WM8996_AIF1_BCLK;
  1415. lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
  1416. lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
  1417. break;
  1418. case 1:
  1419. aifctrl_reg = WM8996_AIF2_CONTROL;
  1420. bclk_reg = WM8996_AIF2_BCLK;
  1421. lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
  1422. lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
  1423. break;
  1424. default:
  1425. WARN(1, "Invalid dai id %d\n", dai->id);
  1426. return -EINVAL;
  1427. }
  1428. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1429. case SND_SOC_DAIFMT_NB_NF:
  1430. break;
  1431. case SND_SOC_DAIFMT_IB_NF:
  1432. bclk |= WM8996_AIF1_BCLK_INV;
  1433. break;
  1434. case SND_SOC_DAIFMT_NB_IF:
  1435. lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
  1436. lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
  1437. break;
  1438. case SND_SOC_DAIFMT_IB_IF:
  1439. bclk |= WM8996_AIF1_BCLK_INV;
  1440. lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
  1441. lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
  1442. break;
  1443. }
  1444. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1445. case SND_SOC_DAIFMT_CBS_CFS:
  1446. break;
  1447. case SND_SOC_DAIFMT_CBS_CFM:
  1448. lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
  1449. lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
  1450. break;
  1451. case SND_SOC_DAIFMT_CBM_CFS:
  1452. bclk |= WM8996_AIF1_BCLK_MSTR;
  1453. break;
  1454. case SND_SOC_DAIFMT_CBM_CFM:
  1455. bclk |= WM8996_AIF1_BCLK_MSTR;
  1456. lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
  1457. lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
  1458. break;
  1459. default:
  1460. return -EINVAL;
  1461. }
  1462. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1463. case SND_SOC_DAIFMT_DSP_A:
  1464. break;
  1465. case SND_SOC_DAIFMT_DSP_B:
  1466. aifctrl |= 1;
  1467. break;
  1468. case SND_SOC_DAIFMT_I2S:
  1469. aifctrl |= 2;
  1470. break;
  1471. case SND_SOC_DAIFMT_LEFT_J:
  1472. aifctrl |= 3;
  1473. break;
  1474. default:
  1475. return -EINVAL;
  1476. }
  1477. snd_soc_component_update_bits(component, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
  1478. snd_soc_component_update_bits(component, bclk_reg,
  1479. WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
  1480. bclk);
  1481. snd_soc_component_update_bits(component, lrclk_tx_reg,
  1482. WM8996_AIF1TX_LRCLK_INV |
  1483. WM8996_AIF1TX_LRCLK_MSTR,
  1484. lrclk_tx);
  1485. snd_soc_component_update_bits(component, lrclk_rx_reg,
  1486. WM8996_AIF1RX_LRCLK_INV |
  1487. WM8996_AIF1RX_LRCLK_MSTR,
  1488. lrclk_rx);
  1489. return 0;
  1490. }
  1491. static const int dsp_divs[] = {
  1492. 48000, 32000, 16000, 8000
  1493. };
  1494. static int wm8996_hw_params(struct snd_pcm_substream *substream,
  1495. struct snd_pcm_hw_params *params,
  1496. struct snd_soc_dai *dai)
  1497. {
  1498. struct snd_soc_component *component = dai->component;
  1499. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1500. int bits, i, bclk_rate, best;
  1501. int aifdata = 0;
  1502. int lrclk = 0;
  1503. int dsp = 0;
  1504. int aifdata_reg, lrclk_reg, dsp_shift;
  1505. switch (dai->id) {
  1506. case 0:
  1507. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  1508. (snd_soc_component_read(component, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
  1509. aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
  1510. lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
  1511. } else {
  1512. aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
  1513. lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
  1514. }
  1515. dsp_shift = 0;
  1516. break;
  1517. case 1:
  1518. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  1519. (snd_soc_component_read(component, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
  1520. aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
  1521. lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
  1522. } else {
  1523. aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
  1524. lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
  1525. }
  1526. dsp_shift = WM8996_DSP2_DIV_SHIFT;
  1527. break;
  1528. default:
  1529. WARN(1, "Invalid dai id %d\n", dai->id);
  1530. return -EINVAL;
  1531. }
  1532. bclk_rate = snd_soc_params_to_bclk(params);
  1533. if (bclk_rate < 0) {
  1534. dev_err(component->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
  1535. return bclk_rate;
  1536. }
  1537. wm8996->bclk_rate[dai->id] = bclk_rate;
  1538. wm8996->rx_rate[dai->id] = params_rate(params);
  1539. /* Needs looking at for TDM */
  1540. bits = params_width(params);
  1541. if (bits < 0)
  1542. return bits;
  1543. aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
  1544. best = 0;
  1545. for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
  1546. if (abs(dsp_divs[i] - params_rate(params)) <
  1547. abs(dsp_divs[best] - params_rate(params)))
  1548. best = i;
  1549. }
  1550. dsp |= i << dsp_shift;
  1551. wm8996_update_bclk(component);
  1552. lrclk = bclk_rate / params_rate(params);
  1553. dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
  1554. lrclk, bclk_rate / lrclk);
  1555. snd_soc_component_update_bits(component, aifdata_reg,
  1556. WM8996_AIF1TX_WL_MASK |
  1557. WM8996_AIF1TX_SLOT_LEN_MASK,
  1558. aifdata);
  1559. snd_soc_component_update_bits(component, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
  1560. lrclk);
  1561. snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_2,
  1562. WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
  1563. return 0;
  1564. }
  1565. static int wm8996_set_sysclk(struct snd_soc_dai *dai,
  1566. int clk_id, unsigned int freq, int dir)
  1567. {
  1568. struct snd_soc_component *component = dai->component;
  1569. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1570. int lfclk = 0;
  1571. int ratediv = 0;
  1572. int sync = WM8996_REG_SYNC;
  1573. int src;
  1574. int old;
  1575. if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
  1576. return 0;
  1577. /* Disable SYSCLK while we reconfigure */
  1578. old = snd_soc_component_read(component, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
  1579. snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
  1580. WM8996_SYSCLK_ENA, 0);
  1581. switch (clk_id) {
  1582. case WM8996_SYSCLK_MCLK1:
  1583. wm8996->sysclk = freq;
  1584. src = 0;
  1585. break;
  1586. case WM8996_SYSCLK_MCLK2:
  1587. wm8996->sysclk = freq;
  1588. src = 1;
  1589. break;
  1590. case WM8996_SYSCLK_FLL:
  1591. wm8996->sysclk = freq;
  1592. src = 2;
  1593. break;
  1594. default:
  1595. dev_err(component->dev, "Unsupported clock source %d\n", clk_id);
  1596. return -EINVAL;
  1597. }
  1598. switch (wm8996->sysclk) {
  1599. case 5644800:
  1600. case 6144000:
  1601. snd_soc_component_update_bits(component, WM8996_AIF_RATE,
  1602. WM8996_SYSCLK_RATE, 0);
  1603. break;
  1604. case 22579200:
  1605. case 24576000:
  1606. ratediv = WM8996_SYSCLK_DIV;
  1607. wm8996->sysclk /= 2;
  1608. fallthrough;
  1609. case 11289600:
  1610. case 12288000:
  1611. snd_soc_component_update_bits(component, WM8996_AIF_RATE,
  1612. WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
  1613. break;
  1614. case 32000:
  1615. case 32768:
  1616. lfclk = WM8996_LFCLK_ENA;
  1617. sync = 0;
  1618. break;
  1619. default:
  1620. dev_warn(component->dev, "Unsupported clock rate %dHz\n",
  1621. wm8996->sysclk);
  1622. return -EINVAL;
  1623. }
  1624. wm8996_update_bclk(component);
  1625. snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
  1626. WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
  1627. src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
  1628. snd_soc_component_update_bits(component, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
  1629. snd_soc_component_update_bits(component, WM8996_CONTROL_INTERFACE_1,
  1630. WM8996_REG_SYNC, sync);
  1631. snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
  1632. WM8996_SYSCLK_ENA, old);
  1633. wm8996->sysclk_src = clk_id;
  1634. return 0;
  1635. }
  1636. struct _fll_div {
  1637. u16 fll_fratio;
  1638. u16 fll_outdiv;
  1639. u16 fll_refclk_div;
  1640. u16 fll_loop_gain;
  1641. u16 fll_ref_freq;
  1642. u16 n;
  1643. u16 theta;
  1644. u16 lambda;
  1645. };
  1646. static struct {
  1647. unsigned int min;
  1648. unsigned int max;
  1649. u16 fll_fratio;
  1650. int ratio;
  1651. } fll_fratios[] = {
  1652. { 0, 64000, 4, 16 },
  1653. { 64000, 128000, 3, 8 },
  1654. { 128000, 256000, 2, 4 },
  1655. { 256000, 1000000, 1, 2 },
  1656. { 1000000, 13500000, 0, 1 },
  1657. };
  1658. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1659. unsigned int Fout)
  1660. {
  1661. unsigned int target;
  1662. unsigned int div;
  1663. unsigned int fratio, gcd_fll;
  1664. int i;
  1665. /* Fref must be <=13.5MHz */
  1666. div = 1;
  1667. fll_div->fll_refclk_div = 0;
  1668. while ((Fref / div) > 13500000) {
  1669. div *= 2;
  1670. fll_div->fll_refclk_div++;
  1671. if (div > 8) {
  1672. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1673. Fref);
  1674. return -EINVAL;
  1675. }
  1676. }
  1677. pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
  1678. /* Apply the division for our remaining calculations */
  1679. Fref /= div;
  1680. if (Fref >= 3000000)
  1681. fll_div->fll_loop_gain = 5;
  1682. else
  1683. fll_div->fll_loop_gain = 0;
  1684. if (Fref >= 48000)
  1685. fll_div->fll_ref_freq = 0;
  1686. else
  1687. fll_div->fll_ref_freq = 1;
  1688. /* Fvco should be 90-100MHz; don't check the upper bound */
  1689. div = 2;
  1690. while (Fout * div < 90000000) {
  1691. div++;
  1692. if (div > 64) {
  1693. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1694. Fout);
  1695. return -EINVAL;
  1696. }
  1697. }
  1698. target = Fout * div;
  1699. fll_div->fll_outdiv = div - 1;
  1700. pr_debug("FLL Fvco=%dHz\n", target);
  1701. /* Find an appropraite FLL_FRATIO and factor it out of the target */
  1702. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1703. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1704. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1705. fratio = fll_fratios[i].ratio;
  1706. break;
  1707. }
  1708. }
  1709. if (i == ARRAY_SIZE(fll_fratios)) {
  1710. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1711. return -EINVAL;
  1712. }
  1713. fll_div->n = target / (fratio * Fref);
  1714. if (target % Fref == 0) {
  1715. fll_div->theta = 0;
  1716. fll_div->lambda = 0;
  1717. } else {
  1718. gcd_fll = gcd(target, fratio * Fref);
  1719. fll_div->theta = (target - (fll_div->n * fratio * Fref))
  1720. / gcd_fll;
  1721. fll_div->lambda = (fratio * Fref) / gcd_fll;
  1722. }
  1723. pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
  1724. fll_div->n, fll_div->theta, fll_div->lambda);
  1725. pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
  1726. fll_div->fll_fratio, fll_div->fll_outdiv,
  1727. fll_div->fll_refclk_div);
  1728. return 0;
  1729. }
  1730. static int wm8996_set_fll(struct snd_soc_component *component, int fll_id, int source,
  1731. unsigned int Fref, unsigned int Fout)
  1732. {
  1733. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1734. struct i2c_client *i2c = to_i2c_client(component->dev);
  1735. struct _fll_div fll_div;
  1736. unsigned long timeout, time_left;
  1737. int ret, reg, retry;
  1738. /* Any change? */
  1739. if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
  1740. Fout == wm8996->fll_fout)
  1741. return 0;
  1742. if (Fout == 0) {
  1743. dev_dbg(component->dev, "FLL disabled\n");
  1744. wm8996->fll_fref = 0;
  1745. wm8996->fll_fout = 0;
  1746. snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1,
  1747. WM8996_FLL_ENA, 0);
  1748. wm8996_bg_disable(component);
  1749. return 0;
  1750. }
  1751. ret = fll_factors(&fll_div, Fref, Fout);
  1752. if (ret != 0)
  1753. return ret;
  1754. switch (source) {
  1755. case WM8996_FLL_MCLK1:
  1756. reg = 0;
  1757. break;
  1758. case WM8996_FLL_MCLK2:
  1759. reg = 1;
  1760. break;
  1761. case WM8996_FLL_DACLRCLK1:
  1762. reg = 2;
  1763. break;
  1764. case WM8996_FLL_BCLK1:
  1765. reg = 3;
  1766. break;
  1767. default:
  1768. dev_err(component->dev, "Unknown FLL source %d\n", ret);
  1769. return -EINVAL;
  1770. }
  1771. reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
  1772. reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
  1773. snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_5,
  1774. WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
  1775. WM8996_FLL_REFCLK_SRC_MASK, reg);
  1776. reg = 0;
  1777. if (fll_div.theta || fll_div.lambda)
  1778. reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
  1779. else
  1780. reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
  1781. snd_soc_component_write(component, WM8996_FLL_EFS_2, reg);
  1782. snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_2,
  1783. WM8996_FLL_OUTDIV_MASK |
  1784. WM8996_FLL_FRATIO_MASK,
  1785. (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
  1786. (fll_div.fll_fratio));
  1787. snd_soc_component_write(component, WM8996_FLL_CONTROL_3, fll_div.theta);
  1788. snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_4,
  1789. WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
  1790. (fll_div.n << WM8996_FLL_N_SHIFT) |
  1791. fll_div.fll_loop_gain);
  1792. snd_soc_component_write(component, WM8996_FLL_EFS_1, fll_div.lambda);
  1793. /* Enable the bandgap if it's not already enabled */
  1794. ret = snd_soc_component_read(component, WM8996_FLL_CONTROL_1);
  1795. if (!(ret & WM8996_FLL_ENA))
  1796. wm8996_bg_enable(component);
  1797. /* Clear any pending completions (eg, from failed startups) */
  1798. try_wait_for_completion(&wm8996->fll_lock);
  1799. snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1,
  1800. WM8996_FLL_ENA, WM8996_FLL_ENA);
  1801. /* The FLL supports live reconfiguration - kick that in case we were
  1802. * already enabled.
  1803. */
  1804. snd_soc_component_write(component, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
  1805. /* Wait for the FLL to lock, using the interrupt if possible */
  1806. if (Fref > 1000000)
  1807. timeout = usecs_to_jiffies(300);
  1808. else
  1809. timeout = msecs_to_jiffies(2);
  1810. /* Allow substantially longer if we've actually got the IRQ, poll
  1811. * at a slightly higher rate if we don't.
  1812. */
  1813. if (i2c->irq)
  1814. timeout *= 10;
  1815. else
  1816. /* ensure timeout of atleast 1 jiffies */
  1817. timeout = timeout/2 ? : 1;
  1818. for (retry = 0; retry < 10; retry++) {
  1819. time_left = wait_for_completion_timeout(&wm8996->fll_lock,
  1820. timeout);
  1821. if (time_left != 0) {
  1822. WARN_ON(!i2c->irq);
  1823. ret = 1;
  1824. break;
  1825. }
  1826. ret = snd_soc_component_read(component, WM8996_INTERRUPT_RAW_STATUS_2);
  1827. if (ret & WM8996_FLL_LOCK_STS)
  1828. break;
  1829. }
  1830. if (retry == 10) {
  1831. dev_err(component->dev, "Timed out waiting for FLL\n");
  1832. ret = -ETIMEDOUT;
  1833. }
  1834. dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1835. wm8996->fll_fref = Fref;
  1836. wm8996->fll_fout = Fout;
  1837. wm8996->fll_src = source;
  1838. return ret;
  1839. }
  1840. #ifdef CONFIG_GPIOLIB
  1841. static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  1842. {
  1843. struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
  1844. regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
  1845. WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
  1846. }
  1847. static int wm8996_gpio_direction_out(struct gpio_chip *chip,
  1848. unsigned offset, int value)
  1849. {
  1850. struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
  1851. int val;
  1852. val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
  1853. return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
  1854. WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
  1855. WM8996_GP1_LVL, val);
  1856. }
  1857. static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
  1858. {
  1859. struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
  1860. unsigned int reg;
  1861. int ret;
  1862. ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
  1863. if (ret < 0)
  1864. return ret;
  1865. return (reg & WM8996_GP1_LVL) != 0;
  1866. }
  1867. static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
  1868. {
  1869. struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
  1870. return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
  1871. WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
  1872. (1 << WM8996_GP1_FN_SHIFT) |
  1873. (1 << WM8996_GP1_DIR_SHIFT));
  1874. }
  1875. static const struct gpio_chip wm8996_template_chip = {
  1876. .label = "wm8996",
  1877. .owner = THIS_MODULE,
  1878. .direction_output = wm8996_gpio_direction_out,
  1879. .set = wm8996_gpio_set,
  1880. .direction_input = wm8996_gpio_direction_in,
  1881. .get = wm8996_gpio_get,
  1882. .can_sleep = 1,
  1883. };
  1884. static void wm8996_init_gpio(struct wm8996_priv *wm8996)
  1885. {
  1886. int ret;
  1887. wm8996->gpio_chip = wm8996_template_chip;
  1888. wm8996->gpio_chip.ngpio = 5;
  1889. wm8996->gpio_chip.parent = wm8996->dev;
  1890. if (wm8996->pdata.gpio_base)
  1891. wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
  1892. else
  1893. wm8996->gpio_chip.base = -1;
  1894. ret = gpiochip_add_data(&wm8996->gpio_chip, wm8996);
  1895. if (ret != 0)
  1896. dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
  1897. }
  1898. static void wm8996_free_gpio(struct wm8996_priv *wm8996)
  1899. {
  1900. gpiochip_remove(&wm8996->gpio_chip);
  1901. }
  1902. #else
  1903. static void wm8996_init_gpio(struct wm8996_priv *wm8996)
  1904. {
  1905. }
  1906. static void wm8996_free_gpio(struct wm8996_priv *wm8996)
  1907. {
  1908. }
  1909. #endif
  1910. /**
  1911. * wm8996_detect - Enable default WM8996 jack detection
  1912. * @component: ASoC component
  1913. * @jack: jack pointer
  1914. * @polarity_cb: polarity callback
  1915. *
  1916. * The WM8996 has advanced accessory detection support for headsets.
  1917. * This function provides a default implementation which integrates
  1918. * the majority of this functionality with minimal user configuration.
  1919. *
  1920. * This will detect headset, headphone and short circuit button and
  1921. * will also detect inverted microphone ground connections and update
  1922. * the polarity of the connections.
  1923. */
  1924. int wm8996_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
  1925. wm8996_polarity_fn polarity_cb)
  1926. {
  1927. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1928. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1929. wm8996->jack = jack;
  1930. wm8996->detecting = true;
  1931. wm8996->polarity_cb = polarity_cb;
  1932. wm8996->jack_flips = 0;
  1933. if (wm8996->polarity_cb)
  1934. wm8996->polarity_cb(component, 0);
  1935. /* Clear discarge to avoid noise during detection */
  1936. snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
  1937. WM8996_MICB1_DISCH, 0);
  1938. snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
  1939. WM8996_MICB2_DISCH, 0);
  1940. /* LDO2 powers the microphones, SYSCLK clocks detection */
  1941. snd_soc_dapm_mutex_lock(dapm);
  1942. snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
  1943. snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
  1944. snd_soc_dapm_mutex_unlock(dapm);
  1945. /* We start off just enabling microphone detection - even a
  1946. * plain headphone will trigger detection.
  1947. */
  1948. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
  1949. WM8996_MICD_ENA, WM8996_MICD_ENA);
  1950. /* Slowest detection rate, gives debounce for initial detection */
  1951. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
  1952. WM8996_MICD_RATE_MASK,
  1953. WM8996_MICD_RATE_MASK);
  1954. /* Enable interrupts and we're off */
  1955. snd_soc_component_update_bits(component, WM8996_INTERRUPT_STATUS_2_MASK,
  1956. WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
  1957. return 0;
  1958. }
  1959. EXPORT_SYMBOL_GPL(wm8996_detect);
  1960. static void wm8996_hpdet_irq(struct snd_soc_component *component)
  1961. {
  1962. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1963. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  1964. int val, reg, report;
  1965. /* Assume headphone in error conditions; we need to report
  1966. * something or we stall our state machine.
  1967. */
  1968. report = SND_JACK_HEADPHONE;
  1969. reg = snd_soc_component_read(component, WM8996_HEADPHONE_DETECT_2);
  1970. if (reg < 0) {
  1971. dev_err(component->dev, "Failed to read HPDET status\n");
  1972. goto out;
  1973. }
  1974. if (!(reg & WM8996_HP_DONE)) {
  1975. dev_err(component->dev, "Got HPDET IRQ but HPDET is busy\n");
  1976. goto out;
  1977. }
  1978. val = reg & WM8996_HP_LVL_MASK;
  1979. dev_dbg(component->dev, "HPDET measured %d ohms\n", val);
  1980. /* If we've got high enough impedence then report as line,
  1981. * otherwise assume headphone.
  1982. */
  1983. if (val >= 126)
  1984. report = SND_JACK_LINEOUT;
  1985. else
  1986. report = SND_JACK_HEADPHONE;
  1987. out:
  1988. if (wm8996->jack_mic)
  1989. report |= SND_JACK_MICROPHONE;
  1990. snd_soc_jack_report(wm8996->jack, report,
  1991. SND_JACK_LINEOUT | SND_JACK_HEADSET);
  1992. wm8996->detecting = false;
  1993. /* If the output isn't running re-clamp it */
  1994. if (!(snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_1) &
  1995. (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
  1996. snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1,
  1997. WM8996_HPOUT1L_RMV_SHORT |
  1998. WM8996_HPOUT1R_RMV_SHORT, 0);
  1999. /* Go back to looking at the microphone */
  2000. snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1,
  2001. WM8996_JD_MODE_MASK, 0);
  2002. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
  2003. WM8996_MICD_ENA);
  2004. snd_soc_dapm_disable_pin(dapm, "Bandgap");
  2005. snd_soc_dapm_sync(dapm);
  2006. }
  2007. static void wm8996_hpdet_start(struct snd_soc_component *component)
  2008. {
  2009. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2010. /* Unclamp the output, we can't measure while we're shorting it */
  2011. snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1,
  2012. WM8996_HPOUT1L_RMV_SHORT |
  2013. WM8996_HPOUT1R_RMV_SHORT,
  2014. WM8996_HPOUT1L_RMV_SHORT |
  2015. WM8996_HPOUT1R_RMV_SHORT);
  2016. /* We need bandgap for HPDET */
  2017. snd_soc_dapm_force_enable_pin(dapm, "Bandgap");
  2018. snd_soc_dapm_sync(dapm);
  2019. /* Go into headphone detect left mode */
  2020. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
  2021. snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1,
  2022. WM8996_JD_MODE_MASK, 1);
  2023. /* Trigger a measurement */
  2024. snd_soc_component_update_bits(component, WM8996_HEADPHONE_DETECT_1,
  2025. WM8996_HP_POLL, WM8996_HP_POLL);
  2026. }
  2027. static void wm8996_report_headphone(struct snd_soc_component *component)
  2028. {
  2029. dev_dbg(component->dev, "Headphone detected\n");
  2030. wm8996_hpdet_start(component);
  2031. /* Increase the detection rate a bit for responsiveness. */
  2032. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
  2033. WM8996_MICD_RATE_MASK |
  2034. WM8996_MICD_BIAS_STARTTIME_MASK,
  2035. 7 << WM8996_MICD_RATE_SHIFT |
  2036. 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
  2037. }
  2038. static void wm8996_micd(struct snd_soc_component *component)
  2039. {
  2040. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  2041. int val, reg;
  2042. val = snd_soc_component_read(component, WM8996_MIC_DETECT_3);
  2043. dev_dbg(component->dev, "Microphone event: %x\n", val);
  2044. if (!(val & WM8996_MICD_VALID)) {
  2045. dev_warn(component->dev, "Microphone detection state invalid\n");
  2046. return;
  2047. }
  2048. /* No accessory, reset everything and report removal */
  2049. if (!(val & WM8996_MICD_STS)) {
  2050. dev_dbg(component->dev, "Jack removal detected\n");
  2051. wm8996->jack_mic = false;
  2052. wm8996->detecting = true;
  2053. wm8996->jack_flips = 0;
  2054. snd_soc_jack_report(wm8996->jack, 0,
  2055. SND_JACK_LINEOUT | SND_JACK_HEADSET |
  2056. SND_JACK_BTN_0);
  2057. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
  2058. WM8996_MICD_RATE_MASK |
  2059. WM8996_MICD_BIAS_STARTTIME_MASK,
  2060. WM8996_MICD_RATE_MASK |
  2061. 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
  2062. return;
  2063. }
  2064. /* If the measurement is very high we've got a microphone,
  2065. * either we just detected one or if we already reported then
  2066. * we've got a button release event.
  2067. */
  2068. if (val & 0x400) {
  2069. if (wm8996->detecting) {
  2070. dev_dbg(component->dev, "Microphone detected\n");
  2071. wm8996->jack_mic = true;
  2072. wm8996_hpdet_start(component);
  2073. /* Increase poll rate to give better responsiveness
  2074. * for buttons */
  2075. snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
  2076. WM8996_MICD_RATE_MASK |
  2077. WM8996_MICD_BIAS_STARTTIME_MASK,
  2078. 5 << WM8996_MICD_RATE_SHIFT |
  2079. 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
  2080. } else {
  2081. dev_dbg(component->dev, "Mic button up\n");
  2082. snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
  2083. }
  2084. return;
  2085. }
  2086. /* If we detected a lower impedence during initial startup
  2087. * then we probably have the wrong polarity, flip it. Don't
  2088. * do this for the lowest impedences to speed up detection of
  2089. * plain headphones. If both polarities report a low
  2090. * impedence then give up and report headphones.
  2091. */
  2092. if (wm8996->detecting && (val & 0x3f0)) {
  2093. wm8996->jack_flips++;
  2094. if (wm8996->jack_flips > 1) {
  2095. wm8996_report_headphone(component);
  2096. return;
  2097. }
  2098. reg = snd_soc_component_read(component, WM8996_ACCESSORY_DETECT_MODE_2);
  2099. reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
  2100. WM8996_MICD_BIAS_SRC;
  2101. snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_2,
  2102. WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
  2103. WM8996_MICD_BIAS_SRC, reg);
  2104. if (wm8996->polarity_cb)
  2105. wm8996->polarity_cb(component,
  2106. (reg & WM8996_MICD_SRC) != 0);
  2107. dev_dbg(component->dev, "Set microphone polarity to %d\n",
  2108. (reg & WM8996_MICD_SRC) != 0);
  2109. return;
  2110. }
  2111. /* Don't distinguish between buttons, just report any low
  2112. * impedence as BTN_0.
  2113. */
  2114. if (val & 0x3fc) {
  2115. if (wm8996->jack_mic) {
  2116. dev_dbg(component->dev, "Mic button detected\n");
  2117. snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
  2118. SND_JACK_BTN_0);
  2119. } else if (wm8996->detecting) {
  2120. wm8996_report_headphone(component);
  2121. }
  2122. }
  2123. }
  2124. static irqreturn_t wm8996_irq(int irq, void *data)
  2125. {
  2126. struct snd_soc_component *component = data;
  2127. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  2128. int irq_val;
  2129. irq_val = snd_soc_component_read(component, WM8996_INTERRUPT_STATUS_2);
  2130. if (irq_val < 0) {
  2131. dev_err(component->dev, "Failed to read IRQ status: %d\n",
  2132. irq_val);
  2133. return IRQ_NONE;
  2134. }
  2135. irq_val &= ~snd_soc_component_read(component, WM8996_INTERRUPT_STATUS_2_MASK);
  2136. if (!irq_val)
  2137. return IRQ_NONE;
  2138. snd_soc_component_write(component, WM8996_INTERRUPT_STATUS_2, irq_val);
  2139. if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
  2140. dev_dbg(component->dev, "DC servo IRQ\n");
  2141. complete(&wm8996->dcs_done);
  2142. }
  2143. if (irq_val & WM8996_FIFOS_ERR_EINT)
  2144. dev_err(component->dev, "Digital core FIFO error\n");
  2145. if (irq_val & WM8996_FLL_LOCK_EINT) {
  2146. dev_dbg(component->dev, "FLL locked\n");
  2147. complete(&wm8996->fll_lock);
  2148. }
  2149. if (irq_val & WM8996_MICD_EINT)
  2150. wm8996_micd(component);
  2151. if (irq_val & WM8996_HP_DONE_EINT)
  2152. wm8996_hpdet_irq(component);
  2153. return IRQ_HANDLED;
  2154. }
  2155. static irqreturn_t wm8996_edge_irq(int irq, void *data)
  2156. {
  2157. irqreturn_t ret = IRQ_NONE;
  2158. irqreturn_t val;
  2159. do {
  2160. val = wm8996_irq(irq, data);
  2161. if (val != IRQ_NONE)
  2162. ret = val;
  2163. } while (val != IRQ_NONE);
  2164. return ret;
  2165. }
  2166. static void wm8996_retune_mobile_pdata(struct snd_soc_component *component)
  2167. {
  2168. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  2169. struct wm8996_pdata *pdata = &wm8996->pdata;
  2170. struct snd_kcontrol_new controls[] = {
  2171. SOC_ENUM_EXT("DSP1 EQ Mode",
  2172. wm8996->retune_mobile_enum,
  2173. wm8996_get_retune_mobile_enum,
  2174. wm8996_put_retune_mobile_enum),
  2175. SOC_ENUM_EXT("DSP2 EQ Mode",
  2176. wm8996->retune_mobile_enum,
  2177. wm8996_get_retune_mobile_enum,
  2178. wm8996_put_retune_mobile_enum),
  2179. };
  2180. int ret, i, j;
  2181. const char **t;
  2182. /* We need an array of texts for the enum API but the number
  2183. * of texts is likely to be less than the number of
  2184. * configurations due to the sample rate dependency of the
  2185. * configurations. */
  2186. wm8996->num_retune_mobile_texts = 0;
  2187. wm8996->retune_mobile_texts = NULL;
  2188. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  2189. for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
  2190. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  2191. wm8996->retune_mobile_texts[j]) == 0)
  2192. break;
  2193. }
  2194. if (j != wm8996->num_retune_mobile_texts)
  2195. continue;
  2196. /* Expand the array... */
  2197. t = krealloc(wm8996->retune_mobile_texts,
  2198. sizeof(char *) *
  2199. (wm8996->num_retune_mobile_texts + 1),
  2200. GFP_KERNEL);
  2201. if (t == NULL)
  2202. continue;
  2203. /* ...store the new entry... */
  2204. t[wm8996->num_retune_mobile_texts] =
  2205. pdata->retune_mobile_cfgs[i].name;
  2206. /* ...and remember the new version. */
  2207. wm8996->num_retune_mobile_texts++;
  2208. wm8996->retune_mobile_texts = t;
  2209. }
  2210. dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
  2211. wm8996->num_retune_mobile_texts);
  2212. wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts;
  2213. wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
  2214. ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
  2215. if (ret != 0)
  2216. dev_err(component->dev,
  2217. "Failed to add ReTune Mobile controls: %d\n", ret);
  2218. }
  2219. static const struct regmap_config wm8996_regmap = {
  2220. .reg_bits = 16,
  2221. .val_bits = 16,
  2222. .max_register = WM8996_MAX_REGISTER,
  2223. .reg_defaults = wm8996_reg,
  2224. .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
  2225. .volatile_reg = wm8996_volatile_register,
  2226. .readable_reg = wm8996_readable_register,
  2227. .cache_type = REGCACHE_RBTREE,
  2228. };
  2229. static int wm8996_probe(struct snd_soc_component *component)
  2230. {
  2231. int ret;
  2232. struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
  2233. struct i2c_client *i2c = to_i2c_client(component->dev);
  2234. int irq_flags;
  2235. wm8996->component = component;
  2236. init_completion(&wm8996->dcs_done);
  2237. init_completion(&wm8996->fll_lock);
  2238. if (wm8996->pdata.num_retune_mobile_cfgs)
  2239. wm8996_retune_mobile_pdata(component);
  2240. else
  2241. snd_soc_add_component_controls(component, wm8996_eq_controls,
  2242. ARRAY_SIZE(wm8996_eq_controls));
  2243. if (i2c->irq) {
  2244. if (wm8996->pdata.irq_flags)
  2245. irq_flags = wm8996->pdata.irq_flags;
  2246. else
  2247. irq_flags = IRQF_TRIGGER_LOW;
  2248. irq_flags |= IRQF_ONESHOT;
  2249. if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
  2250. ret = request_threaded_irq(i2c->irq, NULL,
  2251. wm8996_edge_irq,
  2252. irq_flags, "wm8996", component);
  2253. else
  2254. ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
  2255. irq_flags, "wm8996", component);
  2256. if (ret == 0) {
  2257. /* Unmask the interrupt */
  2258. snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL,
  2259. WM8996_IM_IRQ, 0);
  2260. /* Enable error reporting and DC servo status */
  2261. snd_soc_component_update_bits(component,
  2262. WM8996_INTERRUPT_STATUS_2_MASK,
  2263. WM8996_IM_DCS_DONE_23_EINT |
  2264. WM8996_IM_DCS_DONE_01_EINT |
  2265. WM8996_IM_FLL_LOCK_EINT |
  2266. WM8996_IM_FIFOS_ERR_EINT,
  2267. 0);
  2268. } else {
  2269. dev_err(component->dev, "Failed to request IRQ: %d\n",
  2270. ret);
  2271. return ret;
  2272. }
  2273. }
  2274. return 0;
  2275. }
  2276. static void wm8996_remove(struct snd_soc_component *component)
  2277. {
  2278. struct i2c_client *i2c = to_i2c_client(component->dev);
  2279. snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL,
  2280. WM8996_IM_IRQ, WM8996_IM_IRQ);
  2281. if (i2c->irq)
  2282. free_irq(i2c->irq, component);
  2283. }
  2284. static const struct snd_soc_component_driver soc_component_dev_wm8996 = {
  2285. .probe = wm8996_probe,
  2286. .remove = wm8996_remove,
  2287. .set_bias_level = wm8996_set_bias_level,
  2288. .seq_notifier = wm8996_seq_notifier,
  2289. .controls = wm8996_snd_controls,
  2290. .num_controls = ARRAY_SIZE(wm8996_snd_controls),
  2291. .dapm_widgets = wm8996_dapm_widgets,
  2292. .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
  2293. .dapm_routes = wm8996_dapm_routes,
  2294. .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
  2295. .set_pll = wm8996_set_fll,
  2296. .use_pmdown_time = 1,
  2297. .endianness = 1,
  2298. .non_legacy_dai_naming = 1,
  2299. };
  2300. #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  2301. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
  2302. SNDRV_PCM_RATE_48000)
  2303. #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
  2304. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
  2305. SNDRV_PCM_FMTBIT_S32_LE)
  2306. static const struct snd_soc_dai_ops wm8996_dai_ops = {
  2307. .set_fmt = wm8996_set_fmt,
  2308. .hw_params = wm8996_hw_params,
  2309. .set_sysclk = wm8996_set_sysclk,
  2310. };
  2311. static struct snd_soc_dai_driver wm8996_dai[] = {
  2312. {
  2313. .name = "wm8996-aif1",
  2314. .playback = {
  2315. .stream_name = "AIF1 Playback",
  2316. .channels_min = 1,
  2317. .channels_max = 6,
  2318. .rates = WM8996_RATES,
  2319. .formats = WM8996_FORMATS,
  2320. .sig_bits = 24,
  2321. },
  2322. .capture = {
  2323. .stream_name = "AIF1 Capture",
  2324. .channels_min = 1,
  2325. .channels_max = 6,
  2326. .rates = WM8996_RATES,
  2327. .formats = WM8996_FORMATS,
  2328. .sig_bits = 24,
  2329. },
  2330. .ops = &wm8996_dai_ops,
  2331. },
  2332. {
  2333. .name = "wm8996-aif2",
  2334. .playback = {
  2335. .stream_name = "AIF2 Playback",
  2336. .channels_min = 1,
  2337. .channels_max = 2,
  2338. .rates = WM8996_RATES,
  2339. .formats = WM8996_FORMATS,
  2340. .sig_bits = 24,
  2341. },
  2342. .capture = {
  2343. .stream_name = "AIF2 Capture",
  2344. .channels_min = 1,
  2345. .channels_max = 2,
  2346. .rates = WM8996_RATES,
  2347. .formats = WM8996_FORMATS,
  2348. .sig_bits = 24,
  2349. },
  2350. .ops = &wm8996_dai_ops,
  2351. },
  2352. };
  2353. static int wm8996_i2c_probe(struct i2c_client *i2c,
  2354. const struct i2c_device_id *id)
  2355. {
  2356. struct wm8996_priv *wm8996;
  2357. int ret, i;
  2358. unsigned int reg;
  2359. wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
  2360. GFP_KERNEL);
  2361. if (wm8996 == NULL)
  2362. return -ENOMEM;
  2363. i2c_set_clientdata(i2c, wm8996);
  2364. wm8996->dev = &i2c->dev;
  2365. if (dev_get_platdata(&i2c->dev))
  2366. memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
  2367. sizeof(wm8996->pdata));
  2368. if (wm8996->pdata.ldo_ena > 0) {
  2369. ret = gpio_request_one(wm8996->pdata.ldo_ena,
  2370. GPIOF_OUT_INIT_LOW, "WM8996 ENA");
  2371. if (ret < 0) {
  2372. dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
  2373. wm8996->pdata.ldo_ena, ret);
  2374. goto err;
  2375. }
  2376. }
  2377. for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
  2378. wm8996->supplies[i].supply = wm8996_supply_names[i];
  2379. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
  2380. wm8996->supplies);
  2381. if (ret != 0) {
  2382. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  2383. goto err_gpio;
  2384. }
  2385. wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
  2386. wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
  2387. wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
  2388. /* This should really be moved into the regulator core */
  2389. for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
  2390. ret = devm_regulator_register_notifier(
  2391. wm8996->supplies[i].consumer,
  2392. &wm8996->disable_nb[i]);
  2393. if (ret != 0) {
  2394. dev_err(&i2c->dev,
  2395. "Failed to register regulator notifier: %d\n",
  2396. ret);
  2397. }
  2398. }
  2399. ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
  2400. wm8996->supplies);
  2401. if (ret != 0) {
  2402. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  2403. goto err_gpio;
  2404. }
  2405. if (wm8996->pdata.ldo_ena > 0) {
  2406. gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
  2407. msleep(5);
  2408. }
  2409. wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
  2410. if (IS_ERR(wm8996->regmap)) {
  2411. ret = PTR_ERR(wm8996->regmap);
  2412. dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
  2413. goto err_enable;
  2414. }
  2415. ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
  2416. if (ret < 0) {
  2417. dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
  2418. goto err_regmap;
  2419. }
  2420. if (reg != 0x8915) {
  2421. dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
  2422. ret = -EINVAL;
  2423. goto err_regmap;
  2424. }
  2425. ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
  2426. if (ret < 0) {
  2427. dev_err(&i2c->dev, "Failed to read device revision: %d\n",
  2428. ret);
  2429. goto err_regmap;
  2430. }
  2431. dev_info(&i2c->dev, "revision %c\n",
  2432. (reg & WM8996_CHIP_REV_MASK) + 'A');
  2433. if (wm8996->pdata.ldo_ena > 0) {
  2434. gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
  2435. regcache_cache_only(wm8996->regmap, true);
  2436. } else {
  2437. ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
  2438. 0x8915);
  2439. if (ret != 0) {
  2440. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  2441. goto err_regmap;
  2442. }
  2443. }
  2444. regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
  2445. /* Apply platform data settings */
  2446. regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
  2447. WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
  2448. wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
  2449. wm8996->pdata.inr_mode);
  2450. for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
  2451. if (!wm8996->pdata.gpio_default[i])
  2452. continue;
  2453. regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
  2454. wm8996->pdata.gpio_default[i] & 0xffff);
  2455. }
  2456. if (wm8996->pdata.spkmute_seq)
  2457. regmap_update_bits(wm8996->regmap,
  2458. WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
  2459. WM8996_SPK_MUTE_ENDIAN |
  2460. WM8996_SPK_MUTE_SEQ1_MASK,
  2461. wm8996->pdata.spkmute_seq);
  2462. regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
  2463. WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
  2464. WM8996_MICD_SRC, wm8996->pdata.micdet_def);
  2465. /* Latch volume update bits */
  2466. regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
  2467. WM8996_IN1_VU, WM8996_IN1_VU);
  2468. regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
  2469. WM8996_IN1_VU, WM8996_IN1_VU);
  2470. regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
  2471. WM8996_DAC1_VU, WM8996_DAC1_VU);
  2472. regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
  2473. WM8996_DAC1_VU, WM8996_DAC1_VU);
  2474. regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
  2475. WM8996_DAC2_VU, WM8996_DAC2_VU);
  2476. regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
  2477. WM8996_DAC2_VU, WM8996_DAC2_VU);
  2478. regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
  2479. WM8996_DAC1_VU, WM8996_DAC1_VU);
  2480. regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
  2481. WM8996_DAC1_VU, WM8996_DAC1_VU);
  2482. regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
  2483. WM8996_DAC2_VU, WM8996_DAC2_VU);
  2484. regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
  2485. WM8996_DAC2_VU, WM8996_DAC2_VU);
  2486. regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
  2487. WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
  2488. regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
  2489. WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
  2490. regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
  2491. WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
  2492. regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
  2493. WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
  2494. regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
  2495. WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
  2496. regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
  2497. WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
  2498. regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
  2499. WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
  2500. regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
  2501. WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
  2502. /* No support currently for the underclocked TDM modes and
  2503. * pick a default TDM layout with each channel pair working with
  2504. * slots 0 and 1. */
  2505. regmap_update_bits(wm8996->regmap,
  2506. WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
  2507. WM8996_AIF1RX_CHAN0_SLOTS_MASK |
  2508. WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
  2509. 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
  2510. regmap_update_bits(wm8996->regmap,
  2511. WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
  2512. WM8996_AIF1RX_CHAN1_SLOTS_MASK |
  2513. WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
  2514. 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
  2515. regmap_update_bits(wm8996->regmap,
  2516. WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
  2517. WM8996_AIF1RX_CHAN2_SLOTS_MASK |
  2518. WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
  2519. 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
  2520. regmap_update_bits(wm8996->regmap,
  2521. WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
  2522. WM8996_AIF1RX_CHAN3_SLOTS_MASK |
  2523. WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
  2524. 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
  2525. regmap_update_bits(wm8996->regmap,
  2526. WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
  2527. WM8996_AIF1RX_CHAN4_SLOTS_MASK |
  2528. WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
  2529. 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
  2530. regmap_update_bits(wm8996->regmap,
  2531. WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
  2532. WM8996_AIF1RX_CHAN5_SLOTS_MASK |
  2533. WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
  2534. 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
  2535. regmap_update_bits(wm8996->regmap,
  2536. WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
  2537. WM8996_AIF2RX_CHAN0_SLOTS_MASK |
  2538. WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
  2539. 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
  2540. regmap_update_bits(wm8996->regmap,
  2541. WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
  2542. WM8996_AIF2RX_CHAN1_SLOTS_MASK |
  2543. WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
  2544. 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
  2545. regmap_update_bits(wm8996->regmap,
  2546. WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
  2547. WM8996_AIF1TX_CHAN0_SLOTS_MASK |
  2548. WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
  2549. 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
  2550. regmap_update_bits(wm8996->regmap,
  2551. WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
  2552. WM8996_AIF1TX_CHAN1_SLOTS_MASK |
  2553. WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
  2554. 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
  2555. regmap_update_bits(wm8996->regmap,
  2556. WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
  2557. WM8996_AIF1TX_CHAN2_SLOTS_MASK |
  2558. WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
  2559. 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
  2560. regmap_update_bits(wm8996->regmap,
  2561. WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
  2562. WM8996_AIF1TX_CHAN3_SLOTS_MASK |
  2563. WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
  2564. 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
  2565. regmap_update_bits(wm8996->regmap,
  2566. WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
  2567. WM8996_AIF1TX_CHAN4_SLOTS_MASK |
  2568. WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
  2569. 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
  2570. regmap_update_bits(wm8996->regmap,
  2571. WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
  2572. WM8996_AIF1TX_CHAN5_SLOTS_MASK |
  2573. WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
  2574. 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
  2575. regmap_update_bits(wm8996->regmap,
  2576. WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
  2577. WM8996_AIF2TX_CHAN0_SLOTS_MASK |
  2578. WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
  2579. 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
  2580. regmap_update_bits(wm8996->regmap,
  2581. WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
  2582. WM8996_AIF2TX_CHAN1_SLOTS_MASK |
  2583. WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
  2584. 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
  2585. /* If the TX LRCLK pins are not in LRCLK mode configure the
  2586. * AIFs to source their clocks from the RX LRCLKs.
  2587. */
  2588. ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, &reg);
  2589. if (ret != 0) {
  2590. dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
  2591. goto err_regmap;
  2592. }
  2593. if (reg & WM8996_GP1_FN_MASK)
  2594. regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
  2595. WM8996_AIF1TX_LRCLK_MODE,
  2596. WM8996_AIF1TX_LRCLK_MODE);
  2597. ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, &reg);
  2598. if (ret != 0) {
  2599. dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
  2600. goto err_regmap;
  2601. }
  2602. if (reg & WM8996_GP2_FN_MASK)
  2603. regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
  2604. WM8996_AIF2TX_LRCLK_MODE,
  2605. WM8996_AIF2TX_LRCLK_MODE);
  2606. wm8996_init_gpio(wm8996);
  2607. ret = devm_snd_soc_register_component(&i2c->dev,
  2608. &soc_component_dev_wm8996, wm8996_dai,
  2609. ARRAY_SIZE(wm8996_dai));
  2610. if (ret < 0)
  2611. goto err_gpiolib;
  2612. return ret;
  2613. err_gpiolib:
  2614. wm8996_free_gpio(wm8996);
  2615. err_regmap:
  2616. err_enable:
  2617. if (wm8996->pdata.ldo_ena > 0)
  2618. gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
  2619. regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
  2620. err_gpio:
  2621. if (wm8996->pdata.ldo_ena > 0)
  2622. gpio_free(wm8996->pdata.ldo_ena);
  2623. err:
  2624. return ret;
  2625. }
  2626. static int wm8996_i2c_remove(struct i2c_client *client)
  2627. {
  2628. struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
  2629. wm8996_free_gpio(wm8996);
  2630. if (wm8996->pdata.ldo_ena > 0) {
  2631. gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
  2632. gpio_free(wm8996->pdata.ldo_ena);
  2633. }
  2634. return 0;
  2635. }
  2636. static const struct i2c_device_id wm8996_i2c_id[] = {
  2637. { "wm8996", 0 },
  2638. { }
  2639. };
  2640. MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
  2641. static struct i2c_driver wm8996_i2c_driver = {
  2642. .driver = {
  2643. .name = "wm8996",
  2644. },
  2645. .probe = wm8996_i2c_probe,
  2646. .remove = wm8996_i2c_remove,
  2647. .id_table = wm8996_i2c_id,
  2648. };
  2649. module_i2c_driver(wm8996_i2c_driver);
  2650. MODULE_DESCRIPTION("ASoC WM8996 driver");
  2651. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  2652. MODULE_LICENSE("GPL");