wm8994.c 133 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8994.c -- WM8994 ALSA SoC Audio driver
  4. *
  5. * Copyright 2009-12 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/gcd.h>
  15. #include <linux/i2c.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/slab.h>
  20. #include <sound/core.h>
  21. #include <sound/jack.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include <trace/events/asoc.h>
  28. #include <linux/mfd/wm8994/core.h>
  29. #include <linux/mfd/wm8994/registers.h>
  30. #include <linux/mfd/wm8994/pdata.h>
  31. #include <linux/mfd/wm8994/gpio.h>
  32. #include "wm8994.h"
  33. #include "wm_hubs.h"
  34. #define WM1811_JACKDET_MODE_NONE 0x0000
  35. #define WM1811_JACKDET_MODE_JACK 0x0100
  36. #define WM1811_JACKDET_MODE_MIC 0x0080
  37. #define WM1811_JACKDET_MODE_AUDIO 0x0180
  38. #define WM8994_NUM_DRC 3
  39. #define WM8994_NUM_EQ 3
  40. struct wm8994_reg_mask {
  41. unsigned int reg;
  42. unsigned int mask;
  43. };
  44. static struct wm8994_reg_mask wm8994_vu_bits[] = {
  45. { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  46. { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  47. { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  48. { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  49. { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  50. { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  51. { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  52. { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  53. { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  54. { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  55. { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  56. { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  57. { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  58. { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  59. { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  60. { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  61. { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  62. { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  63. { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  64. { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  65. { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  66. { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  67. };
  68. /* VU bitfields for ADC2, DAC2 not available on WM1811 */
  69. static struct wm8994_reg_mask wm8994_adc2_dac2_vu_bits[] = {
  70. { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  71. { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  72. { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  73. { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  74. };
  75. static int wm8994_drc_base[] = {
  76. WM8994_AIF1_DRC1_1,
  77. WM8994_AIF1_DRC2_1,
  78. WM8994_AIF2_DRC_1,
  79. };
  80. static int wm8994_retune_mobile_base[] = {
  81. WM8994_AIF1_DAC1_EQ_GAINS_1,
  82. WM8994_AIF1_DAC2_EQ_GAINS_1,
  83. WM8994_AIF2_EQ_GAINS_1,
  84. };
  85. static const struct wm8958_micd_rate micdet_rates[] = {
  86. { 32768, true, 1, 4 },
  87. { 32768, false, 1, 1 },
  88. { 44100 * 256, true, 7, 10 },
  89. { 44100 * 256, false, 7, 10 },
  90. };
  91. static const struct wm8958_micd_rate jackdet_rates[] = {
  92. { 32768, true, 0, 1 },
  93. { 32768, false, 0, 1 },
  94. { 44100 * 256, true, 10, 10 },
  95. { 44100 * 256, false, 7, 8 },
  96. };
  97. static void wm8958_micd_set_rate(struct snd_soc_component *component)
  98. {
  99. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  100. struct wm8994 *control = wm8994->wm8994;
  101. int best, i, sysclk, val;
  102. bool idle;
  103. const struct wm8958_micd_rate *rates;
  104. int num_rates;
  105. idle = !wm8994->jack_mic;
  106. sysclk = snd_soc_component_read(component, WM8994_CLOCKING_1);
  107. if (sysclk & WM8994_SYSCLK_SRC)
  108. sysclk = wm8994->aifclk[1];
  109. else
  110. sysclk = wm8994->aifclk[0];
  111. if (control->pdata.micd_rates) {
  112. rates = control->pdata.micd_rates;
  113. num_rates = control->pdata.num_micd_rates;
  114. } else if (wm8994->jackdet) {
  115. rates = jackdet_rates;
  116. num_rates = ARRAY_SIZE(jackdet_rates);
  117. } else {
  118. rates = micdet_rates;
  119. num_rates = ARRAY_SIZE(micdet_rates);
  120. }
  121. best = 0;
  122. for (i = 0; i < num_rates; i++) {
  123. if (rates[i].idle != idle)
  124. continue;
  125. if (abs(rates[i].sysclk - sysclk) <
  126. abs(rates[best].sysclk - sysclk))
  127. best = i;
  128. else if (rates[best].idle != idle)
  129. best = i;
  130. }
  131. val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
  132. | rates[best].rate << WM8958_MICD_RATE_SHIFT;
  133. dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n",
  134. rates[best].start, rates[best].rate, sysclk,
  135. idle ? "idle" : "active");
  136. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
  137. WM8958_MICD_BIAS_STARTTIME_MASK |
  138. WM8958_MICD_RATE_MASK, val);
  139. }
  140. static int configure_aif_clock(struct snd_soc_component *component, int aif)
  141. {
  142. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  143. int rate;
  144. int reg1 = 0;
  145. int offset;
  146. if (aif)
  147. offset = 4;
  148. else
  149. offset = 0;
  150. switch (wm8994->sysclk[aif]) {
  151. case WM8994_SYSCLK_MCLK1:
  152. rate = wm8994->mclk_rate[0];
  153. break;
  154. case WM8994_SYSCLK_MCLK2:
  155. reg1 |= 0x8;
  156. rate = wm8994->mclk_rate[1];
  157. break;
  158. case WM8994_SYSCLK_FLL1:
  159. reg1 |= 0x10;
  160. rate = wm8994->fll[0].out;
  161. break;
  162. case WM8994_SYSCLK_FLL2:
  163. reg1 |= 0x18;
  164. rate = wm8994->fll[1].out;
  165. break;
  166. default:
  167. return -EINVAL;
  168. }
  169. if (rate >= 13500000) {
  170. rate /= 2;
  171. reg1 |= WM8994_AIF1CLK_DIV;
  172. dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
  173. aif + 1, rate);
  174. }
  175. wm8994->aifclk[aif] = rate;
  176. snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset,
  177. WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
  178. reg1);
  179. return 0;
  180. }
  181. static int configure_clock(struct snd_soc_component *component)
  182. {
  183. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  184. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  185. int change, new;
  186. /* Bring up the AIF clocks first */
  187. configure_aif_clock(component, 0);
  188. configure_aif_clock(component, 1);
  189. /* Then switch CLK_SYS over to the higher of them; a change
  190. * can only happen as a result of a clocking change which can
  191. * only be made outside of DAPM so we can safely redo the
  192. * clocking.
  193. */
  194. /* If they're equal it doesn't matter which is used */
  195. if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
  196. wm8958_micd_set_rate(component);
  197. return 0;
  198. }
  199. if (wm8994->aifclk[0] < wm8994->aifclk[1])
  200. new = WM8994_SYSCLK_SRC;
  201. else
  202. new = 0;
  203. change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  204. WM8994_SYSCLK_SRC, new);
  205. if (change)
  206. snd_soc_dapm_sync(dapm);
  207. wm8958_micd_set_rate(component);
  208. return 0;
  209. }
  210. static int check_clk_sys(struct snd_soc_dapm_widget *source,
  211. struct snd_soc_dapm_widget *sink)
  212. {
  213. struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
  214. int reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
  215. const char *clk;
  216. /* Check what we're currently using for CLK_SYS */
  217. if (reg & WM8994_SYSCLK_SRC)
  218. clk = "AIF2CLK";
  219. else
  220. clk = "AIF1CLK";
  221. return strcmp(source->name, clk) == 0;
  222. }
  223. static const char *sidetone_hpf_text[] = {
  224. "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
  225. };
  226. static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
  227. WM8994_SIDETONE, 7, sidetone_hpf_text);
  228. static const char *adc_hpf_text[] = {
  229. "HiFi", "Voice 1", "Voice 2", "Voice 3"
  230. };
  231. static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
  232. WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
  233. static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
  234. WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
  235. static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
  236. WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
  237. static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
  238. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  239. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  240. static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
  241. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  242. static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
  243. #define WM8994_DRC_SWITCH(xname, reg, shift) \
  244. SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
  245. snd_soc_get_volsw, wm8994_put_drc_sw)
  246. static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
  247. struct snd_ctl_elem_value *ucontrol)
  248. {
  249. struct soc_mixer_control *mc =
  250. (struct soc_mixer_control *)kcontrol->private_value;
  251. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  252. int mask, ret;
  253. /* Can't enable both ADC and DAC paths simultaneously */
  254. if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
  255. mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
  256. WM8994_AIF1ADC1R_DRC_ENA_MASK;
  257. else
  258. mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
  259. ret = snd_soc_component_read(component, mc->reg);
  260. if (ret < 0)
  261. return ret;
  262. if (ret & mask)
  263. return -EINVAL;
  264. return snd_soc_put_volsw(kcontrol, ucontrol);
  265. }
  266. static void wm8994_set_drc(struct snd_soc_component *component, int drc)
  267. {
  268. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  269. struct wm8994 *control = wm8994->wm8994;
  270. struct wm8994_pdata *pdata = &control->pdata;
  271. int base = wm8994_drc_base[drc];
  272. int cfg = wm8994->drc_cfg[drc];
  273. int save, i;
  274. /* Save any enables; the configuration should clear them. */
  275. save = snd_soc_component_read(component, base);
  276. save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
  277. WM8994_AIF1ADC1R_DRC_ENA;
  278. for (i = 0; i < WM8994_DRC_REGS; i++)
  279. snd_soc_component_update_bits(component, base + i, 0xffff,
  280. pdata->drc_cfgs[cfg].regs[i]);
  281. snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA |
  282. WM8994_AIF1ADC1L_DRC_ENA |
  283. WM8994_AIF1ADC1R_DRC_ENA, save);
  284. }
  285. /* Icky as hell but saves code duplication */
  286. static int wm8994_get_drc(const char *name)
  287. {
  288. if (strcmp(name, "AIF1DRC1 Mode") == 0)
  289. return 0;
  290. if (strcmp(name, "AIF1DRC2 Mode") == 0)
  291. return 1;
  292. if (strcmp(name, "AIF2DRC Mode") == 0)
  293. return 2;
  294. return -EINVAL;
  295. }
  296. static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
  297. struct snd_ctl_elem_value *ucontrol)
  298. {
  299. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  300. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  301. struct wm8994 *control = wm8994->wm8994;
  302. struct wm8994_pdata *pdata = &control->pdata;
  303. int drc = wm8994_get_drc(kcontrol->id.name);
  304. int value = ucontrol->value.enumerated.item[0];
  305. if (drc < 0)
  306. return drc;
  307. if (value >= pdata->num_drc_cfgs)
  308. return -EINVAL;
  309. wm8994->drc_cfg[drc] = value;
  310. wm8994_set_drc(component, drc);
  311. return 0;
  312. }
  313. static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
  314. struct snd_ctl_elem_value *ucontrol)
  315. {
  316. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  317. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  318. int drc = wm8994_get_drc(kcontrol->id.name);
  319. if (drc < 0)
  320. return drc;
  321. ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
  322. return 0;
  323. }
  324. static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block)
  325. {
  326. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  327. struct wm8994 *control = wm8994->wm8994;
  328. struct wm8994_pdata *pdata = &control->pdata;
  329. int base = wm8994_retune_mobile_base[block];
  330. int iface, best, best_val, save, i, cfg;
  331. if (!pdata || !wm8994->num_retune_mobile_texts)
  332. return;
  333. switch (block) {
  334. case 0:
  335. case 1:
  336. iface = 0;
  337. break;
  338. case 2:
  339. iface = 1;
  340. break;
  341. default:
  342. return;
  343. }
  344. /* Find the version of the currently selected configuration
  345. * with the nearest sample rate. */
  346. cfg = wm8994->retune_mobile_cfg[block];
  347. best = 0;
  348. best_val = INT_MAX;
  349. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  350. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  351. wm8994->retune_mobile_texts[cfg]) == 0 &&
  352. abs(pdata->retune_mobile_cfgs[i].rate
  353. - wm8994->dac_rates[iface]) < best_val) {
  354. best = i;
  355. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  356. - wm8994->dac_rates[iface]);
  357. }
  358. }
  359. dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
  360. block,
  361. pdata->retune_mobile_cfgs[best].name,
  362. pdata->retune_mobile_cfgs[best].rate,
  363. wm8994->dac_rates[iface]);
  364. /* The EQ will be disabled while reconfiguring it, remember the
  365. * current configuration.
  366. */
  367. save = snd_soc_component_read(component, base);
  368. save &= WM8994_AIF1DAC1_EQ_ENA;
  369. for (i = 0; i < WM8994_EQ_REGS; i++)
  370. snd_soc_component_update_bits(component, base + i, 0xffff,
  371. pdata->retune_mobile_cfgs[best].regs[i]);
  372. snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save);
  373. }
  374. /* Icky as hell but saves code duplication */
  375. static int wm8994_get_retune_mobile_block(const char *name)
  376. {
  377. if (strcmp(name, "AIF1.1 EQ Mode") == 0)
  378. return 0;
  379. if (strcmp(name, "AIF1.2 EQ Mode") == 0)
  380. return 1;
  381. if (strcmp(name, "AIF2 EQ Mode") == 0)
  382. return 2;
  383. return -EINVAL;
  384. }
  385. static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  386. struct snd_ctl_elem_value *ucontrol)
  387. {
  388. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  389. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  390. struct wm8994 *control = wm8994->wm8994;
  391. struct wm8994_pdata *pdata = &control->pdata;
  392. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  393. int value = ucontrol->value.enumerated.item[0];
  394. if (block < 0)
  395. return block;
  396. if (value >= pdata->num_retune_mobile_cfgs)
  397. return -EINVAL;
  398. wm8994->retune_mobile_cfg[block] = value;
  399. wm8994_set_retune_mobile(component, block);
  400. return 0;
  401. }
  402. static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  403. struct snd_ctl_elem_value *ucontrol)
  404. {
  405. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  406. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  407. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  408. if (block < 0)
  409. return block;
  410. ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
  411. return 0;
  412. }
  413. static const char *aif_chan_src_text[] = {
  414. "Left", "Right"
  415. };
  416. static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
  417. WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
  418. static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
  419. WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
  420. static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
  421. WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
  422. static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
  423. WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
  424. static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
  425. WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
  426. static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
  427. WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
  428. static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
  429. WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
  430. static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
  431. WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
  432. static const char *osr_text[] = {
  433. "Low Power", "High Performance",
  434. };
  435. static SOC_ENUM_SINGLE_DECL(dac_osr,
  436. WM8994_OVERSAMPLING, 0, osr_text);
  437. static SOC_ENUM_SINGLE_DECL(adc_osr,
  438. WM8994_OVERSAMPLING, 1, osr_text);
  439. static const struct snd_kcontrol_new wm8994_common_snd_controls[] = {
  440. SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
  441. WM8994_AIF1_ADC1_RIGHT_VOLUME,
  442. 1, 119, 0, digital_tlv),
  443. SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
  444. WM8994_AIF2_ADC_RIGHT_VOLUME,
  445. 1, 119, 0, digital_tlv),
  446. SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
  447. SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
  448. SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
  449. SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
  450. SOC_ENUM("AIF1DACL Source", aif1dacl_src),
  451. SOC_ENUM("AIF1DACR Source", aif1dacr_src),
  452. SOC_ENUM("AIF2DACL Source", aif2dacl_src),
  453. SOC_ENUM("AIF2DACR Source", aif2dacr_src),
  454. SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
  455. WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  456. SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
  457. WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  458. SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
  459. SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
  460. SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
  461. SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
  462. WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
  463. WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
  464. WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
  465. WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
  466. WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
  467. WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
  468. SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  469. 5, 12, 0, st_tlv),
  470. SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  471. 0, 12, 0, st_tlv),
  472. SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  473. 5, 12, 0, st_tlv),
  474. SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  475. 0, 12, 0, st_tlv),
  476. SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
  477. SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
  478. SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
  479. SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
  480. SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
  481. SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
  482. SOC_ENUM("ADC OSR", adc_osr),
  483. SOC_ENUM("DAC OSR", dac_osr),
  484. SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
  485. WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  486. SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
  487. WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
  488. SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
  489. WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  490. SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
  491. WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
  492. SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
  493. 6, 1, 1, wm_hubs_spkmix_tlv),
  494. SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
  495. 2, 1, 1, wm_hubs_spkmix_tlv),
  496. SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
  497. 6, 1, 1, wm_hubs_spkmix_tlv),
  498. SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
  499. 2, 1, 1, wm_hubs_spkmix_tlv),
  500. SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
  501. 10, 15, 0, wm8994_3d_tlv),
  502. SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
  503. 8, 1, 0),
  504. SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
  505. 10, 15, 0, wm8994_3d_tlv),
  506. SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
  507. 8, 1, 0),
  508. SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
  509. 10, 15, 0, wm8994_3d_tlv),
  510. SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
  511. 8, 1, 0),
  512. };
  513. /* Controls not available on WM1811 */
  514. static const struct snd_kcontrol_new wm8994_snd_controls[] = {
  515. SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
  516. WM8994_AIF1_ADC2_RIGHT_VOLUME,
  517. 1, 119, 0, digital_tlv),
  518. SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
  519. WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  520. SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
  521. WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
  522. WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
  523. WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
  524. SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
  525. SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
  526. };
  527. static const struct snd_kcontrol_new wm8994_eq_controls[] = {
  528. SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
  529. eq_tlv),
  530. SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
  531. eq_tlv),
  532. SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
  533. eq_tlv),
  534. SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
  535. eq_tlv),
  536. SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
  537. eq_tlv),
  538. SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
  539. eq_tlv),
  540. SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
  541. eq_tlv),
  542. SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
  543. eq_tlv),
  544. SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
  545. eq_tlv),
  546. SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
  547. eq_tlv),
  548. SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
  549. eq_tlv),
  550. SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
  551. eq_tlv),
  552. SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
  553. eq_tlv),
  554. SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
  555. eq_tlv),
  556. SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
  557. eq_tlv),
  558. };
  559. static const struct snd_kcontrol_new wm8994_drc_controls[] = {
  560. SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
  561. WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
  562. WM8994_AIF1ADC1R_DRC_ENA),
  563. SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
  564. WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
  565. WM8994_AIF1ADC2R_DRC_ENA),
  566. SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
  567. WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
  568. WM8994_AIF2ADCR_DRC_ENA),
  569. };
  570. static const char *wm8958_ng_text[] = {
  571. "30ms", "125ms", "250ms", "500ms",
  572. };
  573. static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
  574. WM8958_AIF1_DAC1_NOISE_GATE,
  575. WM8958_AIF1DAC1_NG_THR_SHIFT,
  576. wm8958_ng_text);
  577. static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
  578. WM8958_AIF1_DAC2_NOISE_GATE,
  579. WM8958_AIF1DAC2_NG_THR_SHIFT,
  580. wm8958_ng_text);
  581. static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
  582. WM8958_AIF2_DAC_NOISE_GATE,
  583. WM8958_AIF2DAC_NG_THR_SHIFT,
  584. wm8958_ng_text);
  585. static const struct snd_kcontrol_new wm8958_snd_controls[] = {
  586. SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
  587. SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
  588. WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
  589. SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
  590. SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
  591. WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
  592. 7, 1, ng_tlv),
  593. SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
  594. WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
  595. SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
  596. SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
  597. WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
  598. 7, 1, ng_tlv),
  599. SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
  600. WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
  601. SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
  602. SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
  603. WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
  604. 7, 1, ng_tlv),
  605. };
  606. /* We run all mode setting through a function to enforce audio mode */
  607. static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
  608. {
  609. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  610. if (!wm8994->jackdet || !wm8994->micdet[0].jack)
  611. return;
  612. if (wm8994->active_refcount)
  613. mode = WM1811_JACKDET_MODE_AUDIO;
  614. if (mode == wm8994->jackdet_mode)
  615. return;
  616. wm8994->jackdet_mode = mode;
  617. /* Always use audio mode to detect while the system is active */
  618. if (mode != WM1811_JACKDET_MODE_NONE)
  619. mode = WM1811_JACKDET_MODE_AUDIO;
  620. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  621. WM1811_JACKDET_MODE_MASK, mode);
  622. }
  623. static void active_reference(struct snd_soc_component *component)
  624. {
  625. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  626. mutex_lock(&wm8994->accdet_lock);
  627. wm8994->active_refcount++;
  628. dev_dbg(component->dev, "Active refcount incremented, now %d\n",
  629. wm8994->active_refcount);
  630. /* If we're using jack detection go into audio mode */
  631. wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO);
  632. mutex_unlock(&wm8994->accdet_lock);
  633. }
  634. static void active_dereference(struct snd_soc_component *component)
  635. {
  636. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  637. u16 mode;
  638. mutex_lock(&wm8994->accdet_lock);
  639. wm8994->active_refcount--;
  640. dev_dbg(component->dev, "Active refcount decremented, now %d\n",
  641. wm8994->active_refcount);
  642. if (wm8994->active_refcount == 0) {
  643. /* Go into appropriate detection only mode */
  644. if (wm8994->jack_mic || wm8994->mic_detecting)
  645. mode = WM1811_JACKDET_MODE_MIC;
  646. else
  647. mode = WM1811_JACKDET_MODE_JACK;
  648. wm1811_jackdet_set_mode(component, mode);
  649. }
  650. mutex_unlock(&wm8994->accdet_lock);
  651. }
  652. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  653. struct snd_kcontrol *kcontrol, int event)
  654. {
  655. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  656. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  657. switch (event) {
  658. case SND_SOC_DAPM_PRE_PMU:
  659. return configure_clock(component);
  660. case SND_SOC_DAPM_POST_PMU:
  661. /*
  662. * JACKDET won't run until we start the clock and it
  663. * only reports deltas, make sure we notify the state
  664. * up the stack on startup. Use a *very* generous
  665. * timeout for paranoia, there's no urgency and we
  666. * don't want false reports.
  667. */
  668. if (wm8994->jackdet && !wm8994->clk_has_run) {
  669. queue_delayed_work(system_power_efficient_wq,
  670. &wm8994->jackdet_bootstrap,
  671. msecs_to_jiffies(1000));
  672. wm8994->clk_has_run = true;
  673. }
  674. break;
  675. case SND_SOC_DAPM_POST_PMD:
  676. configure_clock(component);
  677. break;
  678. }
  679. return 0;
  680. }
  681. static void vmid_reference(struct snd_soc_component *component)
  682. {
  683. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  684. pm_runtime_get_sync(component->dev);
  685. wm8994->vmid_refcount++;
  686. dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n",
  687. wm8994->vmid_refcount);
  688. if (wm8994->vmid_refcount == 1) {
  689. snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
  690. WM8994_LINEOUT1_DISCH |
  691. WM8994_LINEOUT2_DISCH, 0);
  692. wm_hubs_vmid_ena(component);
  693. switch (wm8994->vmid_mode) {
  694. default:
  695. WARN_ON(NULL == "Invalid VMID mode");
  696. fallthrough;
  697. case WM8994_VMID_NORMAL:
  698. /* Startup bias, VMID ramp & buffer */
  699. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  700. WM8994_BIAS_SRC |
  701. WM8994_VMID_DISCH |
  702. WM8994_STARTUP_BIAS_ENA |
  703. WM8994_VMID_BUF_ENA |
  704. WM8994_VMID_RAMP_MASK,
  705. WM8994_BIAS_SRC |
  706. WM8994_STARTUP_BIAS_ENA |
  707. WM8994_VMID_BUF_ENA |
  708. (0x2 << WM8994_VMID_RAMP_SHIFT));
  709. /* Main bias enable, VMID=2x40k */
  710. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
  711. WM8994_BIAS_ENA |
  712. WM8994_VMID_SEL_MASK,
  713. WM8994_BIAS_ENA | 0x2);
  714. msleep(300);
  715. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  716. WM8994_VMID_RAMP_MASK |
  717. WM8994_BIAS_SRC,
  718. 0);
  719. break;
  720. case WM8994_VMID_FORCE:
  721. /* Startup bias, slow VMID ramp & buffer */
  722. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  723. WM8994_BIAS_SRC |
  724. WM8994_VMID_DISCH |
  725. WM8994_STARTUP_BIAS_ENA |
  726. WM8994_VMID_BUF_ENA |
  727. WM8994_VMID_RAMP_MASK,
  728. WM8994_BIAS_SRC |
  729. WM8994_STARTUP_BIAS_ENA |
  730. WM8994_VMID_BUF_ENA |
  731. (0x2 << WM8994_VMID_RAMP_SHIFT));
  732. /* Main bias enable, VMID=2x40k */
  733. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
  734. WM8994_BIAS_ENA |
  735. WM8994_VMID_SEL_MASK,
  736. WM8994_BIAS_ENA | 0x2);
  737. msleep(400);
  738. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  739. WM8994_VMID_RAMP_MASK |
  740. WM8994_BIAS_SRC,
  741. 0);
  742. break;
  743. }
  744. }
  745. }
  746. static void vmid_dereference(struct snd_soc_component *component)
  747. {
  748. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  749. wm8994->vmid_refcount--;
  750. dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n",
  751. wm8994->vmid_refcount);
  752. if (wm8994->vmid_refcount == 0) {
  753. if (wm8994->hubs.lineout1_se)
  754. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
  755. WM8994_LINEOUT1N_ENA |
  756. WM8994_LINEOUT1P_ENA,
  757. WM8994_LINEOUT1N_ENA |
  758. WM8994_LINEOUT1P_ENA);
  759. if (wm8994->hubs.lineout2_se)
  760. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
  761. WM8994_LINEOUT2N_ENA |
  762. WM8994_LINEOUT2P_ENA,
  763. WM8994_LINEOUT2N_ENA |
  764. WM8994_LINEOUT2P_ENA);
  765. /* Start discharging VMID */
  766. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  767. WM8994_BIAS_SRC |
  768. WM8994_VMID_DISCH,
  769. WM8994_BIAS_SRC |
  770. WM8994_VMID_DISCH);
  771. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
  772. WM8994_VMID_SEL_MASK, 0);
  773. msleep(400);
  774. /* Active discharge */
  775. snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
  776. WM8994_LINEOUT1_DISCH |
  777. WM8994_LINEOUT2_DISCH,
  778. WM8994_LINEOUT1_DISCH |
  779. WM8994_LINEOUT2_DISCH);
  780. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
  781. WM8994_LINEOUT1N_ENA |
  782. WM8994_LINEOUT1P_ENA |
  783. WM8994_LINEOUT2N_ENA |
  784. WM8994_LINEOUT2P_ENA, 0);
  785. /* Switch off startup biases */
  786. snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
  787. WM8994_BIAS_SRC |
  788. WM8994_STARTUP_BIAS_ENA |
  789. WM8994_VMID_BUF_ENA |
  790. WM8994_VMID_RAMP_MASK, 0);
  791. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
  792. WM8994_VMID_SEL_MASK, 0);
  793. }
  794. pm_runtime_put(component->dev);
  795. }
  796. static int vmid_event(struct snd_soc_dapm_widget *w,
  797. struct snd_kcontrol *kcontrol, int event)
  798. {
  799. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  800. switch (event) {
  801. case SND_SOC_DAPM_PRE_PMU:
  802. vmid_reference(component);
  803. break;
  804. case SND_SOC_DAPM_POST_PMD:
  805. vmid_dereference(component);
  806. break;
  807. }
  808. return 0;
  809. }
  810. static bool wm8994_check_class_w_digital(struct snd_soc_component *component)
  811. {
  812. int source = 0; /* GCC flow analysis can't track enable */
  813. int reg, reg_r;
  814. /* We also need the same AIF source for L/R and only one path */
  815. reg = snd_soc_component_read(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
  816. switch (reg) {
  817. case WM8994_AIF2DACL_TO_DAC1L:
  818. dev_vdbg(component->dev, "Class W source AIF2DAC\n");
  819. source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  820. break;
  821. case WM8994_AIF1DAC2L_TO_DAC1L:
  822. dev_vdbg(component->dev, "Class W source AIF1DAC2\n");
  823. source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  824. break;
  825. case WM8994_AIF1DAC1L_TO_DAC1L:
  826. dev_vdbg(component->dev, "Class W source AIF1DAC1\n");
  827. source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  828. break;
  829. default:
  830. dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg);
  831. return false;
  832. }
  833. reg_r = snd_soc_component_read(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
  834. if (reg_r != reg) {
  835. dev_vdbg(component->dev, "Left and right DAC mixers different\n");
  836. return false;
  837. }
  838. /* Set the source up */
  839. snd_soc_component_update_bits(component, WM8994_CLASS_W_1,
  840. WM8994_CP_DYN_SRC_SEL_MASK, source);
  841. return true;
  842. }
  843. static void wm8994_update_vu_bits(struct snd_soc_component *component)
  844. {
  845. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  846. struct wm8994 *control = wm8994->wm8994;
  847. int i;
  848. for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
  849. snd_soc_component_write(component, wm8994_vu_bits[i].reg,
  850. snd_soc_component_read(component,
  851. wm8994_vu_bits[i].reg));
  852. if (control->type == WM1811)
  853. return;
  854. for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++)
  855. snd_soc_component_write(component,
  856. wm8994_adc2_dac2_vu_bits[i].reg,
  857. snd_soc_component_read(component,
  858. wm8994_adc2_dac2_vu_bits[i].reg));
  859. }
  860. static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable)
  861. {
  862. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  863. unsigned int offset, val, clk_idx;
  864. int ret;
  865. if (aif)
  866. offset = 4;
  867. else
  868. offset = 0;
  869. val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset);
  870. val &= WM8994_AIF1CLK_SRC_MASK;
  871. switch (val) {
  872. case 0:
  873. clk_idx = WM8994_MCLK1;
  874. break;
  875. case 1:
  876. clk_idx = WM8994_MCLK2;
  877. break;
  878. default:
  879. return 0;
  880. }
  881. if (enable) {
  882. ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
  883. if (ret < 0) {
  884. dev_err(component->dev, "Failed to enable MCLK%d\n",
  885. clk_idx);
  886. return ret;
  887. }
  888. } else {
  889. clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
  890. }
  891. return 0;
  892. }
  893. static int aif1clk_ev(struct snd_soc_dapm_widget *w,
  894. struct snd_kcontrol *kcontrol, int event)
  895. {
  896. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  897. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  898. struct wm8994 *control = wm8994->wm8994;
  899. int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
  900. int ret;
  901. int dac;
  902. int adc;
  903. int val;
  904. switch (control->type) {
  905. case WM8994:
  906. case WM8958:
  907. mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
  908. break;
  909. default:
  910. break;
  911. }
  912. switch (event) {
  913. case SND_SOC_DAPM_PRE_PMU:
  914. ret = aif_mclk_set(component, 0, true);
  915. if (ret < 0)
  916. return ret;
  917. /* Don't enable timeslot 2 if not in use */
  918. if (wm8994->channels[0] <= 2)
  919. mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  920. val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_1);
  921. if ((val & WM8994_AIF1ADCL_SRC) &&
  922. (val & WM8994_AIF1ADCR_SRC))
  923. adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
  924. else if (!(val & WM8994_AIF1ADCL_SRC) &&
  925. !(val & WM8994_AIF1ADCR_SRC))
  926. adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
  927. else
  928. adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
  929. WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
  930. val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_2);
  931. if ((val & WM8994_AIF1DACL_SRC) &&
  932. (val & WM8994_AIF1DACR_SRC))
  933. dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
  934. else if (!(val & WM8994_AIF1DACL_SRC) &&
  935. !(val & WM8994_AIF1DACR_SRC))
  936. dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
  937. else
  938. dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
  939. WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
  940. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
  941. mask, adc);
  942. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
  943. mask, dac);
  944. snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  945. WM8994_AIF1DSPCLK_ENA |
  946. WM8994_SYSDSPCLK_ENA,
  947. WM8994_AIF1DSPCLK_ENA |
  948. WM8994_SYSDSPCLK_ENA);
  949. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask,
  950. WM8994_AIF1ADC1R_ENA |
  951. WM8994_AIF1ADC1L_ENA |
  952. WM8994_AIF1ADC2R_ENA |
  953. WM8994_AIF1ADC2L_ENA);
  954. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask,
  955. WM8994_AIF1DAC1R_ENA |
  956. WM8994_AIF1DAC1L_ENA |
  957. WM8994_AIF1DAC2R_ENA |
  958. WM8994_AIF1DAC2L_ENA);
  959. break;
  960. case SND_SOC_DAPM_POST_PMU:
  961. wm8994_update_vu_bits(component);
  962. break;
  963. case SND_SOC_DAPM_PRE_PMD:
  964. case SND_SOC_DAPM_POST_PMD:
  965. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
  966. mask, 0);
  967. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
  968. mask, 0);
  969. val = snd_soc_component_read(component, WM8994_CLOCKING_1);
  970. if (val & WM8994_AIF2DSPCLK_ENA)
  971. val = WM8994_SYSDSPCLK_ENA;
  972. else
  973. val = 0;
  974. snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  975. WM8994_SYSDSPCLK_ENA |
  976. WM8994_AIF1DSPCLK_ENA, val);
  977. break;
  978. }
  979. switch (event) {
  980. case SND_SOC_DAPM_POST_PMD:
  981. aif_mclk_set(component, 0, false);
  982. break;
  983. }
  984. return 0;
  985. }
  986. static int aif2clk_ev(struct snd_soc_dapm_widget *w,
  987. struct snd_kcontrol *kcontrol, int event)
  988. {
  989. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  990. int ret;
  991. int dac;
  992. int adc;
  993. int val;
  994. switch (event) {
  995. case SND_SOC_DAPM_PRE_PMU:
  996. ret = aif_mclk_set(component, 1, true);
  997. if (ret < 0)
  998. return ret;
  999. val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_1);
  1000. if ((val & WM8994_AIF2ADCL_SRC) &&
  1001. (val & WM8994_AIF2ADCR_SRC))
  1002. adc = WM8994_AIF2ADCR_ENA;
  1003. else if (!(val & WM8994_AIF2ADCL_SRC) &&
  1004. !(val & WM8994_AIF2ADCR_SRC))
  1005. adc = WM8994_AIF2ADCL_ENA;
  1006. else
  1007. adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
  1008. val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_2);
  1009. if ((val & WM8994_AIF2DACL_SRC) &&
  1010. (val & WM8994_AIF2DACR_SRC))
  1011. dac = WM8994_AIF2DACR_ENA;
  1012. else if (!(val & WM8994_AIF2DACL_SRC) &&
  1013. !(val & WM8994_AIF2DACR_SRC))
  1014. dac = WM8994_AIF2DACL_ENA;
  1015. else
  1016. dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
  1017. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
  1018. WM8994_AIF2ADCL_ENA |
  1019. WM8994_AIF2ADCR_ENA, adc);
  1020. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
  1021. WM8994_AIF2DACL_ENA |
  1022. WM8994_AIF2DACR_ENA, dac);
  1023. snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  1024. WM8994_AIF2DSPCLK_ENA |
  1025. WM8994_SYSDSPCLK_ENA,
  1026. WM8994_AIF2DSPCLK_ENA |
  1027. WM8994_SYSDSPCLK_ENA);
  1028. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
  1029. WM8994_AIF2ADCL_ENA |
  1030. WM8994_AIF2ADCR_ENA,
  1031. WM8994_AIF2ADCL_ENA |
  1032. WM8994_AIF2ADCR_ENA);
  1033. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
  1034. WM8994_AIF2DACL_ENA |
  1035. WM8994_AIF2DACR_ENA,
  1036. WM8994_AIF2DACL_ENA |
  1037. WM8994_AIF2DACR_ENA);
  1038. break;
  1039. case SND_SOC_DAPM_POST_PMU:
  1040. wm8994_update_vu_bits(component);
  1041. break;
  1042. case SND_SOC_DAPM_PRE_PMD:
  1043. case SND_SOC_DAPM_POST_PMD:
  1044. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
  1045. WM8994_AIF2DACL_ENA |
  1046. WM8994_AIF2DACR_ENA, 0);
  1047. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
  1048. WM8994_AIF2ADCL_ENA |
  1049. WM8994_AIF2ADCR_ENA, 0);
  1050. val = snd_soc_component_read(component, WM8994_CLOCKING_1);
  1051. if (val & WM8994_AIF1DSPCLK_ENA)
  1052. val = WM8994_SYSDSPCLK_ENA;
  1053. else
  1054. val = 0;
  1055. snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
  1056. WM8994_SYSDSPCLK_ENA |
  1057. WM8994_AIF2DSPCLK_ENA, val);
  1058. break;
  1059. }
  1060. switch (event) {
  1061. case SND_SOC_DAPM_POST_PMD:
  1062. aif_mclk_set(component, 1, false);
  1063. break;
  1064. }
  1065. return 0;
  1066. }
  1067. static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
  1068. struct snd_kcontrol *kcontrol, int event)
  1069. {
  1070. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1071. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  1072. switch (event) {
  1073. case SND_SOC_DAPM_PRE_PMU:
  1074. wm8994->aif1clk_enable = 1;
  1075. break;
  1076. case SND_SOC_DAPM_POST_PMD:
  1077. wm8994->aif1clk_disable = 1;
  1078. break;
  1079. }
  1080. return 0;
  1081. }
  1082. static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
  1083. struct snd_kcontrol *kcontrol, int event)
  1084. {
  1085. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1086. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  1087. switch (event) {
  1088. case SND_SOC_DAPM_PRE_PMU:
  1089. wm8994->aif2clk_enable = 1;
  1090. break;
  1091. case SND_SOC_DAPM_POST_PMD:
  1092. wm8994->aif2clk_disable = 1;
  1093. break;
  1094. }
  1095. return 0;
  1096. }
  1097. static int late_enable_ev(struct snd_soc_dapm_widget *w,
  1098. struct snd_kcontrol *kcontrol, int event)
  1099. {
  1100. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1101. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  1102. switch (event) {
  1103. case SND_SOC_DAPM_PRE_PMU:
  1104. if (wm8994->aif1clk_enable) {
  1105. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
  1106. snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
  1107. WM8994_AIF1CLK_ENA_MASK,
  1108. WM8994_AIF1CLK_ENA);
  1109. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
  1110. wm8994->aif1clk_enable = 0;
  1111. }
  1112. if (wm8994->aif2clk_enable) {
  1113. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
  1114. snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
  1115. WM8994_AIF2CLK_ENA_MASK,
  1116. WM8994_AIF2CLK_ENA);
  1117. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
  1118. wm8994->aif2clk_enable = 0;
  1119. }
  1120. break;
  1121. }
  1122. /* We may also have postponed startup of DSP, handle that. */
  1123. wm8958_aif_ev(w, kcontrol, event);
  1124. return 0;
  1125. }
  1126. static int late_disable_ev(struct snd_soc_dapm_widget *w,
  1127. struct snd_kcontrol *kcontrol, int event)
  1128. {
  1129. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1130. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  1131. switch (event) {
  1132. case SND_SOC_DAPM_POST_PMD:
  1133. if (wm8994->aif1clk_disable) {
  1134. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
  1135. snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
  1136. WM8994_AIF1CLK_ENA_MASK, 0);
  1137. aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
  1138. wm8994->aif1clk_disable = 0;
  1139. }
  1140. if (wm8994->aif2clk_disable) {
  1141. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
  1142. snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
  1143. WM8994_AIF2CLK_ENA_MASK, 0);
  1144. aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
  1145. wm8994->aif2clk_disable = 0;
  1146. }
  1147. break;
  1148. }
  1149. return 0;
  1150. }
  1151. static int adc_mux_ev(struct snd_soc_dapm_widget *w,
  1152. struct snd_kcontrol *kcontrol, int event)
  1153. {
  1154. late_enable_ev(w, kcontrol, event);
  1155. return 0;
  1156. }
  1157. static int micbias_ev(struct snd_soc_dapm_widget *w,
  1158. struct snd_kcontrol *kcontrol, int event)
  1159. {
  1160. late_enable_ev(w, kcontrol, event);
  1161. return 0;
  1162. }
  1163. static int dac_ev(struct snd_soc_dapm_widget *w,
  1164. struct snd_kcontrol *kcontrol, int event)
  1165. {
  1166. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1167. unsigned int mask = 1 << w->shift;
  1168. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
  1169. mask, mask);
  1170. return 0;
  1171. }
  1172. static const char *adc_mux_text[] = {
  1173. "ADC",
  1174. "DMIC",
  1175. };
  1176. static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
  1177. static const struct snd_kcontrol_new adcl_mux =
  1178. SOC_DAPM_ENUM("ADCL Mux", adc_enum);
  1179. static const struct snd_kcontrol_new adcr_mux =
  1180. SOC_DAPM_ENUM("ADCR Mux", adc_enum);
  1181. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  1182. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
  1183. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
  1184. SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
  1185. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
  1186. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
  1187. };
  1188. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  1189. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
  1190. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
  1191. SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
  1192. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
  1193. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
  1194. };
  1195. /* Debugging; dump chip status after DAPM transitions */
  1196. static int post_ev(struct snd_soc_dapm_widget *w,
  1197. struct snd_kcontrol *kcontrol, int event)
  1198. {
  1199. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1200. dev_dbg(component->dev, "SRC status: %x\n",
  1201. snd_soc_component_read(component,
  1202. WM8994_RATE_STATUS));
  1203. return 0;
  1204. }
  1205. static const struct snd_kcontrol_new aif1adc1l_mix[] = {
  1206. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  1207. 1, 1, 0),
  1208. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  1209. 0, 1, 0),
  1210. };
  1211. static const struct snd_kcontrol_new aif1adc1r_mix[] = {
  1212. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  1213. 1, 1, 0),
  1214. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  1215. 0, 1, 0),
  1216. };
  1217. static const struct snd_kcontrol_new aif1adc2l_mix[] = {
  1218. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  1219. 1, 1, 0),
  1220. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  1221. 0, 1, 0),
  1222. };
  1223. static const struct snd_kcontrol_new aif1adc2r_mix[] = {
  1224. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  1225. 1, 1, 0),
  1226. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  1227. 0, 1, 0),
  1228. };
  1229. static const struct snd_kcontrol_new aif2dac2l_mix[] = {
  1230. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1231. 5, 1, 0),
  1232. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1233. 4, 1, 0),
  1234. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1235. 2, 1, 0),
  1236. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1237. 1, 1, 0),
  1238. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  1239. 0, 1, 0),
  1240. };
  1241. static const struct snd_kcontrol_new aif2dac2r_mix[] = {
  1242. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1243. 5, 1, 0),
  1244. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1245. 4, 1, 0),
  1246. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1247. 2, 1, 0),
  1248. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1249. 1, 1, 0),
  1250. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  1251. 0, 1, 0),
  1252. };
  1253. #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
  1254. SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
  1255. snd_soc_dapm_get_volsw, wm8994_put_class_w)
  1256. static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
  1257. struct snd_ctl_elem_value *ucontrol)
  1258. {
  1259. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  1260. int ret;
  1261. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  1262. wm_hubs_update_class_w(component);
  1263. return ret;
  1264. }
  1265. static const struct snd_kcontrol_new dac1l_mix[] = {
  1266. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1267. 5, 1, 0),
  1268. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1269. 4, 1, 0),
  1270. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1271. 2, 1, 0),
  1272. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1273. 1, 1, 0),
  1274. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  1275. 0, 1, 0),
  1276. };
  1277. static const struct snd_kcontrol_new dac1r_mix[] = {
  1278. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1279. 5, 1, 0),
  1280. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1281. 4, 1, 0),
  1282. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1283. 2, 1, 0),
  1284. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1285. 1, 1, 0),
  1286. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  1287. 0, 1, 0),
  1288. };
  1289. static const char *sidetone_text[] = {
  1290. "ADC/DMIC1", "DMIC2",
  1291. };
  1292. static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
  1293. WM8994_SIDETONE, 0, sidetone_text);
  1294. static const struct snd_kcontrol_new sidetone1_mux =
  1295. SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
  1296. static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
  1297. WM8994_SIDETONE, 1, sidetone_text);
  1298. static const struct snd_kcontrol_new sidetone2_mux =
  1299. SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
  1300. static const char *aif1dac_text[] = {
  1301. "AIF1DACDAT", "AIF3DACDAT",
  1302. };
  1303. static const char *loopback_text[] = {
  1304. "None", "ADCDAT",
  1305. };
  1306. static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
  1307. WM8994_AIF1_CONTROL_2,
  1308. WM8994_AIF1_LOOPBACK_SHIFT,
  1309. loopback_text);
  1310. static const struct snd_kcontrol_new aif1_loopback =
  1311. SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
  1312. static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
  1313. WM8994_AIF2_CONTROL_2,
  1314. WM8994_AIF2_LOOPBACK_SHIFT,
  1315. loopback_text);
  1316. static const struct snd_kcontrol_new aif2_loopback =
  1317. SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
  1318. static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
  1319. WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
  1320. static const struct snd_kcontrol_new aif1dac_mux =
  1321. SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
  1322. static const char *aif2dac_text[] = {
  1323. "AIF2DACDAT", "AIF3DACDAT",
  1324. };
  1325. static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
  1326. WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
  1327. static const struct snd_kcontrol_new aif2dac_mux =
  1328. SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
  1329. static const char *aif2adc_text[] = {
  1330. "AIF2ADCDAT", "AIF3DACDAT",
  1331. };
  1332. static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
  1333. WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
  1334. static const struct snd_kcontrol_new aif2adc_mux =
  1335. SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
  1336. static const char *aif3adc_text[] = {
  1337. "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
  1338. };
  1339. static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
  1340. WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
  1341. static const struct snd_kcontrol_new wm8994_aif3adc_mux =
  1342. SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
  1343. static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
  1344. WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
  1345. static const struct snd_kcontrol_new wm8958_aif3adc_mux =
  1346. SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
  1347. static const char *mono_pcm_out_text[] = {
  1348. "None", "AIF2ADCL", "AIF2ADCR",
  1349. };
  1350. static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
  1351. WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
  1352. static const struct snd_kcontrol_new mono_pcm_out_mux =
  1353. SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
  1354. static const char *aif2dac_src_text[] = {
  1355. "AIF2", "AIF3",
  1356. };
  1357. /* Note that these two control shouldn't be simultaneously switched to AIF3 */
  1358. static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
  1359. WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
  1360. static const struct snd_kcontrol_new aif2dacl_src_mux =
  1361. SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
  1362. static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
  1363. WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
  1364. static const struct snd_kcontrol_new aif2dacr_src_mux =
  1365. SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
  1366. static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
  1367. SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
  1368. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1369. SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
  1370. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1371. SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1372. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1373. SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1374. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1375. SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1376. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1377. SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  1378. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1379. SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
  1380. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1381. SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
  1382. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
  1383. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1384. SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
  1385. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
  1386. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1387. SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
  1388. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1389. SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
  1390. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  1391. SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
  1392. };
  1393. static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
  1394. SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
  1395. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1396. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1397. SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
  1398. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1399. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1400. SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
  1401. SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
  1402. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  1403. SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
  1404. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  1405. SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
  1406. SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
  1407. };
  1408. static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
  1409. SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
  1410. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1411. SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
  1412. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1413. SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
  1414. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1415. SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
  1416. dac_ev, SND_SOC_DAPM_PRE_PMU),
  1417. };
  1418. static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
  1419. SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
  1420. SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
  1421. SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
  1422. SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
  1423. };
  1424. static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
  1425. SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
  1426. adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
  1427. SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
  1428. adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
  1429. };
  1430. static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
  1431. SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
  1432. SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
  1433. };
  1434. static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
  1435. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  1436. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  1437. SND_SOC_DAPM_INPUT("Clock"),
  1438. SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
  1439. SND_SOC_DAPM_PRE_PMU),
  1440. SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
  1441. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  1442. SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
  1443. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1444. SND_SOC_DAPM_PRE_PMD),
  1445. SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
  1446. SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
  1447. SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
  1448. SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
  1449. 0, SND_SOC_NOPM, 9, 0),
  1450. SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
  1451. 0, SND_SOC_NOPM, 8, 0),
  1452. SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
  1453. SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
  1454. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1455. SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
  1456. SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
  1457. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1458. SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
  1459. 0, SND_SOC_NOPM, 11, 0),
  1460. SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
  1461. 0, SND_SOC_NOPM, 10, 0),
  1462. SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
  1463. SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
  1464. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1465. SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
  1466. SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
  1467. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1468. SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
  1469. aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
  1470. SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
  1471. aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
  1472. SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
  1473. aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
  1474. SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
  1475. aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
  1476. SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
  1477. aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
  1478. SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
  1479. aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
  1480. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
  1481. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
  1482. SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
  1483. dac1l_mix, ARRAY_SIZE(dac1l_mix)),
  1484. SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
  1485. dac1r_mix, ARRAY_SIZE(dac1r_mix)),
  1486. SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
  1487. SND_SOC_NOPM, 13, 0),
  1488. SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
  1489. SND_SOC_NOPM, 12, 0),
  1490. SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
  1491. SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
  1492. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1493. SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
  1494. SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
  1495. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1496. SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1497. SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1498. SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1499. SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1500. SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
  1501. SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
  1502. SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
  1503. SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1504. SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
  1505. SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
  1506. SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
  1507. SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
  1508. SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
  1509. SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
  1510. /* Power is done with the muxes since the ADC power also controls the
  1511. * downsampling chain, the chip will automatically manage the analogue
  1512. * specific portions.
  1513. */
  1514. SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
  1515. SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
  1516. SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
  1517. SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
  1518. SND_SOC_DAPM_POST("Debug log", post_ev),
  1519. };
  1520. static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
  1521. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
  1522. };
  1523. static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
  1524. SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
  1525. SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
  1526. SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
  1527. SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
  1528. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
  1529. };
  1530. static const struct snd_soc_dapm_route intercon[] = {
  1531. { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
  1532. { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
  1533. { "DSP1CLK", NULL, "CLK_SYS" },
  1534. { "DSP2CLK", NULL, "CLK_SYS" },
  1535. { "DSPINTCLK", NULL, "CLK_SYS" },
  1536. { "AIF1ADC1L", NULL, "AIF1CLK" },
  1537. { "AIF1ADC1L", NULL, "DSP1CLK" },
  1538. { "AIF1ADC1R", NULL, "AIF1CLK" },
  1539. { "AIF1ADC1R", NULL, "DSP1CLK" },
  1540. { "AIF1ADC1R", NULL, "DSPINTCLK" },
  1541. { "AIF1DAC1L", NULL, "AIF1CLK" },
  1542. { "AIF1DAC1L", NULL, "DSP1CLK" },
  1543. { "AIF1DAC1R", NULL, "AIF1CLK" },
  1544. { "AIF1DAC1R", NULL, "DSP1CLK" },
  1545. { "AIF1DAC1R", NULL, "DSPINTCLK" },
  1546. { "AIF1ADC2L", NULL, "AIF1CLK" },
  1547. { "AIF1ADC2L", NULL, "DSP1CLK" },
  1548. { "AIF1ADC2R", NULL, "AIF1CLK" },
  1549. { "AIF1ADC2R", NULL, "DSP1CLK" },
  1550. { "AIF1ADC2R", NULL, "DSPINTCLK" },
  1551. { "AIF1DAC2L", NULL, "AIF1CLK" },
  1552. { "AIF1DAC2L", NULL, "DSP1CLK" },
  1553. { "AIF1DAC2R", NULL, "AIF1CLK" },
  1554. { "AIF1DAC2R", NULL, "DSP1CLK" },
  1555. { "AIF1DAC2R", NULL, "DSPINTCLK" },
  1556. { "AIF2ADCL", NULL, "AIF2CLK" },
  1557. { "AIF2ADCL", NULL, "DSP2CLK" },
  1558. { "AIF2ADCR", NULL, "AIF2CLK" },
  1559. { "AIF2ADCR", NULL, "DSP2CLK" },
  1560. { "AIF2ADCR", NULL, "DSPINTCLK" },
  1561. { "AIF2DACL", NULL, "AIF2CLK" },
  1562. { "AIF2DACL", NULL, "DSP2CLK" },
  1563. { "AIF2DACR", NULL, "AIF2CLK" },
  1564. { "AIF2DACR", NULL, "DSP2CLK" },
  1565. { "AIF2DACR", NULL, "DSPINTCLK" },
  1566. { "DMIC1L", NULL, "DMIC1DAT" },
  1567. { "DMIC1L", NULL, "CLK_SYS" },
  1568. { "DMIC1R", NULL, "DMIC1DAT" },
  1569. { "DMIC1R", NULL, "CLK_SYS" },
  1570. { "DMIC2L", NULL, "DMIC2DAT" },
  1571. { "DMIC2L", NULL, "CLK_SYS" },
  1572. { "DMIC2R", NULL, "DMIC2DAT" },
  1573. { "DMIC2R", NULL, "CLK_SYS" },
  1574. { "ADCL", NULL, "AIF1CLK" },
  1575. { "ADCL", NULL, "DSP1CLK" },
  1576. { "ADCL", NULL, "DSPINTCLK" },
  1577. { "ADCR", NULL, "AIF1CLK" },
  1578. { "ADCR", NULL, "DSP1CLK" },
  1579. { "ADCR", NULL, "DSPINTCLK" },
  1580. { "ADCL Mux", "ADC", "ADCL" },
  1581. { "ADCL Mux", "DMIC", "DMIC1L" },
  1582. { "ADCR Mux", "ADC", "ADCR" },
  1583. { "ADCR Mux", "DMIC", "DMIC1R" },
  1584. { "DAC1L", NULL, "AIF1CLK" },
  1585. { "DAC1L", NULL, "DSP1CLK" },
  1586. { "DAC1L", NULL, "DSPINTCLK" },
  1587. { "DAC1R", NULL, "AIF1CLK" },
  1588. { "DAC1R", NULL, "DSP1CLK" },
  1589. { "DAC1R", NULL, "DSPINTCLK" },
  1590. { "DAC2L", NULL, "AIF2CLK" },
  1591. { "DAC2L", NULL, "DSP2CLK" },
  1592. { "DAC2L", NULL, "DSPINTCLK" },
  1593. { "DAC2R", NULL, "AIF2DACR" },
  1594. { "DAC2R", NULL, "AIF2CLK" },
  1595. { "DAC2R", NULL, "DSP2CLK" },
  1596. { "DAC2R", NULL, "DSPINTCLK" },
  1597. { "TOCLK", NULL, "CLK_SYS" },
  1598. { "AIF1DACDAT", NULL, "AIF1 Playback" },
  1599. { "AIF2DACDAT", NULL, "AIF2 Playback" },
  1600. { "AIF3DACDAT", NULL, "AIF3 Playback" },
  1601. { "AIF1 Capture", NULL, "AIF1ADCDAT" },
  1602. { "AIF2 Capture", NULL, "AIF2ADCDAT" },
  1603. { "AIF3 Capture", NULL, "AIF3ADCDAT" },
  1604. /* AIF1 outputs */
  1605. { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
  1606. { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
  1607. { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  1608. { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
  1609. { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
  1610. { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  1611. { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
  1612. { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
  1613. { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  1614. { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
  1615. { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
  1616. { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  1617. /* Pin level routing for AIF3 */
  1618. { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
  1619. { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
  1620. { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
  1621. { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
  1622. { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
  1623. { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  1624. { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
  1625. { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  1626. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
  1627. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
  1628. { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
  1629. /* DAC1 inputs */
  1630. { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  1631. { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  1632. { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  1633. { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1634. { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1635. { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  1636. { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  1637. { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  1638. { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1639. { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1640. /* DAC2/AIF2 outputs */
  1641. { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
  1642. { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  1643. { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  1644. { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  1645. { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1646. { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1647. { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
  1648. { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  1649. { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  1650. { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  1651. { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1652. { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1653. { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
  1654. { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
  1655. { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
  1656. { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
  1657. { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
  1658. /* AIF3 output */
  1659. { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
  1660. { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
  1661. { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
  1662. { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
  1663. { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
  1664. { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
  1665. { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
  1666. { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
  1667. { "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
  1668. /* Loopback */
  1669. { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
  1670. { "AIF1 Loopback", "None", "AIF1DACDAT" },
  1671. { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
  1672. { "AIF2 Loopback", "None", "AIF2DACDAT" },
  1673. /* Sidetone */
  1674. { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
  1675. { "Left Sidetone", "DMIC2", "DMIC2L" },
  1676. { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
  1677. { "Right Sidetone", "DMIC2", "DMIC2R" },
  1678. /* Output stages */
  1679. { "Left Output Mixer", "DAC Switch", "DAC1L" },
  1680. { "Right Output Mixer", "DAC Switch", "DAC1R" },
  1681. { "SPKL", "DAC1 Switch", "DAC1L" },
  1682. { "SPKL", "DAC2 Switch", "DAC2L" },
  1683. { "SPKR", "DAC1 Switch", "DAC1R" },
  1684. { "SPKR", "DAC2 Switch", "DAC2R" },
  1685. { "Left Headphone Mux", "DAC", "DAC1L" },
  1686. { "Right Headphone Mux", "DAC", "DAC1R" },
  1687. };
  1688. static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
  1689. { "DAC1L", NULL, "Late DAC1L Enable PGA" },
  1690. { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
  1691. { "DAC1R", NULL, "Late DAC1R Enable PGA" },
  1692. { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
  1693. { "DAC2L", NULL, "Late DAC2L Enable PGA" },
  1694. { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
  1695. { "DAC2R", NULL, "Late DAC2R Enable PGA" },
  1696. { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
  1697. };
  1698. static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
  1699. { "DAC1L", NULL, "DAC1L Mixer" },
  1700. { "DAC1R", NULL, "DAC1R Mixer" },
  1701. { "DAC2L", NULL, "AIF2DAC2L Mixer" },
  1702. { "DAC2R", NULL, "AIF2DAC2R Mixer" },
  1703. };
  1704. static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
  1705. { "AIF1DACDAT", NULL, "AIF2DACDAT" },
  1706. { "AIF2DACDAT", NULL, "AIF1DACDAT" },
  1707. { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
  1708. { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
  1709. { "MICBIAS1", NULL, "CLK_SYS" },
  1710. { "MICBIAS1", NULL, "MICBIAS Supply" },
  1711. { "MICBIAS2", NULL, "CLK_SYS" },
  1712. { "MICBIAS2", NULL, "MICBIAS Supply" },
  1713. };
  1714. static const struct snd_soc_dapm_route wm8994_intercon[] = {
  1715. { "AIF2DACL", NULL, "AIF2DAC Mux" },
  1716. { "AIF2DACR", NULL, "AIF2DAC Mux" },
  1717. { "MICBIAS1", NULL, "VMID" },
  1718. { "MICBIAS2", NULL, "VMID" },
  1719. };
  1720. static const struct snd_soc_dapm_route wm8958_intercon[] = {
  1721. { "AIF2DACL", NULL, "AIF2DACL Mux" },
  1722. { "AIF2DACR", NULL, "AIF2DACR Mux" },
  1723. { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
  1724. { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
  1725. { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
  1726. { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
  1727. { "AIF3DACDAT", NULL, "AIF3" },
  1728. { "AIF3ADCDAT", NULL, "AIF3" },
  1729. { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
  1730. { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
  1731. { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
  1732. };
  1733. /* The size in bits of the FLL divide multiplied by 10
  1734. * to allow rounding later */
  1735. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1736. struct fll_div {
  1737. u16 outdiv;
  1738. u16 n;
  1739. u16 k;
  1740. u16 lambda;
  1741. u16 clk_ref_div;
  1742. u16 fll_fratio;
  1743. };
  1744. static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
  1745. int freq_in, int freq_out)
  1746. {
  1747. u64 Kpart;
  1748. unsigned int K, Ndiv, Nmod, gcd_fll;
  1749. pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
  1750. /* Scale the input frequency down to <= 13.5MHz */
  1751. fll->clk_ref_div = 0;
  1752. while (freq_in > 13500000) {
  1753. fll->clk_ref_div++;
  1754. freq_in /= 2;
  1755. if (fll->clk_ref_div > 3)
  1756. return -EINVAL;
  1757. }
  1758. pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
  1759. /* Scale the output to give 90MHz<=Fvco<=100MHz */
  1760. fll->outdiv = 3;
  1761. while (freq_out * (fll->outdiv + 1) < 90000000) {
  1762. fll->outdiv++;
  1763. if (fll->outdiv > 63)
  1764. return -EINVAL;
  1765. }
  1766. freq_out *= fll->outdiv + 1;
  1767. pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
  1768. if (freq_in > 1000000) {
  1769. fll->fll_fratio = 0;
  1770. } else if (freq_in > 256000) {
  1771. fll->fll_fratio = 1;
  1772. freq_in *= 2;
  1773. } else if (freq_in > 128000) {
  1774. fll->fll_fratio = 2;
  1775. freq_in *= 4;
  1776. } else if (freq_in > 64000) {
  1777. fll->fll_fratio = 3;
  1778. freq_in *= 8;
  1779. } else {
  1780. fll->fll_fratio = 4;
  1781. freq_in *= 16;
  1782. }
  1783. pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
  1784. /* Now, calculate N.K */
  1785. Ndiv = freq_out / freq_in;
  1786. fll->n = Ndiv;
  1787. Nmod = freq_out % freq_in;
  1788. pr_debug("Nmod=%d\n", Nmod);
  1789. switch (control->type) {
  1790. case WM8994:
  1791. /* Calculate fractional part - scale up so we can round. */
  1792. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1793. do_div(Kpart, freq_in);
  1794. K = Kpart & 0xFFFFFFFF;
  1795. if ((K % 10) >= 5)
  1796. K += 5;
  1797. /* Move down to proper range now rounding is done */
  1798. fll->k = K / 10;
  1799. fll->lambda = 0;
  1800. pr_debug("N=%x K=%x\n", fll->n, fll->k);
  1801. break;
  1802. default:
  1803. gcd_fll = gcd(freq_out, freq_in);
  1804. fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
  1805. fll->lambda = freq_in / gcd_fll;
  1806. }
  1807. return 0;
  1808. }
  1809. static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
  1810. unsigned int freq_in, unsigned int freq_out)
  1811. {
  1812. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  1813. struct wm8994 *control = wm8994->wm8994;
  1814. int reg_offset, ret;
  1815. struct fll_div fll;
  1816. u16 reg, clk1, aif_reg, aif_src;
  1817. unsigned long timeout;
  1818. bool was_enabled;
  1819. struct clk *mclk;
  1820. switch (id) {
  1821. case WM8994_FLL1:
  1822. reg_offset = 0;
  1823. id = 0;
  1824. aif_src = 0x10;
  1825. break;
  1826. case WM8994_FLL2:
  1827. reg_offset = 0x20;
  1828. id = 1;
  1829. aif_src = 0x18;
  1830. break;
  1831. default:
  1832. return -EINVAL;
  1833. }
  1834. reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset);
  1835. was_enabled = reg & WM8994_FLL1_ENA;
  1836. switch (src) {
  1837. case 0:
  1838. /* Allow no source specification when stopping */
  1839. if (freq_out)
  1840. return -EINVAL;
  1841. src = wm8994->fll[id].src;
  1842. break;
  1843. case WM8994_FLL_SRC_MCLK1:
  1844. case WM8994_FLL_SRC_MCLK2:
  1845. case WM8994_FLL_SRC_LRCLK:
  1846. case WM8994_FLL_SRC_BCLK:
  1847. break;
  1848. case WM8994_FLL_SRC_INTERNAL:
  1849. freq_in = 12000000;
  1850. freq_out = 12000000;
  1851. break;
  1852. default:
  1853. return -EINVAL;
  1854. }
  1855. /* Are we changing anything? */
  1856. if (wm8994->fll[id].src == src &&
  1857. wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
  1858. return 0;
  1859. /* If we're stopping the FLL redo the old config - no
  1860. * registers will actually be written but we avoid GCC flow
  1861. * analysis bugs spewing warnings.
  1862. */
  1863. if (freq_out)
  1864. ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
  1865. else
  1866. ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
  1867. wm8994->fll[id].out);
  1868. if (ret < 0)
  1869. return ret;
  1870. /* Make sure that we're not providing SYSCLK right now */
  1871. clk1 = snd_soc_component_read(component, WM8994_CLOCKING_1);
  1872. if (clk1 & WM8994_SYSCLK_SRC)
  1873. aif_reg = WM8994_AIF2_CLOCKING_1;
  1874. else
  1875. aif_reg = WM8994_AIF1_CLOCKING_1;
  1876. reg = snd_soc_component_read(component, aif_reg);
  1877. if ((reg & WM8994_AIF1CLK_ENA) &&
  1878. (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
  1879. dev_err(component->dev, "FLL%d is currently providing SYSCLK\n",
  1880. id + 1);
  1881. return -EBUSY;
  1882. }
  1883. /* We always need to disable the FLL while reconfiguring */
  1884. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
  1885. WM8994_FLL1_ENA, 0);
  1886. /* Disable MCLK if needed before we possibly change to new clock parent */
  1887. if (was_enabled) {
  1888. reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_5
  1889. + reg_offset);
  1890. reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK)
  1891. >> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1;
  1892. switch (reg) {
  1893. case WM8994_FLL_SRC_MCLK1:
  1894. mclk = wm8994->mclk[WM8994_MCLK1].clk;
  1895. break;
  1896. case WM8994_FLL_SRC_MCLK2:
  1897. mclk = wm8994->mclk[WM8994_MCLK2].clk;
  1898. break;
  1899. default:
  1900. mclk = NULL;
  1901. }
  1902. clk_disable_unprepare(mclk);
  1903. }
  1904. if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
  1905. freq_in == freq_out && freq_out) {
  1906. dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1);
  1907. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
  1908. WM8958_FLL1_BYP, WM8958_FLL1_BYP);
  1909. goto out;
  1910. }
  1911. reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
  1912. (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
  1913. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
  1914. WM8994_FLL1_OUTDIV_MASK |
  1915. WM8994_FLL1_FRATIO_MASK, reg);
  1916. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
  1917. WM8994_FLL1_K_MASK, fll.k);
  1918. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
  1919. WM8994_FLL1_N_MASK,
  1920. fll.n << WM8994_FLL1_N_SHIFT);
  1921. if (fll.lambda) {
  1922. snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,
  1923. WM8958_FLL1_LAMBDA_MASK,
  1924. fll.lambda);
  1925. snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
  1926. WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
  1927. } else {
  1928. snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
  1929. WM8958_FLL1_EFS_ENA, 0);
  1930. }
  1931. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
  1932. WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
  1933. WM8994_FLL1_REFCLK_DIV_MASK |
  1934. WM8994_FLL1_REFCLK_SRC_MASK,
  1935. ((src == WM8994_FLL_SRC_INTERNAL)
  1936. << WM8994_FLL1_FRC_NCO_SHIFT) |
  1937. (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
  1938. (src - 1));
  1939. /* Clear any pending completion from a previous failure */
  1940. try_wait_for_completion(&wm8994->fll_locked[id]);
  1941. switch (src) {
  1942. case WM8994_FLL_SRC_MCLK1:
  1943. mclk = wm8994->mclk[WM8994_MCLK1].clk;
  1944. break;
  1945. case WM8994_FLL_SRC_MCLK2:
  1946. mclk = wm8994->mclk[WM8994_MCLK2].clk;
  1947. break;
  1948. default:
  1949. mclk = NULL;
  1950. }
  1951. /* Enable (with fractional mode if required) */
  1952. if (freq_out) {
  1953. ret = clk_prepare_enable(mclk);
  1954. if (ret < 0) {
  1955. dev_err(component->dev, "Failed to enable MCLK for FLL%d\n",
  1956. id + 1);
  1957. return ret;
  1958. }
  1959. /* Enable VMID if we need it */
  1960. if (!was_enabled) {
  1961. active_reference(component);
  1962. switch (control->type) {
  1963. case WM8994:
  1964. vmid_reference(component);
  1965. break;
  1966. case WM8958:
  1967. if (control->revision < 1)
  1968. vmid_reference(component);
  1969. break;
  1970. default:
  1971. break;
  1972. }
  1973. }
  1974. reg = WM8994_FLL1_ENA;
  1975. if (fll.k)
  1976. reg |= WM8994_FLL1_FRAC;
  1977. if (src == WM8994_FLL_SRC_INTERNAL)
  1978. reg |= WM8994_FLL1_OSC_ENA;
  1979. snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
  1980. WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
  1981. WM8994_FLL1_FRAC, reg);
  1982. if (wm8994->fll_locked_irq) {
  1983. timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
  1984. msecs_to_jiffies(10));
  1985. if (timeout == 0)
  1986. dev_warn(component->dev,
  1987. "Timed out waiting for FLL lock\n");
  1988. } else {
  1989. msleep(5);
  1990. }
  1991. } else {
  1992. if (was_enabled) {
  1993. switch (control->type) {
  1994. case WM8994:
  1995. vmid_dereference(component);
  1996. break;
  1997. case WM8958:
  1998. if (control->revision < 1)
  1999. vmid_dereference(component);
  2000. break;
  2001. default:
  2002. break;
  2003. }
  2004. active_dereference(component);
  2005. }
  2006. }
  2007. out:
  2008. wm8994->fll[id].in = freq_in;
  2009. wm8994->fll[id].out = freq_out;
  2010. wm8994->fll[id].src = src;
  2011. configure_clock(component);
  2012. /*
  2013. * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
  2014. * for detection.
  2015. */
  2016. if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
  2017. dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
  2018. wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
  2019. & WM8994_AIF1CLK_RATE_MASK;
  2020. wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
  2021. & WM8994_AIF1CLK_RATE_MASK;
  2022. snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
  2023. WM8994_AIF1CLK_RATE_MASK, 0x1);
  2024. snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
  2025. WM8994_AIF2CLK_RATE_MASK, 0x1);
  2026. } else if (wm8994->aifdiv[0]) {
  2027. snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
  2028. WM8994_AIF1CLK_RATE_MASK,
  2029. wm8994->aifdiv[0]);
  2030. snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
  2031. WM8994_AIF2CLK_RATE_MASK,
  2032. wm8994->aifdiv[1]);
  2033. wm8994->aifdiv[0] = 0;
  2034. wm8994->aifdiv[1] = 0;
  2035. }
  2036. return 0;
  2037. }
  2038. static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
  2039. {
  2040. struct completion *completion = data;
  2041. complete(completion);
  2042. return IRQ_HANDLED;
  2043. }
  2044. static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  2045. static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
  2046. unsigned int freq_in, unsigned int freq_out)
  2047. {
  2048. return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
  2049. }
  2050. static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id,
  2051. unsigned int *freq)
  2052. {
  2053. int ret;
  2054. if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id])
  2055. return 0;
  2056. ret = clk_set_rate(wm8994->mclk[id].clk, *freq);
  2057. if (ret < 0)
  2058. return ret;
  2059. *freq = clk_get_rate(wm8994->mclk[id].clk);
  2060. return 0;
  2061. }
  2062. static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
  2063. int clk_id, unsigned int freq, int dir)
  2064. {
  2065. struct snd_soc_component *component = dai->component;
  2066. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2067. int ret, i;
  2068. switch (dai->id) {
  2069. case 1:
  2070. case 2:
  2071. break;
  2072. default:
  2073. /* AIF3 shares clocking with AIF1/2 */
  2074. return -EINVAL;
  2075. }
  2076. switch (clk_id) {
  2077. case WM8994_SYSCLK_MCLK1:
  2078. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
  2079. ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
  2080. if (ret < 0)
  2081. return ret;
  2082. wm8994->mclk_rate[0] = freq;
  2083. dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
  2084. dai->id, freq);
  2085. break;
  2086. case WM8994_SYSCLK_MCLK2:
  2087. /* TODO: Set GPIO AF */
  2088. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
  2089. ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
  2090. if (ret < 0)
  2091. return ret;
  2092. wm8994->mclk_rate[1] = freq;
  2093. dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
  2094. dai->id, freq);
  2095. break;
  2096. case WM8994_SYSCLK_FLL1:
  2097. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
  2098. dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
  2099. break;
  2100. case WM8994_SYSCLK_FLL2:
  2101. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
  2102. dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
  2103. break;
  2104. case WM8994_SYSCLK_OPCLK:
  2105. /* Special case - a division (times 10) is given and
  2106. * no effect on main clocking.
  2107. */
  2108. if (freq) {
  2109. for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
  2110. if (opclk_divs[i] == freq)
  2111. break;
  2112. if (i == ARRAY_SIZE(opclk_divs))
  2113. return -EINVAL;
  2114. snd_soc_component_update_bits(component, WM8994_CLOCKING_2,
  2115. WM8994_OPCLK_DIV_MASK, i);
  2116. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
  2117. WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
  2118. } else {
  2119. snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
  2120. WM8994_OPCLK_ENA, 0);
  2121. }
  2122. break;
  2123. default:
  2124. return -EINVAL;
  2125. }
  2126. configure_clock(component);
  2127. /*
  2128. * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
  2129. * for detection.
  2130. */
  2131. if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
  2132. dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
  2133. wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
  2134. & WM8994_AIF1CLK_RATE_MASK;
  2135. wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
  2136. & WM8994_AIF1CLK_RATE_MASK;
  2137. snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
  2138. WM8994_AIF1CLK_RATE_MASK, 0x1);
  2139. snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
  2140. WM8994_AIF2CLK_RATE_MASK, 0x1);
  2141. } else if (wm8994->aifdiv[0]) {
  2142. snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
  2143. WM8994_AIF1CLK_RATE_MASK,
  2144. wm8994->aifdiv[0]);
  2145. snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
  2146. WM8994_AIF2CLK_RATE_MASK,
  2147. wm8994->aifdiv[1]);
  2148. wm8994->aifdiv[0] = 0;
  2149. wm8994->aifdiv[1] = 0;
  2150. }
  2151. return 0;
  2152. }
  2153. static int wm8994_set_bias_level(struct snd_soc_component *component,
  2154. enum snd_soc_bias_level level)
  2155. {
  2156. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2157. struct wm8994 *control = wm8994->wm8994;
  2158. wm_hubs_set_bias_level(component, level);
  2159. switch (level) {
  2160. case SND_SOC_BIAS_ON:
  2161. break;
  2162. case SND_SOC_BIAS_PREPARE:
  2163. /* MICBIAS into regulating mode */
  2164. switch (control->type) {
  2165. case WM8958:
  2166. case WM1811:
  2167. snd_soc_component_update_bits(component, WM8958_MICBIAS1,
  2168. WM8958_MICB1_MODE, 0);
  2169. snd_soc_component_update_bits(component, WM8958_MICBIAS2,
  2170. WM8958_MICB2_MODE, 0);
  2171. break;
  2172. default:
  2173. break;
  2174. }
  2175. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
  2176. active_reference(component);
  2177. break;
  2178. case SND_SOC_BIAS_STANDBY:
  2179. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  2180. switch (control->type) {
  2181. case WM8958:
  2182. if (control->revision == 0) {
  2183. /* Optimise performance for rev A */
  2184. snd_soc_component_update_bits(component,
  2185. WM8958_CHARGE_PUMP_2,
  2186. WM8958_CP_DISCH,
  2187. WM8958_CP_DISCH);
  2188. }
  2189. break;
  2190. default:
  2191. break;
  2192. }
  2193. /* Discharge LINEOUT1 & 2 */
  2194. snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
  2195. WM8994_LINEOUT1_DISCH |
  2196. WM8994_LINEOUT2_DISCH,
  2197. WM8994_LINEOUT1_DISCH |
  2198. WM8994_LINEOUT2_DISCH);
  2199. }
  2200. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
  2201. active_dereference(component);
  2202. /* MICBIAS into bypass mode on newer devices */
  2203. switch (control->type) {
  2204. case WM8958:
  2205. case WM1811:
  2206. snd_soc_component_update_bits(component, WM8958_MICBIAS1,
  2207. WM8958_MICB1_MODE,
  2208. WM8958_MICB1_MODE);
  2209. snd_soc_component_update_bits(component, WM8958_MICBIAS2,
  2210. WM8958_MICB2_MODE,
  2211. WM8958_MICB2_MODE);
  2212. break;
  2213. default:
  2214. break;
  2215. }
  2216. break;
  2217. case SND_SOC_BIAS_OFF:
  2218. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
  2219. wm8994->cur_fw = NULL;
  2220. break;
  2221. }
  2222. return 0;
  2223. }
  2224. int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode)
  2225. {
  2226. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2227. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2228. switch (mode) {
  2229. case WM8994_VMID_NORMAL:
  2230. snd_soc_dapm_mutex_lock(dapm);
  2231. if (wm8994->hubs.lineout1_se) {
  2232. snd_soc_dapm_disable_pin_unlocked(dapm,
  2233. "LINEOUT1N Driver");
  2234. snd_soc_dapm_disable_pin_unlocked(dapm,
  2235. "LINEOUT1P Driver");
  2236. }
  2237. if (wm8994->hubs.lineout2_se) {
  2238. snd_soc_dapm_disable_pin_unlocked(dapm,
  2239. "LINEOUT2N Driver");
  2240. snd_soc_dapm_disable_pin_unlocked(dapm,
  2241. "LINEOUT2P Driver");
  2242. }
  2243. /* Do the sync with the old mode to allow it to clean up */
  2244. snd_soc_dapm_sync_unlocked(dapm);
  2245. wm8994->vmid_mode = mode;
  2246. snd_soc_dapm_mutex_unlock(dapm);
  2247. break;
  2248. case WM8994_VMID_FORCE:
  2249. snd_soc_dapm_mutex_lock(dapm);
  2250. if (wm8994->hubs.lineout1_se) {
  2251. snd_soc_dapm_force_enable_pin_unlocked(dapm,
  2252. "LINEOUT1N Driver");
  2253. snd_soc_dapm_force_enable_pin_unlocked(dapm,
  2254. "LINEOUT1P Driver");
  2255. }
  2256. if (wm8994->hubs.lineout2_se) {
  2257. snd_soc_dapm_force_enable_pin_unlocked(dapm,
  2258. "LINEOUT2N Driver");
  2259. snd_soc_dapm_force_enable_pin_unlocked(dapm,
  2260. "LINEOUT2P Driver");
  2261. }
  2262. wm8994->vmid_mode = mode;
  2263. snd_soc_dapm_sync_unlocked(dapm);
  2264. snd_soc_dapm_mutex_unlock(dapm);
  2265. break;
  2266. default:
  2267. return -EINVAL;
  2268. }
  2269. return 0;
  2270. }
  2271. static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  2272. {
  2273. struct snd_soc_component *component = dai->component;
  2274. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2275. struct wm8994 *control = wm8994->wm8994;
  2276. int ms_reg;
  2277. int aif1_reg;
  2278. int dac_reg;
  2279. int adc_reg;
  2280. int ms = 0;
  2281. int aif1 = 0;
  2282. int lrclk = 0;
  2283. switch (dai->id) {
  2284. case 1:
  2285. ms_reg = WM8994_AIF1_MASTER_SLAVE;
  2286. aif1_reg = WM8994_AIF1_CONTROL_1;
  2287. dac_reg = WM8994_AIF1DAC_LRCLK;
  2288. adc_reg = WM8994_AIF1ADC_LRCLK;
  2289. break;
  2290. case 2:
  2291. ms_reg = WM8994_AIF2_MASTER_SLAVE;
  2292. aif1_reg = WM8994_AIF2_CONTROL_1;
  2293. dac_reg = WM8994_AIF1DAC_LRCLK;
  2294. adc_reg = WM8994_AIF1ADC_LRCLK;
  2295. break;
  2296. default:
  2297. return -EINVAL;
  2298. }
  2299. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  2300. case SND_SOC_DAIFMT_CBS_CFS:
  2301. break;
  2302. case SND_SOC_DAIFMT_CBM_CFM:
  2303. ms = WM8994_AIF1_MSTR;
  2304. break;
  2305. default:
  2306. return -EINVAL;
  2307. }
  2308. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2309. case SND_SOC_DAIFMT_DSP_B:
  2310. aif1 |= WM8994_AIF1_LRCLK_INV;
  2311. lrclk |= WM8958_AIF1_LRCLK_INV;
  2312. fallthrough;
  2313. case SND_SOC_DAIFMT_DSP_A:
  2314. aif1 |= 0x18;
  2315. break;
  2316. case SND_SOC_DAIFMT_I2S:
  2317. aif1 |= 0x10;
  2318. break;
  2319. case SND_SOC_DAIFMT_RIGHT_J:
  2320. break;
  2321. case SND_SOC_DAIFMT_LEFT_J:
  2322. aif1 |= 0x8;
  2323. break;
  2324. default:
  2325. return -EINVAL;
  2326. }
  2327. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  2328. case SND_SOC_DAIFMT_DSP_A:
  2329. case SND_SOC_DAIFMT_DSP_B:
  2330. /* frame inversion not valid for DSP modes */
  2331. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2332. case SND_SOC_DAIFMT_NB_NF:
  2333. break;
  2334. case SND_SOC_DAIFMT_IB_NF:
  2335. aif1 |= WM8994_AIF1_BCLK_INV;
  2336. break;
  2337. default:
  2338. return -EINVAL;
  2339. }
  2340. break;
  2341. case SND_SOC_DAIFMT_I2S:
  2342. case SND_SOC_DAIFMT_RIGHT_J:
  2343. case SND_SOC_DAIFMT_LEFT_J:
  2344. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  2345. case SND_SOC_DAIFMT_NB_NF:
  2346. break;
  2347. case SND_SOC_DAIFMT_IB_IF:
  2348. aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
  2349. lrclk |= WM8958_AIF1_LRCLK_INV;
  2350. break;
  2351. case SND_SOC_DAIFMT_IB_NF:
  2352. aif1 |= WM8994_AIF1_BCLK_INV;
  2353. break;
  2354. case SND_SOC_DAIFMT_NB_IF:
  2355. aif1 |= WM8994_AIF1_LRCLK_INV;
  2356. lrclk |= WM8958_AIF1_LRCLK_INV;
  2357. break;
  2358. default:
  2359. return -EINVAL;
  2360. }
  2361. break;
  2362. default:
  2363. return -EINVAL;
  2364. }
  2365. /* The AIF2 format configuration needs to be mirrored to AIF3
  2366. * on WM8958 if it's in use so just do it all the time. */
  2367. switch (control->type) {
  2368. case WM1811:
  2369. case WM8958:
  2370. if (dai->id == 2)
  2371. snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1,
  2372. WM8994_AIF1_LRCLK_INV |
  2373. WM8958_AIF3_FMT_MASK, aif1);
  2374. break;
  2375. default:
  2376. break;
  2377. }
  2378. snd_soc_component_update_bits(component, aif1_reg,
  2379. WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
  2380. WM8994_AIF1_FMT_MASK,
  2381. aif1);
  2382. snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR,
  2383. ms);
  2384. snd_soc_component_update_bits(component, dac_reg,
  2385. WM8958_AIF1_LRCLK_INV, lrclk);
  2386. snd_soc_component_update_bits(component, adc_reg,
  2387. WM8958_AIF1_LRCLK_INV, lrclk);
  2388. return 0;
  2389. }
  2390. static struct {
  2391. int val, rate;
  2392. } srs[] = {
  2393. { 0, 8000 },
  2394. { 1, 11025 },
  2395. { 2, 12000 },
  2396. { 3, 16000 },
  2397. { 4, 22050 },
  2398. { 5, 24000 },
  2399. { 6, 32000 },
  2400. { 7, 44100 },
  2401. { 8, 48000 },
  2402. { 9, 88200 },
  2403. { 10, 96000 },
  2404. };
  2405. static int fs_ratios[] = {
  2406. 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
  2407. };
  2408. static int bclk_divs[] = {
  2409. 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  2410. 640, 880, 960, 1280, 1760, 1920
  2411. };
  2412. static int wm8994_hw_params(struct snd_pcm_substream *substream,
  2413. struct snd_pcm_hw_params *params,
  2414. struct snd_soc_dai *dai)
  2415. {
  2416. struct snd_soc_component *component = dai->component;
  2417. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2418. struct wm8994 *control = wm8994->wm8994;
  2419. struct wm8994_pdata *pdata = &control->pdata;
  2420. int aif1_reg;
  2421. int aif2_reg;
  2422. int bclk_reg;
  2423. int lrclk_reg;
  2424. int rate_reg;
  2425. int aif1 = 0;
  2426. int aif2 = 0;
  2427. int bclk = 0;
  2428. int lrclk = 0;
  2429. int rate_val = 0;
  2430. int id = dai->id - 1;
  2431. int i, cur_val, best_val, bclk_rate, best;
  2432. switch (dai->id) {
  2433. case 1:
  2434. aif1_reg = WM8994_AIF1_CONTROL_1;
  2435. aif2_reg = WM8994_AIF1_CONTROL_2;
  2436. bclk_reg = WM8994_AIF1_BCLK;
  2437. rate_reg = WM8994_AIF1_RATE;
  2438. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  2439. wm8994->lrclk_shared[0]) {
  2440. lrclk_reg = WM8994_AIF1DAC_LRCLK;
  2441. } else {
  2442. lrclk_reg = WM8994_AIF1ADC_LRCLK;
  2443. dev_dbg(component->dev, "AIF1 using split LRCLK\n");
  2444. }
  2445. break;
  2446. case 2:
  2447. aif1_reg = WM8994_AIF2_CONTROL_1;
  2448. aif2_reg = WM8994_AIF2_CONTROL_2;
  2449. bclk_reg = WM8994_AIF2_BCLK;
  2450. rate_reg = WM8994_AIF2_RATE;
  2451. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  2452. wm8994->lrclk_shared[1]) {
  2453. lrclk_reg = WM8994_AIF2DAC_LRCLK;
  2454. } else {
  2455. lrclk_reg = WM8994_AIF2ADC_LRCLK;
  2456. dev_dbg(component->dev, "AIF2 using split LRCLK\n");
  2457. }
  2458. break;
  2459. default:
  2460. return -EINVAL;
  2461. }
  2462. bclk_rate = params_rate(params);
  2463. switch (params_width(params)) {
  2464. case 16:
  2465. bclk_rate *= 16;
  2466. break;
  2467. case 20:
  2468. bclk_rate *= 20;
  2469. aif1 |= 0x20;
  2470. break;
  2471. case 24:
  2472. bclk_rate *= 24;
  2473. aif1 |= 0x40;
  2474. break;
  2475. case 32:
  2476. bclk_rate *= 32;
  2477. aif1 |= 0x60;
  2478. break;
  2479. default:
  2480. return -EINVAL;
  2481. }
  2482. wm8994->channels[id] = params_channels(params);
  2483. if (pdata->max_channels_clocked[id] &&
  2484. wm8994->channels[id] > pdata->max_channels_clocked[id]) {
  2485. dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
  2486. pdata->max_channels_clocked[id], wm8994->channels[id]);
  2487. wm8994->channels[id] = pdata->max_channels_clocked[id];
  2488. }
  2489. switch (wm8994->channels[id]) {
  2490. case 1:
  2491. case 2:
  2492. bclk_rate *= 2;
  2493. break;
  2494. default:
  2495. bclk_rate *= 4;
  2496. break;
  2497. }
  2498. /* Try to find an appropriate sample rate; look for an exact match. */
  2499. for (i = 0; i < ARRAY_SIZE(srs); i++)
  2500. if (srs[i].rate == params_rate(params))
  2501. break;
  2502. if (i == ARRAY_SIZE(srs))
  2503. return -EINVAL;
  2504. rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
  2505. dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
  2506. dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
  2507. dai->id, wm8994->aifclk[id], bclk_rate);
  2508. if (wm8994->channels[id] == 1 &&
  2509. (snd_soc_component_read(component, aif1_reg) & 0x18) == 0x18)
  2510. aif2 |= WM8994_AIF1_MONO;
  2511. if (wm8994->aifclk[id] == 0) {
  2512. dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
  2513. return -EINVAL;
  2514. }
  2515. /* AIFCLK/fs ratio; look for a close match in either direction */
  2516. best = 0;
  2517. best_val = abs((fs_ratios[0] * params_rate(params))
  2518. - wm8994->aifclk[id]);
  2519. for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
  2520. cur_val = abs((fs_ratios[i] * params_rate(params))
  2521. - wm8994->aifclk[id]);
  2522. if (cur_val >= best_val)
  2523. continue;
  2524. best = i;
  2525. best_val = cur_val;
  2526. }
  2527. dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
  2528. dai->id, fs_ratios[best]);
  2529. rate_val |= best;
  2530. /* We may not get quite the right frequency if using
  2531. * approximate clocks so look for the closest match that is
  2532. * higher than the target (we need to ensure that there enough
  2533. * BCLKs to clock out the samples).
  2534. */
  2535. best = 0;
  2536. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  2537. cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
  2538. if (cur_val < 0) /* BCLK table is sorted */
  2539. break;
  2540. best = i;
  2541. }
  2542. bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
  2543. dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
  2544. bclk_divs[best], bclk_rate);
  2545. bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
  2546. lrclk = bclk_rate / params_rate(params);
  2547. if (!lrclk) {
  2548. dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
  2549. bclk_rate);
  2550. return -EINVAL;
  2551. }
  2552. dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
  2553. lrclk, bclk_rate / lrclk);
  2554. snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  2555. snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2);
  2556. snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
  2557. snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
  2558. lrclk);
  2559. snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK |
  2560. WM8994_AIF1CLK_RATE_MASK, rate_val);
  2561. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2562. switch (dai->id) {
  2563. case 1:
  2564. wm8994->dac_rates[0] = params_rate(params);
  2565. wm8994_set_retune_mobile(component, 0);
  2566. wm8994_set_retune_mobile(component, 1);
  2567. break;
  2568. case 2:
  2569. wm8994->dac_rates[1] = params_rate(params);
  2570. wm8994_set_retune_mobile(component, 2);
  2571. break;
  2572. }
  2573. }
  2574. return 0;
  2575. }
  2576. static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
  2577. struct snd_pcm_hw_params *params,
  2578. struct snd_soc_dai *dai)
  2579. {
  2580. struct snd_soc_component *component = dai->component;
  2581. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2582. struct wm8994 *control = wm8994->wm8994;
  2583. int aif1_reg;
  2584. int aif1 = 0;
  2585. switch (dai->id) {
  2586. case 3:
  2587. switch (control->type) {
  2588. case WM1811:
  2589. case WM8958:
  2590. aif1_reg = WM8958_AIF3_CONTROL_1;
  2591. break;
  2592. default:
  2593. return 0;
  2594. }
  2595. break;
  2596. default:
  2597. return 0;
  2598. }
  2599. switch (params_width(params)) {
  2600. case 16:
  2601. break;
  2602. case 20:
  2603. aif1 |= 0x20;
  2604. break;
  2605. case 24:
  2606. aif1 |= 0x40;
  2607. break;
  2608. case 32:
  2609. aif1 |= 0x60;
  2610. break;
  2611. default:
  2612. return -EINVAL;
  2613. }
  2614. return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  2615. }
  2616. static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute,
  2617. int direction)
  2618. {
  2619. struct snd_soc_component *component = codec_dai->component;
  2620. int mute_reg;
  2621. int reg;
  2622. switch (codec_dai->id) {
  2623. case 1:
  2624. mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
  2625. break;
  2626. case 2:
  2627. mute_reg = WM8994_AIF2_DAC_FILTERS_1;
  2628. break;
  2629. default:
  2630. return -EINVAL;
  2631. }
  2632. if (mute)
  2633. reg = WM8994_AIF1DAC1_MUTE;
  2634. else
  2635. reg = 0;
  2636. snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
  2637. return 0;
  2638. }
  2639. static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
  2640. {
  2641. struct snd_soc_component *component = codec_dai->component;
  2642. int reg, val, mask;
  2643. switch (codec_dai->id) {
  2644. case 1:
  2645. reg = WM8994_AIF1_MASTER_SLAVE;
  2646. mask = WM8994_AIF1_TRI;
  2647. break;
  2648. case 2:
  2649. reg = WM8994_AIF2_MASTER_SLAVE;
  2650. mask = WM8994_AIF2_TRI;
  2651. break;
  2652. default:
  2653. return -EINVAL;
  2654. }
  2655. if (tristate)
  2656. val = mask;
  2657. else
  2658. val = 0;
  2659. return snd_soc_component_update_bits(component, reg, mask, val);
  2660. }
  2661. static int wm8994_aif2_probe(struct snd_soc_dai *dai)
  2662. {
  2663. struct snd_soc_component *component = dai->component;
  2664. /* Disable the pulls on the AIF if we're using it to save power. */
  2665. snd_soc_component_update_bits(component, WM8994_GPIO_3,
  2666. WM8994_GPN_PU | WM8994_GPN_PD, 0);
  2667. snd_soc_component_update_bits(component, WM8994_GPIO_4,
  2668. WM8994_GPN_PU | WM8994_GPN_PD, 0);
  2669. snd_soc_component_update_bits(component, WM8994_GPIO_5,
  2670. WM8994_GPN_PU | WM8994_GPN_PD, 0);
  2671. return 0;
  2672. }
  2673. #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
  2674. #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  2675. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  2676. static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
  2677. .set_sysclk = wm8994_set_dai_sysclk,
  2678. .set_fmt = wm8994_set_dai_fmt,
  2679. .hw_params = wm8994_hw_params,
  2680. .mute_stream = wm8994_aif_mute,
  2681. .set_pll = wm8994_set_fll,
  2682. .set_tristate = wm8994_set_tristate,
  2683. .no_capture_mute = 1,
  2684. };
  2685. static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
  2686. .set_sysclk = wm8994_set_dai_sysclk,
  2687. .set_fmt = wm8994_set_dai_fmt,
  2688. .hw_params = wm8994_hw_params,
  2689. .mute_stream = wm8994_aif_mute,
  2690. .set_pll = wm8994_set_fll,
  2691. .set_tristate = wm8994_set_tristate,
  2692. .no_capture_mute = 1,
  2693. };
  2694. static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
  2695. .hw_params = wm8994_aif3_hw_params,
  2696. };
  2697. static struct snd_soc_dai_driver wm8994_dai[] = {
  2698. {
  2699. .name = "wm8994-aif1",
  2700. .id = 1,
  2701. .playback = {
  2702. .stream_name = "AIF1 Playback",
  2703. .channels_min = 1,
  2704. .channels_max = 2,
  2705. .rates = WM8994_RATES,
  2706. .formats = WM8994_FORMATS,
  2707. .sig_bits = 24,
  2708. },
  2709. .capture = {
  2710. .stream_name = "AIF1 Capture",
  2711. .channels_min = 1,
  2712. .channels_max = 2,
  2713. .rates = WM8994_RATES,
  2714. .formats = WM8994_FORMATS,
  2715. .sig_bits = 24,
  2716. },
  2717. .ops = &wm8994_aif1_dai_ops,
  2718. },
  2719. {
  2720. .name = "wm8994-aif2",
  2721. .id = 2,
  2722. .playback = {
  2723. .stream_name = "AIF2 Playback",
  2724. .channels_min = 1,
  2725. .channels_max = 2,
  2726. .rates = WM8994_RATES,
  2727. .formats = WM8994_FORMATS,
  2728. .sig_bits = 24,
  2729. },
  2730. .capture = {
  2731. .stream_name = "AIF2 Capture",
  2732. .channels_min = 1,
  2733. .channels_max = 2,
  2734. .rates = WM8994_RATES,
  2735. .formats = WM8994_FORMATS,
  2736. .sig_bits = 24,
  2737. },
  2738. .probe = wm8994_aif2_probe,
  2739. .ops = &wm8994_aif2_dai_ops,
  2740. },
  2741. {
  2742. .name = "wm8994-aif3",
  2743. .id = 3,
  2744. .playback = {
  2745. .stream_name = "AIF3 Playback",
  2746. .channels_min = 1,
  2747. .channels_max = 2,
  2748. .rates = WM8994_RATES,
  2749. .formats = WM8994_FORMATS,
  2750. .sig_bits = 24,
  2751. },
  2752. .capture = {
  2753. .stream_name = "AIF3 Capture",
  2754. .channels_min = 1,
  2755. .channels_max = 2,
  2756. .rates = WM8994_RATES,
  2757. .formats = WM8994_FORMATS,
  2758. .sig_bits = 24,
  2759. },
  2760. .ops = &wm8994_aif3_dai_ops,
  2761. }
  2762. };
  2763. #ifdef CONFIG_PM
  2764. static int wm8994_component_suspend(struct snd_soc_component *component)
  2765. {
  2766. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2767. int i, ret;
  2768. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  2769. memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
  2770. sizeof(struct wm8994_fll_config));
  2771. ret = _wm8994_set_fll(component, i + 1, 0, 0, 0);
  2772. if (ret < 0)
  2773. dev_warn(component->dev, "Failed to stop FLL%d: %d\n",
  2774. i + 1, ret);
  2775. }
  2776. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  2777. return 0;
  2778. }
  2779. static int wm8994_component_resume(struct snd_soc_component *component)
  2780. {
  2781. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2782. int i, ret;
  2783. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  2784. if (!wm8994->fll_suspend[i].out)
  2785. continue;
  2786. ret = _wm8994_set_fll(component, i + 1,
  2787. wm8994->fll_suspend[i].src,
  2788. wm8994->fll_suspend[i].in,
  2789. wm8994->fll_suspend[i].out);
  2790. if (ret < 0)
  2791. dev_warn(component->dev, "Failed to restore FLL%d: %d\n",
  2792. i + 1, ret);
  2793. }
  2794. return 0;
  2795. }
  2796. #else
  2797. #define wm8994_component_suspend NULL
  2798. #define wm8994_component_resume NULL
  2799. #endif
  2800. static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
  2801. {
  2802. struct snd_soc_component *component = wm8994->hubs.component;
  2803. struct wm8994 *control = wm8994->wm8994;
  2804. struct wm8994_pdata *pdata = &control->pdata;
  2805. struct snd_kcontrol_new controls[] = {
  2806. SOC_ENUM_EXT("AIF1.1 EQ Mode",
  2807. wm8994->retune_mobile_enum,
  2808. wm8994_get_retune_mobile_enum,
  2809. wm8994_put_retune_mobile_enum),
  2810. SOC_ENUM_EXT("AIF1.2 EQ Mode",
  2811. wm8994->retune_mobile_enum,
  2812. wm8994_get_retune_mobile_enum,
  2813. wm8994_put_retune_mobile_enum),
  2814. SOC_ENUM_EXT("AIF2 EQ Mode",
  2815. wm8994->retune_mobile_enum,
  2816. wm8994_get_retune_mobile_enum,
  2817. wm8994_put_retune_mobile_enum),
  2818. };
  2819. int ret, i, j;
  2820. const char **t;
  2821. /* We need an array of texts for the enum API but the number
  2822. * of texts is likely to be less than the number of
  2823. * configurations due to the sample rate dependency of the
  2824. * configurations. */
  2825. wm8994->num_retune_mobile_texts = 0;
  2826. wm8994->retune_mobile_texts = NULL;
  2827. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  2828. for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
  2829. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  2830. wm8994->retune_mobile_texts[j]) == 0)
  2831. break;
  2832. }
  2833. if (j != wm8994->num_retune_mobile_texts)
  2834. continue;
  2835. /* Expand the array... */
  2836. t = krealloc(wm8994->retune_mobile_texts,
  2837. sizeof(char *) *
  2838. (wm8994->num_retune_mobile_texts + 1),
  2839. GFP_KERNEL);
  2840. if (t == NULL)
  2841. continue;
  2842. /* ...store the new entry... */
  2843. t[wm8994->num_retune_mobile_texts] =
  2844. pdata->retune_mobile_cfgs[i].name;
  2845. /* ...and remember the new version. */
  2846. wm8994->num_retune_mobile_texts++;
  2847. wm8994->retune_mobile_texts = t;
  2848. }
  2849. dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
  2850. wm8994->num_retune_mobile_texts);
  2851. wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
  2852. wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
  2853. ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
  2854. ARRAY_SIZE(controls));
  2855. if (ret != 0)
  2856. dev_err(wm8994->hubs.component->dev,
  2857. "Failed to add ReTune Mobile controls: %d\n", ret);
  2858. }
  2859. static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
  2860. {
  2861. struct snd_soc_component *component = wm8994->hubs.component;
  2862. struct wm8994 *control = wm8994->wm8994;
  2863. struct wm8994_pdata *pdata = &control->pdata;
  2864. int ret, i;
  2865. if (!pdata)
  2866. return;
  2867. wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff,
  2868. pdata->lineout2_diff,
  2869. pdata->lineout1fb,
  2870. pdata->lineout2fb,
  2871. pdata->jd_scthr,
  2872. pdata->jd_thr,
  2873. pdata->micb1_delay,
  2874. pdata->micb2_delay,
  2875. pdata->micbias1_lvl,
  2876. pdata->micbias2_lvl);
  2877. dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  2878. if (pdata->num_drc_cfgs) {
  2879. struct snd_kcontrol_new controls[] = {
  2880. SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
  2881. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2882. SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
  2883. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2884. SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
  2885. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2886. };
  2887. /* We need an array of texts for the enum API */
  2888. wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev,
  2889. pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL);
  2890. if (!wm8994->drc_texts)
  2891. return;
  2892. for (i = 0; i < pdata->num_drc_cfgs; i++)
  2893. wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
  2894. wm8994->drc_enum.items = pdata->num_drc_cfgs;
  2895. wm8994->drc_enum.texts = wm8994->drc_texts;
  2896. ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
  2897. ARRAY_SIZE(controls));
  2898. for (i = 0; i < WM8994_NUM_DRC; i++)
  2899. wm8994_set_drc(component, i);
  2900. } else {
  2901. ret = snd_soc_add_component_controls(wm8994->hubs.component,
  2902. wm8994_drc_controls,
  2903. ARRAY_SIZE(wm8994_drc_controls));
  2904. }
  2905. if (ret != 0)
  2906. dev_err(wm8994->hubs.component->dev,
  2907. "Failed to add DRC mode controls: %d\n", ret);
  2908. dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
  2909. pdata->num_retune_mobile_cfgs);
  2910. if (pdata->num_retune_mobile_cfgs)
  2911. wm8994_handle_retune_mobile_pdata(wm8994);
  2912. else
  2913. snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls,
  2914. ARRAY_SIZE(wm8994_eq_controls));
  2915. for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
  2916. if (pdata->micbias[i]) {
  2917. snd_soc_component_write(component, WM8958_MICBIAS1 + i,
  2918. pdata->micbias[i] & 0xffff);
  2919. }
  2920. }
  2921. }
  2922. /**
  2923. * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
  2924. *
  2925. * @component: WM8994 component
  2926. * @jack: jack to report detection events on
  2927. * @micbias: microphone bias to detect on
  2928. *
  2929. * Enable microphone detection via IRQ on the WM8994. If GPIOs are
  2930. * being used to bring out signals to the processor then only platform
  2931. * data configuration is needed for WM8994 and processor GPIOs should
  2932. * be configured using snd_soc_jack_add_gpios() instead.
  2933. *
  2934. * Configuration of detection levels is available via the micbias1_lvl
  2935. * and micbias2_lvl platform data members.
  2936. */
  2937. int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
  2938. int micbias)
  2939. {
  2940. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  2941. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  2942. struct wm8994_micdet *micdet;
  2943. struct wm8994 *control = wm8994->wm8994;
  2944. int reg, ret;
  2945. if (control->type != WM8994) {
  2946. dev_warn(component->dev, "Not a WM8994\n");
  2947. return -EINVAL;
  2948. }
  2949. pm_runtime_get_sync(component->dev);
  2950. switch (micbias) {
  2951. case 1:
  2952. micdet = &wm8994->micdet[0];
  2953. if (jack)
  2954. ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
  2955. else
  2956. ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
  2957. break;
  2958. case 2:
  2959. micdet = &wm8994->micdet[1];
  2960. if (jack)
  2961. ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
  2962. else
  2963. ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
  2964. break;
  2965. default:
  2966. dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias);
  2967. return -EINVAL;
  2968. }
  2969. if (ret != 0)
  2970. dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n",
  2971. micbias, ret);
  2972. dev_dbg(component->dev, "Configuring microphone detection on %d %p\n",
  2973. micbias, jack);
  2974. /* Store the configuration */
  2975. micdet->jack = jack;
  2976. micdet->detecting = true;
  2977. /* If either of the jacks is set up then enable detection */
  2978. if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
  2979. reg = WM8994_MICD_ENA;
  2980. else
  2981. reg = 0;
  2982. snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
  2983. /* enable MICDET and MICSHRT deboune */
  2984. snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE,
  2985. WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
  2986. WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
  2987. WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
  2988. snd_soc_dapm_sync(dapm);
  2989. pm_runtime_put(component->dev);
  2990. return 0;
  2991. }
  2992. EXPORT_SYMBOL_GPL(wm8994_mic_detect);
  2993. static void wm8994_mic_work(struct work_struct *work)
  2994. {
  2995. struct wm8994_priv *priv = container_of(work,
  2996. struct wm8994_priv,
  2997. mic_work.work);
  2998. struct regmap *regmap = priv->wm8994->regmap;
  2999. struct device *dev = priv->wm8994->dev;
  3000. unsigned int reg;
  3001. int ret;
  3002. int report;
  3003. pm_runtime_get_sync(dev);
  3004. ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
  3005. if (ret < 0) {
  3006. dev_err(dev, "Failed to read microphone status: %d\n",
  3007. ret);
  3008. pm_runtime_put(dev);
  3009. return;
  3010. }
  3011. dev_dbg(dev, "Microphone status: %x\n", reg);
  3012. report = 0;
  3013. if (reg & WM8994_MIC1_DET_STS) {
  3014. if (priv->micdet[0].detecting)
  3015. report = SND_JACK_HEADSET;
  3016. }
  3017. if (reg & WM8994_MIC1_SHRT_STS) {
  3018. if (priv->micdet[0].detecting)
  3019. report = SND_JACK_HEADPHONE;
  3020. else
  3021. report |= SND_JACK_BTN_0;
  3022. }
  3023. if (report)
  3024. priv->micdet[0].detecting = false;
  3025. else
  3026. priv->micdet[0].detecting = true;
  3027. snd_soc_jack_report(priv->micdet[0].jack, report,
  3028. SND_JACK_HEADSET | SND_JACK_BTN_0);
  3029. report = 0;
  3030. if (reg & WM8994_MIC2_DET_STS) {
  3031. if (priv->micdet[1].detecting)
  3032. report = SND_JACK_HEADSET;
  3033. }
  3034. if (reg & WM8994_MIC2_SHRT_STS) {
  3035. if (priv->micdet[1].detecting)
  3036. report = SND_JACK_HEADPHONE;
  3037. else
  3038. report |= SND_JACK_BTN_0;
  3039. }
  3040. if (report)
  3041. priv->micdet[1].detecting = false;
  3042. else
  3043. priv->micdet[1].detecting = true;
  3044. snd_soc_jack_report(priv->micdet[1].jack, report,
  3045. SND_JACK_HEADSET | SND_JACK_BTN_0);
  3046. pm_runtime_put(dev);
  3047. }
  3048. static irqreturn_t wm8994_mic_irq(int irq, void *data)
  3049. {
  3050. struct wm8994_priv *priv = data;
  3051. struct snd_soc_component *component = priv->hubs.component;
  3052. #ifndef CONFIG_SND_SOC_WM8994_MODULE
  3053. trace_snd_soc_jack_irq(dev_name(component->dev));
  3054. #endif
  3055. pm_wakeup_event(component->dev, 300);
  3056. queue_delayed_work(system_power_efficient_wq,
  3057. &priv->mic_work, msecs_to_jiffies(250));
  3058. return IRQ_HANDLED;
  3059. }
  3060. /* Should be called with accdet_lock held */
  3061. static void wm1811_micd_stop(struct snd_soc_component *component)
  3062. {
  3063. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  3064. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  3065. if (!wm8994->jackdet)
  3066. return;
  3067. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
  3068. wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
  3069. if (wm8994->wm8994->pdata.jd_ext_cap)
  3070. snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
  3071. }
  3072. static void wm8958_button_det(struct snd_soc_component *component, u16 status)
  3073. {
  3074. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  3075. int report;
  3076. report = 0;
  3077. if (status & 0x4)
  3078. report |= SND_JACK_BTN_0;
  3079. if (status & 0x8)
  3080. report |= SND_JACK_BTN_1;
  3081. if (status & 0x10)
  3082. report |= SND_JACK_BTN_2;
  3083. if (status & 0x20)
  3084. report |= SND_JACK_BTN_3;
  3085. if (status & 0x40)
  3086. report |= SND_JACK_BTN_4;
  3087. if (status & 0x80)
  3088. report |= SND_JACK_BTN_5;
  3089. snd_soc_jack_report(wm8994->micdet[0].jack, report,
  3090. wm8994->btn_mask);
  3091. }
  3092. static void wm8958_open_circuit_work(struct work_struct *work)
  3093. {
  3094. struct wm8994_priv *wm8994 = container_of(work,
  3095. struct wm8994_priv,
  3096. open_circuit_work.work);
  3097. struct device *dev = wm8994->wm8994->dev;
  3098. mutex_lock(&wm8994->accdet_lock);
  3099. wm1811_micd_stop(wm8994->hubs.component);
  3100. dev_dbg(dev, "Reporting open circuit\n");
  3101. wm8994->jack_mic = false;
  3102. wm8994->mic_detecting = true;
  3103. wm8958_micd_set_rate(wm8994->hubs.component);
  3104. snd_soc_jack_report(wm8994->micdet[0].jack, 0,
  3105. wm8994->btn_mask |
  3106. SND_JACK_HEADSET);
  3107. mutex_unlock(&wm8994->accdet_lock);
  3108. }
  3109. static void wm8958_mic_id(void *data, u16 status)
  3110. {
  3111. struct snd_soc_component *component = data;
  3112. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  3113. /* Either nothing present or just starting detection */
  3114. if (!(status & WM8958_MICD_STS)) {
  3115. /* If nothing present then clear our statuses */
  3116. dev_dbg(component->dev, "Detected open circuit\n");
  3117. queue_delayed_work(system_power_efficient_wq,
  3118. &wm8994->open_circuit_work,
  3119. msecs_to_jiffies(2500));
  3120. return;
  3121. }
  3122. /* If the measurement is showing a high impedence we've got a
  3123. * microphone.
  3124. */
  3125. if (status & 0x600) {
  3126. dev_dbg(component->dev, "Detected microphone\n");
  3127. wm8994->mic_detecting = false;
  3128. wm8994->jack_mic = true;
  3129. wm8958_micd_set_rate(component);
  3130. snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
  3131. SND_JACK_HEADSET);
  3132. }
  3133. if (status & 0xfc) {
  3134. dev_dbg(component->dev, "Detected headphone\n");
  3135. wm8994->mic_detecting = false;
  3136. wm8958_micd_set_rate(component);
  3137. /* If we have jackdet that will detect removal */
  3138. wm1811_micd_stop(component);
  3139. snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
  3140. SND_JACK_HEADSET);
  3141. }
  3142. }
  3143. /* Deferred mic detection to allow for extra settling time */
  3144. static void wm1811_mic_work(struct work_struct *work)
  3145. {
  3146. struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
  3147. mic_work.work);
  3148. struct wm8994 *control = wm8994->wm8994;
  3149. struct snd_soc_component *component = wm8994->hubs.component;
  3150. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  3151. pm_runtime_get_sync(component->dev);
  3152. /* If required for an external cap force MICBIAS on */
  3153. if (control->pdata.jd_ext_cap) {
  3154. snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
  3155. snd_soc_dapm_sync(dapm);
  3156. }
  3157. mutex_lock(&wm8994->accdet_lock);
  3158. dev_dbg(component->dev, "Starting mic detection\n");
  3159. /* Use a user-supplied callback if we have one */
  3160. if (wm8994->micd_cb) {
  3161. wm8994->micd_cb(wm8994->micd_cb_data);
  3162. } else {
  3163. /*
  3164. * Start off measument of microphone impedence to find out
  3165. * what's actually there.
  3166. */
  3167. wm8994->mic_detecting = true;
  3168. wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC);
  3169. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
  3170. WM8958_MICD_ENA, WM8958_MICD_ENA);
  3171. }
  3172. mutex_unlock(&wm8994->accdet_lock);
  3173. pm_runtime_put(component->dev);
  3174. }
  3175. static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
  3176. {
  3177. struct wm8994_priv *wm8994 = data;
  3178. struct wm8994 *control = wm8994->wm8994;
  3179. struct snd_soc_component *component = wm8994->hubs.component;
  3180. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  3181. int reg, delay;
  3182. bool present;
  3183. pm_runtime_get_sync(component->dev);
  3184. cancel_delayed_work_sync(&wm8994->mic_complete_work);
  3185. mutex_lock(&wm8994->accdet_lock);
  3186. reg = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
  3187. if (reg < 0) {
  3188. dev_err(component->dev, "Failed to read jack status: %d\n", reg);
  3189. mutex_unlock(&wm8994->accdet_lock);
  3190. pm_runtime_put(component->dev);
  3191. return IRQ_NONE;
  3192. }
  3193. dev_dbg(component->dev, "JACKDET %x\n", reg);
  3194. present = reg & WM1811_JACKDET_LVL;
  3195. if (present) {
  3196. dev_dbg(component->dev, "Jack detected\n");
  3197. wm8958_micd_set_rate(component);
  3198. snd_soc_component_update_bits(component, WM8958_MICBIAS2,
  3199. WM8958_MICB2_DISCH, 0);
  3200. /* Disable debounce while inserted */
  3201. snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
  3202. WM1811_JACKDET_DB, 0);
  3203. delay = control->pdata.micdet_delay;
  3204. queue_delayed_work(system_power_efficient_wq,
  3205. &wm8994->mic_work,
  3206. msecs_to_jiffies(delay));
  3207. } else {
  3208. dev_dbg(component->dev, "Jack not detected\n");
  3209. cancel_delayed_work_sync(&wm8994->mic_work);
  3210. snd_soc_component_update_bits(component, WM8958_MICBIAS2,
  3211. WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
  3212. /* Enable debounce while removed */
  3213. snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
  3214. WM1811_JACKDET_DB, WM1811_JACKDET_DB);
  3215. wm8994->mic_detecting = false;
  3216. wm8994->jack_mic = false;
  3217. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
  3218. WM8958_MICD_ENA, 0);
  3219. wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
  3220. }
  3221. mutex_unlock(&wm8994->accdet_lock);
  3222. /* Turn off MICBIAS if it was on for an external cap */
  3223. if (control->pdata.jd_ext_cap && !present)
  3224. snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
  3225. if (present)
  3226. snd_soc_jack_report(wm8994->micdet[0].jack,
  3227. SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
  3228. else
  3229. snd_soc_jack_report(wm8994->micdet[0].jack, 0,
  3230. SND_JACK_MECHANICAL | SND_JACK_HEADSET |
  3231. wm8994->btn_mask);
  3232. /* Since we only report deltas force an update, ensures we
  3233. * avoid bootstrapping issues with the core. */
  3234. snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
  3235. pm_runtime_put(component->dev);
  3236. return IRQ_HANDLED;
  3237. }
  3238. static void wm1811_jackdet_bootstrap(struct work_struct *work)
  3239. {
  3240. struct wm8994_priv *wm8994 = container_of(work,
  3241. struct wm8994_priv,
  3242. jackdet_bootstrap.work);
  3243. wm1811_jackdet_irq(0, wm8994);
  3244. }
  3245. /**
  3246. * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
  3247. *
  3248. * @component: WM8958 component
  3249. * @jack: jack to report detection events on
  3250. * @det_cb: detection callback
  3251. * @det_cb_data: data for detection callback
  3252. * @id_cb: mic id callback
  3253. * @id_cb_data: data for mic id callback
  3254. *
  3255. * Enable microphone detection functionality for the WM8958. By
  3256. * default simple detection which supports the detection of up to 6
  3257. * buttons plus video and microphone functionality is supported.
  3258. *
  3259. * The WM8958 has an advanced jack detection facility which is able to
  3260. * support complex accessory detection, especially when used in
  3261. * conjunction with external circuitry. In order to provide maximum
  3262. * flexiblity a callback is provided which allows a completely custom
  3263. * detection algorithm.
  3264. */
  3265. int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
  3266. wm1811_micdet_cb det_cb, void *det_cb_data,
  3267. wm1811_mic_id_cb id_cb, void *id_cb_data)
  3268. {
  3269. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  3270. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  3271. struct wm8994 *control = wm8994->wm8994;
  3272. u16 micd_lvl_sel;
  3273. switch (control->type) {
  3274. case WM1811:
  3275. case WM8958:
  3276. break;
  3277. default:
  3278. return -EINVAL;
  3279. }
  3280. pm_runtime_get_sync(component->dev);
  3281. if (jack) {
  3282. snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
  3283. snd_soc_dapm_sync(dapm);
  3284. wm8994->micdet[0].jack = jack;
  3285. if (det_cb) {
  3286. wm8994->micd_cb = det_cb;
  3287. wm8994->micd_cb_data = det_cb_data;
  3288. } else {
  3289. wm8994->mic_detecting = true;
  3290. wm8994->jack_mic = false;
  3291. }
  3292. if (id_cb) {
  3293. wm8994->mic_id_cb = id_cb;
  3294. wm8994->mic_id_cb_data = id_cb_data;
  3295. } else {
  3296. wm8994->mic_id_cb = wm8958_mic_id;
  3297. wm8994->mic_id_cb_data = component;
  3298. }
  3299. wm8958_micd_set_rate(component);
  3300. /* Detect microphones and short circuits by default */
  3301. if (control->pdata.micd_lvl_sel)
  3302. micd_lvl_sel = control->pdata.micd_lvl_sel;
  3303. else
  3304. micd_lvl_sel = 0x41;
  3305. wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  3306. SND_JACK_BTN_2 | SND_JACK_BTN_3 |
  3307. SND_JACK_BTN_4 | SND_JACK_BTN_5;
  3308. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2,
  3309. WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
  3310. WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY);
  3311. /*
  3312. * If we can use jack detection start off with that,
  3313. * otherwise jump straight to microphone detection.
  3314. */
  3315. if (wm8994->jackdet) {
  3316. /* Disable debounce for the initial detect */
  3317. snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
  3318. WM1811_JACKDET_DB, 0);
  3319. snd_soc_component_update_bits(component, WM8958_MICBIAS2,
  3320. WM8958_MICB2_DISCH,
  3321. WM8958_MICB2_DISCH);
  3322. snd_soc_component_update_bits(component, WM8994_LDO_1,
  3323. WM8994_LDO1_DISCH, 0);
  3324. wm1811_jackdet_set_mode(component,
  3325. WM1811_JACKDET_MODE_JACK);
  3326. } else {
  3327. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
  3328. WM8958_MICD_ENA, WM8958_MICD_ENA);
  3329. }
  3330. } else {
  3331. snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
  3332. WM8958_MICD_ENA, 0);
  3333. wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE);
  3334. snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
  3335. snd_soc_dapm_sync(dapm);
  3336. }
  3337. pm_runtime_put(component->dev);
  3338. return 0;
  3339. }
  3340. EXPORT_SYMBOL_GPL(wm8958_mic_detect);
  3341. static void wm8958_mic_work(struct work_struct *work)
  3342. {
  3343. struct wm8994_priv *wm8994 = container_of(work,
  3344. struct wm8994_priv,
  3345. mic_complete_work.work);
  3346. struct snd_soc_component *component = wm8994->hubs.component;
  3347. pm_runtime_get_sync(component->dev);
  3348. mutex_lock(&wm8994->accdet_lock);
  3349. wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
  3350. mutex_unlock(&wm8994->accdet_lock);
  3351. pm_runtime_put(component->dev);
  3352. }
  3353. static irqreturn_t wm8958_mic_irq(int irq, void *data)
  3354. {
  3355. struct wm8994_priv *wm8994 = data;
  3356. struct snd_soc_component *component = wm8994->hubs.component;
  3357. int reg, count, ret, id_delay;
  3358. /*
  3359. * Jack detection may have detected a removal simulataneously
  3360. * with an update of the MICDET status; if so it will have
  3361. * stopped detection and we can ignore this interrupt.
  3362. */
  3363. if (!(snd_soc_component_read(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
  3364. return IRQ_HANDLED;
  3365. cancel_delayed_work_sync(&wm8994->mic_complete_work);
  3366. cancel_delayed_work_sync(&wm8994->open_circuit_work);
  3367. pm_runtime_get_sync(component->dev);
  3368. /* We may occasionally read a detection without an impedence
  3369. * range being provided - if that happens loop again.
  3370. */
  3371. count = 10;
  3372. do {
  3373. reg = snd_soc_component_read(component, WM8958_MIC_DETECT_3);
  3374. if (reg < 0) {
  3375. dev_err(component->dev,
  3376. "Failed to read mic detect status: %d\n",
  3377. reg);
  3378. pm_runtime_put(component->dev);
  3379. return IRQ_NONE;
  3380. }
  3381. if (!(reg & WM8958_MICD_VALID)) {
  3382. dev_dbg(component->dev, "Mic detect data not valid\n");
  3383. goto out;
  3384. }
  3385. if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
  3386. break;
  3387. msleep(1);
  3388. } while (count--);
  3389. if (count == 0)
  3390. dev_warn(component->dev, "No impedance range reported for jack\n");
  3391. #ifndef CONFIG_SND_SOC_WM8994_MODULE
  3392. trace_snd_soc_jack_irq(dev_name(component->dev));
  3393. #endif
  3394. /* Avoid a transient report when the accessory is being removed */
  3395. if (wm8994->jackdet) {
  3396. ret = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
  3397. if (ret < 0) {
  3398. dev_err(component->dev, "Failed to read jack status: %d\n",
  3399. ret);
  3400. } else if (!(ret & WM1811_JACKDET_LVL)) {
  3401. dev_dbg(component->dev, "Ignoring removed jack\n");
  3402. goto out;
  3403. }
  3404. } else if (!(reg & WM8958_MICD_STS)) {
  3405. snd_soc_jack_report(wm8994->micdet[0].jack, 0,
  3406. SND_JACK_MECHANICAL | SND_JACK_HEADSET |
  3407. wm8994->btn_mask);
  3408. wm8994->mic_detecting = true;
  3409. goto out;
  3410. }
  3411. wm8994->mic_status = reg;
  3412. id_delay = wm8994->wm8994->pdata.mic_id_delay;
  3413. if (wm8994->mic_detecting)
  3414. queue_delayed_work(system_power_efficient_wq,
  3415. &wm8994->mic_complete_work,
  3416. msecs_to_jiffies(id_delay));
  3417. else
  3418. wm8958_button_det(component, reg);
  3419. out:
  3420. pm_runtime_put(component->dev);
  3421. return IRQ_HANDLED;
  3422. }
  3423. static irqreturn_t wm8994_fifo_error(int irq, void *data)
  3424. {
  3425. struct snd_soc_component *component = data;
  3426. dev_err(component->dev, "FIFO error\n");
  3427. return IRQ_HANDLED;
  3428. }
  3429. static irqreturn_t wm8994_temp_warn(int irq, void *data)
  3430. {
  3431. struct snd_soc_component *component = data;
  3432. dev_err(component->dev, "Thermal warning\n");
  3433. return IRQ_HANDLED;
  3434. }
  3435. static irqreturn_t wm8994_temp_shut(int irq, void *data)
  3436. {
  3437. struct snd_soc_component *component = data;
  3438. dev_crit(component->dev, "Thermal shutdown\n");
  3439. return IRQ_HANDLED;
  3440. }
  3441. static int wm8994_component_probe(struct snd_soc_component *component)
  3442. {
  3443. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  3444. struct wm8994 *control = dev_get_drvdata(component->dev->parent);
  3445. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  3446. unsigned int reg;
  3447. int ret, i;
  3448. snd_soc_component_init_regmap(component, control->regmap);
  3449. wm8994->hubs.component = component;
  3450. mutex_init(&wm8994->accdet_lock);
  3451. INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
  3452. wm1811_jackdet_bootstrap);
  3453. INIT_DELAYED_WORK(&wm8994->open_circuit_work,
  3454. wm8958_open_circuit_work);
  3455. switch (control->type) {
  3456. case WM8994:
  3457. INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
  3458. break;
  3459. case WM1811:
  3460. INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
  3461. break;
  3462. default:
  3463. break;
  3464. }
  3465. INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
  3466. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
  3467. init_completion(&wm8994->fll_locked[i]);
  3468. wm8994->micdet_irq = control->pdata.micdet_irq;
  3469. /* By default use idle_bias_off, will override for WM8994 */
  3470. dapm->idle_bias_off = 1;
  3471. /* Set revision-specific configuration */
  3472. switch (control->type) {
  3473. case WM8994:
  3474. /* Single ended line outputs should have VMID on. */
  3475. if (!control->pdata.lineout1_diff ||
  3476. !control->pdata.lineout2_diff)
  3477. dapm->idle_bias_off = 0;
  3478. switch (control->revision) {
  3479. case 2:
  3480. case 3:
  3481. wm8994->hubs.dcs_codes_l = -5;
  3482. wm8994->hubs.dcs_codes_r = -5;
  3483. wm8994->hubs.hp_startup_mode = 1;
  3484. wm8994->hubs.dcs_readback_mode = 1;
  3485. wm8994->hubs.series_startup = 1;
  3486. break;
  3487. default:
  3488. wm8994->hubs.dcs_readback_mode = 2;
  3489. break;
  3490. }
  3491. wm8994->hubs.micd_scthr = true;
  3492. break;
  3493. case WM8958:
  3494. wm8994->hubs.dcs_readback_mode = 1;
  3495. wm8994->hubs.hp_startup_mode = 1;
  3496. wm8994->hubs.micd_scthr = true;
  3497. switch (control->revision) {
  3498. case 0:
  3499. break;
  3500. default:
  3501. wm8994->fll_byp = true;
  3502. break;
  3503. }
  3504. break;
  3505. case WM1811:
  3506. wm8994->hubs.dcs_readback_mode = 2;
  3507. wm8994->hubs.no_series_update = 1;
  3508. wm8994->hubs.hp_startup_mode = 1;
  3509. wm8994->hubs.no_cache_dac_hp_direct = true;
  3510. wm8994->fll_byp = true;
  3511. wm8994->hubs.dcs_codes_l = -9;
  3512. wm8994->hubs.dcs_codes_r = -7;
  3513. snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1,
  3514. WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
  3515. break;
  3516. default:
  3517. break;
  3518. }
  3519. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
  3520. wm8994_fifo_error, "FIFO error", component);
  3521. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
  3522. wm8994_temp_warn, "Thermal warning", component);
  3523. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
  3524. wm8994_temp_shut, "Thermal shutdown", component);
  3525. switch (control->type) {
  3526. case WM8994:
  3527. if (wm8994->micdet_irq)
  3528. ret = request_threaded_irq(wm8994->micdet_irq, NULL,
  3529. wm8994_mic_irq,
  3530. IRQF_TRIGGER_RISING |
  3531. IRQF_ONESHOT,
  3532. "Mic1 detect",
  3533. wm8994);
  3534. else
  3535. ret = wm8994_request_irq(wm8994->wm8994,
  3536. WM8994_IRQ_MIC1_DET,
  3537. wm8994_mic_irq, "Mic 1 detect",
  3538. wm8994);
  3539. if (ret != 0)
  3540. dev_warn(component->dev,
  3541. "Failed to request Mic1 detect IRQ: %d\n",
  3542. ret);
  3543. ret = wm8994_request_irq(wm8994->wm8994,
  3544. WM8994_IRQ_MIC1_SHRT,
  3545. wm8994_mic_irq, "Mic 1 short",
  3546. wm8994);
  3547. if (ret != 0)
  3548. dev_warn(component->dev,
  3549. "Failed to request Mic1 short IRQ: %d\n",
  3550. ret);
  3551. ret = wm8994_request_irq(wm8994->wm8994,
  3552. WM8994_IRQ_MIC2_DET,
  3553. wm8994_mic_irq, "Mic 2 detect",
  3554. wm8994);
  3555. if (ret != 0)
  3556. dev_warn(component->dev,
  3557. "Failed to request Mic2 detect IRQ: %d\n",
  3558. ret);
  3559. ret = wm8994_request_irq(wm8994->wm8994,
  3560. WM8994_IRQ_MIC2_SHRT,
  3561. wm8994_mic_irq, "Mic 2 short",
  3562. wm8994);
  3563. if (ret != 0)
  3564. dev_warn(component->dev,
  3565. "Failed to request Mic2 short IRQ: %d\n",
  3566. ret);
  3567. break;
  3568. case WM8958:
  3569. case WM1811:
  3570. if (wm8994->micdet_irq) {
  3571. ret = request_threaded_irq(wm8994->micdet_irq, NULL,
  3572. wm8958_mic_irq,
  3573. IRQF_TRIGGER_RISING |
  3574. IRQF_ONESHOT,
  3575. "Mic detect",
  3576. wm8994);
  3577. if (ret != 0)
  3578. dev_warn(component->dev,
  3579. "Failed to request Mic detect IRQ: %d\n",
  3580. ret);
  3581. } else {
  3582. wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
  3583. wm8958_mic_irq, "Mic detect",
  3584. wm8994);
  3585. }
  3586. }
  3587. switch (control->type) {
  3588. case WM1811:
  3589. if (control->cust_id > 1 || control->revision > 1) {
  3590. ret = wm8994_request_irq(wm8994->wm8994,
  3591. WM8994_IRQ_GPIO(6),
  3592. wm1811_jackdet_irq, "JACKDET",
  3593. wm8994);
  3594. if (ret == 0)
  3595. wm8994->jackdet = true;
  3596. }
  3597. break;
  3598. default:
  3599. break;
  3600. }
  3601. wm8994->fll_locked_irq = true;
  3602. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
  3603. ret = wm8994_request_irq(wm8994->wm8994,
  3604. WM8994_IRQ_FLL1_LOCK + i,
  3605. wm8994_fll_locked_irq, "FLL lock",
  3606. &wm8994->fll_locked[i]);
  3607. if (ret != 0)
  3608. wm8994->fll_locked_irq = false;
  3609. }
  3610. /* Make sure we can read from the GPIOs if they're inputs */
  3611. pm_runtime_get_sync(component->dev);
  3612. /* Remember if AIFnLRCLK is configured as a GPIO. This should be
  3613. * configured on init - if a system wants to do this dynamically
  3614. * at runtime we can deal with that then.
  3615. */
  3616. ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
  3617. if (ret < 0) {
  3618. dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret);
  3619. goto err_irq;
  3620. }
  3621. if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  3622. wm8994->lrclk_shared[0] = 1;
  3623. wm8994_dai[0].symmetric_rates = 1;
  3624. } else {
  3625. wm8994->lrclk_shared[0] = 0;
  3626. }
  3627. ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
  3628. if (ret < 0) {
  3629. dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret);
  3630. goto err_irq;
  3631. }
  3632. if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  3633. wm8994->lrclk_shared[1] = 1;
  3634. wm8994_dai[1].symmetric_rates = 1;
  3635. } else {
  3636. wm8994->lrclk_shared[1] = 0;
  3637. }
  3638. pm_runtime_put(component->dev);
  3639. /* Latch volume update bits */
  3640. for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
  3641. snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg,
  3642. wm8994_vu_bits[i].mask,
  3643. wm8994_vu_bits[i].mask);
  3644. if (control->type != WM1811) {
  3645. for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++)
  3646. snd_soc_component_update_bits(component,
  3647. wm8994_adc2_dac2_vu_bits[i].reg,
  3648. wm8994_adc2_dac2_vu_bits[i].mask,
  3649. wm8994_adc2_dac2_vu_bits[i].mask);
  3650. }
  3651. /* Set the low bit of the 3D stereo depth so TLV matches */
  3652. snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
  3653. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
  3654. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
  3655. snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2,
  3656. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
  3657. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
  3658. snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2,
  3659. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
  3660. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
  3661. /* Unconditionally enable AIF1 ADC TDM mode on chips which can
  3662. * use this; it only affects behaviour on idle TDM clock
  3663. * cycles. */
  3664. switch (control->type) {
  3665. case WM8994:
  3666. case WM8958:
  3667. snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1,
  3668. WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
  3669. break;
  3670. default:
  3671. break;
  3672. }
  3673. /* Put MICBIAS into bypass mode by default on newer devices */
  3674. switch (control->type) {
  3675. case WM8958:
  3676. case WM1811:
  3677. snd_soc_component_update_bits(component, WM8958_MICBIAS1,
  3678. WM8958_MICB1_MODE, WM8958_MICB1_MODE);
  3679. snd_soc_component_update_bits(component, WM8958_MICBIAS2,
  3680. WM8958_MICB2_MODE, WM8958_MICB2_MODE);
  3681. break;
  3682. default:
  3683. break;
  3684. }
  3685. wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
  3686. wm_hubs_update_class_w(component);
  3687. wm8994_handle_pdata(wm8994);
  3688. wm_hubs_add_analogue_controls(component);
  3689. snd_soc_add_component_controls(component, wm8994_common_snd_controls,
  3690. ARRAY_SIZE(wm8994_common_snd_controls));
  3691. snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
  3692. ARRAY_SIZE(wm8994_dapm_widgets));
  3693. switch (control->type) {
  3694. case WM8994:
  3695. snd_soc_add_component_controls(component, wm8994_snd_controls,
  3696. ARRAY_SIZE(wm8994_snd_controls));
  3697. snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
  3698. ARRAY_SIZE(wm8994_specific_dapm_widgets));
  3699. if (control->revision < 4) {
  3700. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
  3701. ARRAY_SIZE(wm8994_lateclk_revd_widgets));
  3702. snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
  3703. ARRAY_SIZE(wm8994_adc_revd_widgets));
  3704. snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
  3705. ARRAY_SIZE(wm8994_dac_revd_widgets));
  3706. } else {
  3707. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  3708. ARRAY_SIZE(wm8994_lateclk_widgets));
  3709. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  3710. ARRAY_SIZE(wm8994_adc_widgets));
  3711. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  3712. ARRAY_SIZE(wm8994_dac_widgets));
  3713. }
  3714. break;
  3715. case WM8958:
  3716. snd_soc_add_component_controls(component, wm8994_snd_controls,
  3717. ARRAY_SIZE(wm8994_snd_controls));
  3718. snd_soc_add_component_controls(component, wm8958_snd_controls,
  3719. ARRAY_SIZE(wm8958_snd_controls));
  3720. snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
  3721. ARRAY_SIZE(wm8958_dapm_widgets));
  3722. if (control->revision < 1) {
  3723. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
  3724. ARRAY_SIZE(wm8994_lateclk_revd_widgets));
  3725. snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
  3726. ARRAY_SIZE(wm8994_adc_revd_widgets));
  3727. snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
  3728. ARRAY_SIZE(wm8994_dac_revd_widgets));
  3729. } else {
  3730. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  3731. ARRAY_SIZE(wm8994_lateclk_widgets));
  3732. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  3733. ARRAY_SIZE(wm8994_adc_widgets));
  3734. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  3735. ARRAY_SIZE(wm8994_dac_widgets));
  3736. }
  3737. break;
  3738. case WM1811:
  3739. snd_soc_add_component_controls(component, wm8958_snd_controls,
  3740. ARRAY_SIZE(wm8958_snd_controls));
  3741. snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
  3742. ARRAY_SIZE(wm8958_dapm_widgets));
  3743. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  3744. ARRAY_SIZE(wm8994_lateclk_widgets));
  3745. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  3746. ARRAY_SIZE(wm8994_adc_widgets));
  3747. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  3748. ARRAY_SIZE(wm8994_dac_widgets));
  3749. break;
  3750. }
  3751. wm_hubs_add_analogue_routes(component, 0, 0);
  3752. ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
  3753. wm_hubs_dcs_done, "DC servo done",
  3754. &wm8994->hubs);
  3755. if (ret == 0)
  3756. wm8994->hubs.dcs_done_irq = true;
  3757. snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
  3758. switch (control->type) {
  3759. case WM8994:
  3760. snd_soc_dapm_add_routes(dapm, wm8994_intercon,
  3761. ARRAY_SIZE(wm8994_intercon));
  3762. if (control->revision < 4) {
  3763. snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
  3764. ARRAY_SIZE(wm8994_revd_intercon));
  3765. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
  3766. ARRAY_SIZE(wm8994_lateclk_revd_intercon));
  3767. } else {
  3768. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  3769. ARRAY_SIZE(wm8994_lateclk_intercon));
  3770. }
  3771. break;
  3772. case WM8958:
  3773. if (control->revision < 1) {
  3774. snd_soc_dapm_add_routes(dapm, wm8994_intercon,
  3775. ARRAY_SIZE(wm8994_intercon));
  3776. snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
  3777. ARRAY_SIZE(wm8994_revd_intercon));
  3778. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
  3779. ARRAY_SIZE(wm8994_lateclk_revd_intercon));
  3780. } else {
  3781. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  3782. ARRAY_SIZE(wm8994_lateclk_intercon));
  3783. snd_soc_dapm_add_routes(dapm, wm8958_intercon,
  3784. ARRAY_SIZE(wm8958_intercon));
  3785. }
  3786. wm8958_dsp2_init(component);
  3787. break;
  3788. case WM1811:
  3789. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  3790. ARRAY_SIZE(wm8994_lateclk_intercon));
  3791. snd_soc_dapm_add_routes(dapm, wm8958_intercon,
  3792. ARRAY_SIZE(wm8958_intercon));
  3793. break;
  3794. }
  3795. return 0;
  3796. err_irq:
  3797. if (wm8994->jackdet)
  3798. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
  3799. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
  3800. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
  3801. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
  3802. if (wm8994->micdet_irq)
  3803. free_irq(wm8994->micdet_irq, wm8994);
  3804. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
  3805. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
  3806. &wm8994->fll_locked[i]);
  3807. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
  3808. &wm8994->hubs);
  3809. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
  3810. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
  3811. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
  3812. return ret;
  3813. }
  3814. static void wm8994_component_remove(struct snd_soc_component *component)
  3815. {
  3816. struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
  3817. struct wm8994 *control = wm8994->wm8994;
  3818. int i;
  3819. for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
  3820. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
  3821. &wm8994->fll_locked[i]);
  3822. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
  3823. &wm8994->hubs);
  3824. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
  3825. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
  3826. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
  3827. if (wm8994->jackdet)
  3828. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
  3829. switch (control->type) {
  3830. case WM8994:
  3831. if (wm8994->micdet_irq)
  3832. free_irq(wm8994->micdet_irq, wm8994);
  3833. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
  3834. wm8994);
  3835. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
  3836. wm8994);
  3837. wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
  3838. wm8994);
  3839. break;
  3840. case WM1811:
  3841. case WM8958:
  3842. if (wm8994->micdet_irq)
  3843. free_irq(wm8994->micdet_irq, wm8994);
  3844. break;
  3845. }
  3846. release_firmware(wm8994->mbc);
  3847. release_firmware(wm8994->mbc_vss);
  3848. release_firmware(wm8994->enh_eq);
  3849. kfree(wm8994->retune_mobile_texts);
  3850. }
  3851. static const struct snd_soc_component_driver soc_component_dev_wm8994 = {
  3852. .probe = wm8994_component_probe,
  3853. .remove = wm8994_component_remove,
  3854. .suspend = wm8994_component_suspend,
  3855. .resume = wm8994_component_resume,
  3856. .set_bias_level = wm8994_set_bias_level,
  3857. .idle_bias_on = 1,
  3858. .use_pmdown_time = 1,
  3859. .endianness = 1,
  3860. .non_legacy_dai_naming = 1,
  3861. };
  3862. static int wm8994_probe(struct platform_device *pdev)
  3863. {
  3864. struct wm8994_priv *wm8994;
  3865. int ret;
  3866. wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
  3867. GFP_KERNEL);
  3868. if (wm8994 == NULL)
  3869. return -ENOMEM;
  3870. platform_set_drvdata(pdev, wm8994);
  3871. mutex_init(&wm8994->fw_lock);
  3872. wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
  3873. wm8994->mclk[WM8994_MCLK1].id = "MCLK1";
  3874. wm8994->mclk[WM8994_MCLK2].id = "MCLK2";
  3875. ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk),
  3876. wm8994->mclk);
  3877. if (ret < 0) {
  3878. dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret);
  3879. return ret;
  3880. }
  3881. pm_runtime_enable(&pdev->dev);
  3882. pm_runtime_idle(&pdev->dev);
  3883. ret = devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
  3884. wm8994_dai, ARRAY_SIZE(wm8994_dai));
  3885. if (ret < 0)
  3886. pm_runtime_disable(&pdev->dev);
  3887. return ret;
  3888. }
  3889. static int wm8994_remove(struct platform_device *pdev)
  3890. {
  3891. pm_runtime_disable(&pdev->dev);
  3892. return 0;
  3893. }
  3894. #ifdef CONFIG_PM_SLEEP
  3895. static int wm8994_suspend(struct device *dev)
  3896. {
  3897. struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
  3898. /* Drop down to power saving mode when system is suspended */
  3899. if (wm8994->jackdet && !wm8994->active_refcount)
  3900. regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
  3901. WM1811_JACKDET_MODE_MASK,
  3902. wm8994->jackdet_mode);
  3903. return 0;
  3904. }
  3905. static int wm8994_resume(struct device *dev)
  3906. {
  3907. struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
  3908. if (wm8994->jackdet && wm8994->jackdet_mode)
  3909. regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
  3910. WM1811_JACKDET_MODE_MASK,
  3911. WM1811_JACKDET_MODE_AUDIO);
  3912. return 0;
  3913. }
  3914. #endif
  3915. static const struct dev_pm_ops wm8994_pm_ops = {
  3916. SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
  3917. };
  3918. static struct platform_driver wm8994_codec_driver = {
  3919. .driver = {
  3920. .name = "wm8994-codec",
  3921. .pm = &wm8994_pm_ops,
  3922. },
  3923. .probe = wm8994_probe,
  3924. .remove = wm8994_remove,
  3925. };
  3926. module_platform_driver(wm8994_codec_driver);
  3927. MODULE_DESCRIPTION("ASoC WM8994 driver");
  3928. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  3929. MODULE_LICENSE("GPL");
  3930. MODULE_ALIAS("platform:wm8994-codec");