wm8993.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8993.c -- WM8993 ALSA SoC audio driver
  4. *
  5. * Copyright 2009-12 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/slab.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/tlv.h>
  23. #include <sound/soc.h>
  24. #include <sound/initval.h>
  25. #include <sound/wm8993.h>
  26. #include "wm8993.h"
  27. #include "wm_hubs.h"
  28. #define WM8993_NUM_SUPPLIES 6
  29. static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
  30. "DCVDD",
  31. "DBVDD",
  32. "AVDD1",
  33. "AVDD2",
  34. "CPVDD",
  35. "SPKVDD",
  36. };
  37. static const struct reg_default wm8993_reg_defaults[] = {
  38. { 1, 0x0000 }, /* R1 - Power Management (1) */
  39. { 2, 0x6000 }, /* R2 - Power Management (2) */
  40. { 3, 0x0000 }, /* R3 - Power Management (3) */
  41. { 4, 0x4050 }, /* R4 - Audio Interface (1) */
  42. { 5, 0x4000 }, /* R5 - Audio Interface (2) */
  43. { 6, 0x01C8 }, /* R6 - Clocking 1 */
  44. { 7, 0x0000 }, /* R7 - Clocking 2 */
  45. { 8, 0x0000 }, /* R8 - Audio Interface (3) */
  46. { 9, 0x0040 }, /* R9 - Audio Interface (4) */
  47. { 10, 0x0004 }, /* R10 - DAC CTRL */
  48. { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
  49. { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
  50. { 13, 0x0000 }, /* R13 - Digital Side Tone */
  51. { 14, 0x0300 }, /* R14 - ADC CTRL */
  52. { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
  53. { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
  54. { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
  55. { 19, 0x0010 }, /* R19 - GPIO1 */
  56. { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */
  57. { 21, 0x0000 }, /* R21 - Inputs Clamp */
  58. { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
  59. { 23, 0x0800 }, /* R23 - GPIO_POL */
  60. { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
  61. { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
  62. { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
  63. { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
  64. { 28, 0x006D }, /* R28 - Left Output Volume */
  65. { 29, 0x006D }, /* R29 - Right Output Volume */
  66. { 30, 0x0066 }, /* R30 - Line Outputs Volume */
  67. { 31, 0x0020 }, /* R31 - HPOUT2 Volume */
  68. { 32, 0x0079 }, /* R32 - Left OPGA Volume */
  69. { 33, 0x0079 }, /* R33 - Right OPGA Volume */
  70. { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */
  71. { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */
  72. { 36, 0x0011 }, /* R36 - SPKOUT Mixers */
  73. { 37, 0x0100 }, /* R37 - SPKOUT Boost */
  74. { 38, 0x0079 }, /* R38 - Speaker Volume Left */
  75. { 39, 0x0079 }, /* R39 - Speaker Volume Right */
  76. { 40, 0x0000 }, /* R40 - Input Mixer2 */
  77. { 41, 0x0000 }, /* R41 - Input Mixer3 */
  78. { 42, 0x0000 }, /* R42 - Input Mixer4 */
  79. { 43, 0x0000 }, /* R43 - Input Mixer5 */
  80. { 44, 0x0000 }, /* R44 - Input Mixer6 */
  81. { 45, 0x0000 }, /* R45 - Output Mixer1 */
  82. { 46, 0x0000 }, /* R46 - Output Mixer2 */
  83. { 47, 0x0000 }, /* R47 - Output Mixer3 */
  84. { 48, 0x0000 }, /* R48 - Output Mixer4 */
  85. { 49, 0x0000 }, /* R49 - Output Mixer5 */
  86. { 50, 0x0000 }, /* R50 - Output Mixer6 */
  87. { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */
  88. { 52, 0x0000 }, /* R52 - Line Mixer1 */
  89. { 53, 0x0000 }, /* R53 - Line Mixer2 */
  90. { 54, 0x0000 }, /* R54 - Speaker Mixer */
  91. { 55, 0x0000 }, /* R55 - Additional Control */
  92. { 56, 0x0000 }, /* R56 - AntiPOP1 */
  93. { 57, 0x0000 }, /* R57 - AntiPOP2 */
  94. { 58, 0x0000 }, /* R58 - MICBIAS */
  95. { 60, 0x0000 }, /* R60 - FLL Control 1 */
  96. { 61, 0x0000 }, /* R61 - FLL Control 2 */
  97. { 62, 0x0000 }, /* R62 - FLL Control 3 */
  98. { 63, 0x2EE0 }, /* R63 - FLL Control 4 */
  99. { 64, 0x0002 }, /* R64 - FLL Control 5 */
  100. { 65, 0x2287 }, /* R65 - Clocking 3 */
  101. { 66, 0x025F }, /* R66 - Clocking 4 */
  102. { 67, 0x0000 }, /* R67 - MW Slave Control */
  103. { 69, 0x0002 }, /* R69 - Bus Control 1 */
  104. { 70, 0x0000 }, /* R70 - Write Sequencer 0 */
  105. { 71, 0x0000 }, /* R71 - Write Sequencer 1 */
  106. { 72, 0x0000 }, /* R72 - Write Sequencer 2 */
  107. { 73, 0x0000 }, /* R73 - Write Sequencer 3 */
  108. { 74, 0x0000 }, /* R74 - Write Sequencer 4 */
  109. { 75, 0x0000 }, /* R75 - Write Sequencer 5 */
  110. { 76, 0x1F25 }, /* R76 - Charge Pump 1 */
  111. { 81, 0x0000 }, /* R81 - Class W 0 */
  112. { 85, 0x054A }, /* R85 - DC Servo 1 */
  113. { 87, 0x0000 }, /* R87 - DC Servo 3 */
  114. { 96, 0x0100 }, /* R96 - Analogue HP 0 */
  115. { 98, 0x0000 }, /* R98 - EQ1 */
  116. { 99, 0x000C }, /* R99 - EQ2 */
  117. { 100, 0x000C }, /* R100 - EQ3 */
  118. { 101, 0x000C }, /* R101 - EQ4 */
  119. { 102, 0x000C }, /* R102 - EQ5 */
  120. { 103, 0x000C }, /* R103 - EQ6 */
  121. { 104, 0x0FCA }, /* R104 - EQ7 */
  122. { 105, 0x0400 }, /* R105 - EQ8 */
  123. { 106, 0x00D8 }, /* R106 - EQ9 */
  124. { 107, 0x1EB5 }, /* R107 - EQ10 */
  125. { 108, 0xF145 }, /* R108 - EQ11 */
  126. { 109, 0x0B75 }, /* R109 - EQ12 */
  127. { 110, 0x01C5 }, /* R110 - EQ13 */
  128. { 111, 0x1C58 }, /* R111 - EQ14 */
  129. { 112, 0xF373 }, /* R112 - EQ15 */
  130. { 113, 0x0A54 }, /* R113 - EQ16 */
  131. { 114, 0x0558 }, /* R114 - EQ17 */
  132. { 115, 0x168E }, /* R115 - EQ18 */
  133. { 116, 0xF829 }, /* R116 - EQ19 */
  134. { 117, 0x07AD }, /* R117 - EQ20 */
  135. { 118, 0x1103 }, /* R118 - EQ21 */
  136. { 119, 0x0564 }, /* R119 - EQ22 */
  137. { 120, 0x0559 }, /* R120 - EQ23 */
  138. { 121, 0x4000 }, /* R121 - EQ24 */
  139. { 122, 0x0000 }, /* R122 - Digital Pulls */
  140. { 123, 0x0F08 }, /* R123 - DRC Control 1 */
  141. { 124, 0x0000 }, /* R124 - DRC Control 2 */
  142. { 125, 0x0080 }, /* R125 - DRC Control 3 */
  143. { 126, 0x0000 }, /* R126 - DRC Control 4 */
  144. };
  145. static struct {
  146. int ratio;
  147. int clk_sys_rate;
  148. } clk_sys_rates[] = {
  149. { 64, 0 },
  150. { 128, 1 },
  151. { 192, 2 },
  152. { 256, 3 },
  153. { 384, 4 },
  154. { 512, 5 },
  155. { 768, 6 },
  156. { 1024, 7 },
  157. { 1408, 8 },
  158. { 1536, 9 },
  159. };
  160. static struct {
  161. int rate;
  162. int sample_rate;
  163. } sample_rates[] = {
  164. { 8000, 0 },
  165. { 11025, 1 },
  166. { 12000, 1 },
  167. { 16000, 2 },
  168. { 22050, 3 },
  169. { 24000, 3 },
  170. { 32000, 4 },
  171. { 44100, 5 },
  172. { 48000, 5 },
  173. };
  174. static struct {
  175. int div; /* *10 due to .5s */
  176. int bclk_div;
  177. } bclk_divs[] = {
  178. { 10, 0 },
  179. { 15, 1 },
  180. { 20, 2 },
  181. { 30, 3 },
  182. { 40, 4 },
  183. { 55, 5 },
  184. { 60, 6 },
  185. { 80, 7 },
  186. { 110, 8 },
  187. { 120, 9 },
  188. { 160, 10 },
  189. { 220, 11 },
  190. { 240, 12 },
  191. { 320, 13 },
  192. { 440, 14 },
  193. { 480, 15 },
  194. };
  195. struct wm8993_priv {
  196. struct wm_hubs_data hubs_data;
  197. struct device *dev;
  198. struct regmap *regmap;
  199. struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
  200. struct wm8993_platform_data pdata;
  201. struct completion fll_lock;
  202. int master;
  203. int sysclk_source;
  204. int tdm_slots;
  205. int tdm_width;
  206. unsigned int mclk_rate;
  207. unsigned int sysclk_rate;
  208. unsigned int fs;
  209. unsigned int bclk;
  210. unsigned int fll_fref;
  211. unsigned int fll_fout;
  212. int fll_src;
  213. };
  214. static bool wm8993_volatile(struct device *dev, unsigned int reg)
  215. {
  216. switch (reg) {
  217. case WM8993_SOFTWARE_RESET:
  218. case WM8993_GPIO_CTRL_1:
  219. case WM8993_DC_SERVO_0:
  220. case WM8993_DC_SERVO_READBACK_0:
  221. case WM8993_DC_SERVO_READBACK_1:
  222. case WM8993_DC_SERVO_READBACK_2:
  223. return true;
  224. default:
  225. return false;
  226. }
  227. }
  228. static bool wm8993_readable(struct device *dev, unsigned int reg)
  229. {
  230. switch (reg) {
  231. case WM8993_SOFTWARE_RESET:
  232. case WM8993_POWER_MANAGEMENT_1:
  233. case WM8993_POWER_MANAGEMENT_2:
  234. case WM8993_POWER_MANAGEMENT_3:
  235. case WM8993_AUDIO_INTERFACE_1:
  236. case WM8993_AUDIO_INTERFACE_2:
  237. case WM8993_CLOCKING_1:
  238. case WM8993_CLOCKING_2:
  239. case WM8993_AUDIO_INTERFACE_3:
  240. case WM8993_AUDIO_INTERFACE_4:
  241. case WM8993_DAC_CTRL:
  242. case WM8993_LEFT_DAC_DIGITAL_VOLUME:
  243. case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
  244. case WM8993_DIGITAL_SIDE_TONE:
  245. case WM8993_ADC_CTRL:
  246. case WM8993_LEFT_ADC_DIGITAL_VOLUME:
  247. case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
  248. case WM8993_GPIO_CTRL_1:
  249. case WM8993_GPIO1:
  250. case WM8993_IRQ_DEBOUNCE:
  251. case WM8993_GPIOCTRL_2:
  252. case WM8993_GPIO_POL:
  253. case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
  254. case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
  255. case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
  256. case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
  257. case WM8993_LEFT_OUTPUT_VOLUME:
  258. case WM8993_RIGHT_OUTPUT_VOLUME:
  259. case WM8993_LINE_OUTPUTS_VOLUME:
  260. case WM8993_HPOUT2_VOLUME:
  261. case WM8993_LEFT_OPGA_VOLUME:
  262. case WM8993_RIGHT_OPGA_VOLUME:
  263. case WM8993_SPKMIXL_ATTENUATION:
  264. case WM8993_SPKMIXR_ATTENUATION:
  265. case WM8993_SPKOUT_MIXERS:
  266. case WM8993_SPKOUT_BOOST:
  267. case WM8993_SPEAKER_VOLUME_LEFT:
  268. case WM8993_SPEAKER_VOLUME_RIGHT:
  269. case WM8993_INPUT_MIXER2:
  270. case WM8993_INPUT_MIXER3:
  271. case WM8993_INPUT_MIXER4:
  272. case WM8993_INPUT_MIXER5:
  273. case WM8993_INPUT_MIXER6:
  274. case WM8993_OUTPUT_MIXER1:
  275. case WM8993_OUTPUT_MIXER2:
  276. case WM8993_OUTPUT_MIXER3:
  277. case WM8993_OUTPUT_MIXER4:
  278. case WM8993_OUTPUT_MIXER5:
  279. case WM8993_OUTPUT_MIXER6:
  280. case WM8993_HPOUT2_MIXER:
  281. case WM8993_LINE_MIXER1:
  282. case WM8993_LINE_MIXER2:
  283. case WM8993_SPEAKER_MIXER:
  284. case WM8993_ADDITIONAL_CONTROL:
  285. case WM8993_ANTIPOP1:
  286. case WM8993_ANTIPOP2:
  287. case WM8993_MICBIAS:
  288. case WM8993_FLL_CONTROL_1:
  289. case WM8993_FLL_CONTROL_2:
  290. case WM8993_FLL_CONTROL_3:
  291. case WM8993_FLL_CONTROL_4:
  292. case WM8993_FLL_CONTROL_5:
  293. case WM8993_CLOCKING_3:
  294. case WM8993_CLOCKING_4:
  295. case WM8993_MW_SLAVE_CONTROL:
  296. case WM8993_BUS_CONTROL_1:
  297. case WM8993_WRITE_SEQUENCER_0:
  298. case WM8993_WRITE_SEQUENCER_1:
  299. case WM8993_WRITE_SEQUENCER_2:
  300. case WM8993_WRITE_SEQUENCER_3:
  301. case WM8993_WRITE_SEQUENCER_4:
  302. case WM8993_WRITE_SEQUENCER_5:
  303. case WM8993_CHARGE_PUMP_1:
  304. case WM8993_CLASS_W_0:
  305. case WM8993_DC_SERVO_0:
  306. case WM8993_DC_SERVO_1:
  307. case WM8993_DC_SERVO_3:
  308. case WM8993_DC_SERVO_READBACK_0:
  309. case WM8993_DC_SERVO_READBACK_1:
  310. case WM8993_DC_SERVO_READBACK_2:
  311. case WM8993_ANALOGUE_HP_0:
  312. case WM8993_EQ1:
  313. case WM8993_EQ2:
  314. case WM8993_EQ3:
  315. case WM8993_EQ4:
  316. case WM8993_EQ5:
  317. case WM8993_EQ6:
  318. case WM8993_EQ7:
  319. case WM8993_EQ8:
  320. case WM8993_EQ9:
  321. case WM8993_EQ10:
  322. case WM8993_EQ11:
  323. case WM8993_EQ12:
  324. case WM8993_EQ13:
  325. case WM8993_EQ14:
  326. case WM8993_EQ15:
  327. case WM8993_EQ16:
  328. case WM8993_EQ17:
  329. case WM8993_EQ18:
  330. case WM8993_EQ19:
  331. case WM8993_EQ20:
  332. case WM8993_EQ21:
  333. case WM8993_EQ22:
  334. case WM8993_EQ23:
  335. case WM8993_EQ24:
  336. case WM8993_DIGITAL_PULLS:
  337. case WM8993_DRC_CONTROL_1:
  338. case WM8993_DRC_CONTROL_2:
  339. case WM8993_DRC_CONTROL_3:
  340. case WM8993_DRC_CONTROL_4:
  341. return true;
  342. default:
  343. return false;
  344. }
  345. }
  346. struct _fll_div {
  347. u16 fll_fratio;
  348. u16 fll_outdiv;
  349. u16 fll_clk_ref_div;
  350. u16 n;
  351. u16 k;
  352. };
  353. /* The size in bits of the FLL divide multiplied by 10
  354. * to allow rounding later */
  355. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  356. static struct {
  357. unsigned int min;
  358. unsigned int max;
  359. u16 fll_fratio;
  360. int ratio;
  361. } fll_fratios[] = {
  362. { 0, 64000, 4, 16 },
  363. { 64000, 128000, 3, 8 },
  364. { 128000, 256000, 2, 4 },
  365. { 256000, 1000000, 1, 2 },
  366. { 1000000, 13500000, 0, 1 },
  367. };
  368. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  369. unsigned int Fout)
  370. {
  371. u64 Kpart;
  372. unsigned int K, Ndiv, Nmod, target;
  373. unsigned int div;
  374. int i;
  375. /* Fref must be <=13.5MHz */
  376. div = 1;
  377. fll_div->fll_clk_ref_div = 0;
  378. while ((Fref / div) > 13500000) {
  379. div *= 2;
  380. fll_div->fll_clk_ref_div++;
  381. if (div > 8) {
  382. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  383. Fref);
  384. return -EINVAL;
  385. }
  386. }
  387. pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
  388. /* Apply the division for our remaining calculations */
  389. Fref /= div;
  390. /* Fvco should be 90-100MHz; don't check the upper bound */
  391. div = 0;
  392. target = Fout * 2;
  393. while (target < 90000000) {
  394. div++;
  395. target *= 2;
  396. if (div > 7) {
  397. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  398. Fout);
  399. return -EINVAL;
  400. }
  401. }
  402. fll_div->fll_outdiv = div;
  403. pr_debug("Fvco=%dHz\n", target);
  404. /* Find an appropriate FLL_FRATIO and factor it out of the target */
  405. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  406. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  407. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  408. target /= fll_fratios[i].ratio;
  409. break;
  410. }
  411. }
  412. if (i == ARRAY_SIZE(fll_fratios)) {
  413. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  414. return -EINVAL;
  415. }
  416. /* Now, calculate N.K */
  417. Ndiv = target / Fref;
  418. fll_div->n = Ndiv;
  419. Nmod = target % Fref;
  420. pr_debug("Nmod=%d\n", Nmod);
  421. /* Calculate fractional part - scale up so we can round. */
  422. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  423. do_div(Kpart, Fref);
  424. K = Kpart & 0xFFFFFFFF;
  425. if ((K % 10) >= 5)
  426. K += 5;
  427. /* Move down to proper range now rounding is done */
  428. fll_div->k = K / 10;
  429. pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
  430. fll_div->n, fll_div->k,
  431. fll_div->fll_fratio, fll_div->fll_outdiv,
  432. fll_div->fll_clk_ref_div);
  433. return 0;
  434. }
  435. static int _wm8993_set_fll(struct snd_soc_component *component, int fll_id, int source,
  436. unsigned int Fref, unsigned int Fout)
  437. {
  438. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  439. struct i2c_client *i2c = to_i2c_client(component->dev);
  440. u16 reg1, reg4, reg5;
  441. struct _fll_div fll_div;
  442. unsigned int timeout;
  443. int ret;
  444. /* Any change? */
  445. if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
  446. return 0;
  447. /* Disable the FLL */
  448. if (Fout == 0) {
  449. dev_dbg(component->dev, "FLL disabled\n");
  450. wm8993->fll_fref = 0;
  451. wm8993->fll_fout = 0;
  452. reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
  453. reg1 &= ~WM8993_FLL_ENA;
  454. snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
  455. return 0;
  456. }
  457. ret = fll_factors(&fll_div, Fref, Fout);
  458. if (ret != 0)
  459. return ret;
  460. reg5 = snd_soc_component_read(component, WM8993_FLL_CONTROL_5);
  461. reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
  462. switch (fll_id) {
  463. case WM8993_FLL_MCLK:
  464. break;
  465. case WM8993_FLL_LRCLK:
  466. reg5 |= 1;
  467. break;
  468. case WM8993_FLL_BCLK:
  469. reg5 |= 2;
  470. break;
  471. default:
  472. dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
  473. return -EINVAL;
  474. }
  475. /* Any FLL configuration change requires that the FLL be
  476. * disabled first. */
  477. reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
  478. reg1 &= ~WM8993_FLL_ENA;
  479. snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
  480. /* Apply the configuration */
  481. if (fll_div.k)
  482. reg1 |= WM8993_FLL_FRAC_MASK;
  483. else
  484. reg1 &= ~WM8993_FLL_FRAC_MASK;
  485. snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
  486. snd_soc_component_write(component, WM8993_FLL_CONTROL_2,
  487. (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
  488. (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
  489. snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k);
  490. reg4 = snd_soc_component_read(component, WM8993_FLL_CONTROL_4);
  491. reg4 &= ~WM8993_FLL_N_MASK;
  492. reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
  493. snd_soc_component_write(component, WM8993_FLL_CONTROL_4, reg4);
  494. reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
  495. reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
  496. snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5);
  497. /* If we've got an interrupt wired up make sure we get it */
  498. if (i2c->irq)
  499. timeout = msecs_to_jiffies(20);
  500. else if (Fref < 1000000)
  501. timeout = msecs_to_jiffies(3);
  502. else
  503. timeout = msecs_to_jiffies(1);
  504. try_wait_for_completion(&wm8993->fll_lock);
  505. /* Enable the FLL */
  506. snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
  507. timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout);
  508. if (i2c->irq && !timeout)
  509. dev_warn(component->dev, "Timed out waiting for FLL\n");
  510. dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
  511. wm8993->fll_fref = Fref;
  512. wm8993->fll_fout = Fout;
  513. wm8993->fll_src = source;
  514. return 0;
  515. }
  516. static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  517. unsigned int Fref, unsigned int Fout)
  518. {
  519. return _wm8993_set_fll(dai->component, fll_id, source, Fref, Fout);
  520. }
  521. static int configure_clock(struct snd_soc_component *component)
  522. {
  523. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  524. unsigned int reg;
  525. /* This should be done on init() for bypass paths */
  526. switch (wm8993->sysclk_source) {
  527. case WM8993_SYSCLK_MCLK:
  528. dev_dbg(component->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
  529. reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
  530. reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
  531. if (wm8993->mclk_rate > 13500000) {
  532. reg |= WM8993_MCLK_DIV;
  533. wm8993->sysclk_rate = wm8993->mclk_rate / 2;
  534. } else {
  535. reg &= ~WM8993_MCLK_DIV;
  536. wm8993->sysclk_rate = wm8993->mclk_rate;
  537. }
  538. snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
  539. break;
  540. case WM8993_SYSCLK_FLL:
  541. dev_dbg(component->dev, "Using %dHz FLL clock\n",
  542. wm8993->fll_fout);
  543. reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
  544. reg |= WM8993_SYSCLK_SRC;
  545. if (wm8993->fll_fout > 13500000) {
  546. reg |= WM8993_MCLK_DIV;
  547. wm8993->sysclk_rate = wm8993->fll_fout / 2;
  548. } else {
  549. reg &= ~WM8993_MCLK_DIV;
  550. wm8993->sysclk_rate = wm8993->fll_fout;
  551. }
  552. snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
  553. break;
  554. default:
  555. dev_err(component->dev, "System clock not configured\n");
  556. return -EINVAL;
  557. }
  558. dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
  559. return 0;
  560. }
  561. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  562. static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
  563. static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
  564. static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
  565. static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
  566. 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
  567. 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
  568. );
  569. static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
  570. static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
  571. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  572. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  573. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  574. static const char *dac_deemph_text[] = {
  575. "None",
  576. "32kHz",
  577. "44.1kHz",
  578. "48kHz",
  579. };
  580. static SOC_ENUM_SINGLE_DECL(dac_deemph,
  581. WM8993_DAC_CTRL, 4, dac_deemph_text);
  582. static const char *adc_hpf_text[] = {
  583. "Hi-Fi",
  584. "Voice 1",
  585. "Voice 2",
  586. "Voice 3",
  587. };
  588. static SOC_ENUM_SINGLE_DECL(adc_hpf,
  589. WM8993_ADC_CTRL, 5, adc_hpf_text);
  590. static const char *drc_path_text[] = {
  591. "ADC",
  592. "DAC"
  593. };
  594. static SOC_ENUM_SINGLE_DECL(drc_path,
  595. WM8993_DRC_CONTROL_1, 14, drc_path_text);
  596. static const char *drc_r0_text[] = {
  597. "1",
  598. "1/2",
  599. "1/4",
  600. "1/8",
  601. "1/16",
  602. "0",
  603. };
  604. static SOC_ENUM_SINGLE_DECL(drc_r0,
  605. WM8993_DRC_CONTROL_3, 8, drc_r0_text);
  606. static const char *drc_r1_text[] = {
  607. "1",
  608. "1/2",
  609. "1/4",
  610. "1/8",
  611. "0",
  612. };
  613. static SOC_ENUM_SINGLE_DECL(drc_r1,
  614. WM8993_DRC_CONTROL_4, 13, drc_r1_text);
  615. static const char *drc_attack_text[] = {
  616. "Reserved",
  617. "181us",
  618. "363us",
  619. "726us",
  620. "1.45ms",
  621. "2.9ms",
  622. "5.8ms",
  623. "11.6ms",
  624. "23.2ms",
  625. "46.4ms",
  626. "92.8ms",
  627. "185.6ms",
  628. };
  629. static SOC_ENUM_SINGLE_DECL(drc_attack,
  630. WM8993_DRC_CONTROL_2, 12, drc_attack_text);
  631. static const char *drc_decay_text[] = {
  632. "186ms",
  633. "372ms",
  634. "743ms",
  635. "1.49s",
  636. "2.97ms",
  637. "5.94ms",
  638. "11.89ms",
  639. "23.78ms",
  640. "47.56ms",
  641. };
  642. static SOC_ENUM_SINGLE_DECL(drc_decay,
  643. WM8993_DRC_CONTROL_2, 8, drc_decay_text);
  644. static const char *drc_ff_text[] = {
  645. "5 samples",
  646. "9 samples",
  647. };
  648. static SOC_ENUM_SINGLE_DECL(drc_ff,
  649. WM8993_DRC_CONTROL_3, 7, drc_ff_text);
  650. static const char *drc_qr_rate_text[] = {
  651. "0.725ms",
  652. "1.45ms",
  653. "5.8ms",
  654. };
  655. static SOC_ENUM_SINGLE_DECL(drc_qr_rate,
  656. WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text);
  657. static const char *drc_smooth_text[] = {
  658. "Low",
  659. "Medium",
  660. "High",
  661. };
  662. static SOC_ENUM_SINGLE_DECL(drc_smooth,
  663. WM8993_DRC_CONTROL_1, 4, drc_smooth_text);
  664. static const struct snd_kcontrol_new wm8993_snd_controls[] = {
  665. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
  666. 5, 9, 12, 0, sidetone_tlv),
  667. SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
  668. SOC_ENUM("DRC Path", drc_path),
  669. SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
  670. 2, 60, 1, drc_comp_threash),
  671. SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
  672. 11, 30, 1, drc_comp_amp),
  673. SOC_ENUM("DRC R0", drc_r0),
  674. SOC_ENUM("DRC R1", drc_r1),
  675. SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
  676. drc_min_tlv),
  677. SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
  678. drc_max_tlv),
  679. SOC_ENUM("DRC Attack Rate", drc_attack),
  680. SOC_ENUM("DRC Decay Rate", drc_decay),
  681. SOC_ENUM("DRC FF Delay", drc_ff),
  682. SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
  683. SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
  684. SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
  685. drc_qr_tlv),
  686. SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
  687. SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
  688. SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
  689. SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
  690. SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
  691. drc_startup_tlv),
  692. SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
  693. SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
  694. WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
  695. SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
  696. SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
  697. SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
  698. WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
  699. SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
  700. dac_boost_tlv),
  701. SOC_ENUM("DAC Deemphasis", dac_deemph),
  702. SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
  703. 2, 1, 1, wm_hubs_spkmix_tlv),
  704. SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
  705. 2, 1, 1, wm_hubs_spkmix_tlv),
  706. };
  707. static const struct snd_kcontrol_new wm8993_eq_controls[] = {
  708. SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
  709. SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
  710. SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
  711. SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
  712. SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
  713. };
  714. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  715. struct snd_kcontrol *kcontrol, int event)
  716. {
  717. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  718. switch (event) {
  719. case SND_SOC_DAPM_PRE_PMU:
  720. return configure_clock(component);
  721. case SND_SOC_DAPM_POST_PMD:
  722. break;
  723. }
  724. return 0;
  725. }
  726. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  727. SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
  728. SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
  729. SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
  730. SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
  731. };
  732. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  733. SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
  734. SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
  735. SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
  736. SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
  737. };
  738. static const char *aif_text[] = {
  739. "Left", "Right"
  740. };
  741. static SOC_ENUM_SINGLE_DECL(aifoutl_enum,
  742. WM8993_AUDIO_INTERFACE_1, 15, aif_text);
  743. static const struct snd_kcontrol_new aifoutl_mux =
  744. SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
  745. static SOC_ENUM_SINGLE_DECL(aifoutr_enum,
  746. WM8993_AUDIO_INTERFACE_1, 14, aif_text);
  747. static const struct snd_kcontrol_new aifoutr_mux =
  748. SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
  749. static SOC_ENUM_SINGLE_DECL(aifinl_enum,
  750. WM8993_AUDIO_INTERFACE_2, 15, aif_text);
  751. static const struct snd_kcontrol_new aifinl_mux =
  752. SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
  753. static SOC_ENUM_SINGLE_DECL(aifinr_enum,
  754. WM8993_AUDIO_INTERFACE_2, 14, aif_text);
  755. static const struct snd_kcontrol_new aifinr_mux =
  756. SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
  757. static const char *sidetone_text[] = {
  758. "None", "Left", "Right"
  759. };
  760. static SOC_ENUM_SINGLE_DECL(sidetonel_enum,
  761. WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text);
  762. static const struct snd_kcontrol_new sidetonel_mux =
  763. SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
  764. static SOC_ENUM_SINGLE_DECL(sidetoner_enum,
  765. WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text);
  766. static const struct snd_kcontrol_new sidetoner_mux =
  767. SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
  768. static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
  769. SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
  770. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  771. SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
  772. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
  773. SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
  774. SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
  775. SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
  776. SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
  777. SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
  778. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  779. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  780. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  781. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  782. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
  783. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
  784. SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
  785. SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
  786. SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
  787. SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
  788. SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
  789. SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
  790. SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
  791. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  792. SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
  793. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  794. SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
  795. };
  796. static const struct snd_soc_dapm_route routes[] = {
  797. { "MICBIAS1", NULL, "VMID" },
  798. { "MICBIAS2", NULL, "VMID" },
  799. { "ADCL", NULL, "CLK_SYS" },
  800. { "ADCL", NULL, "CLK_DSP" },
  801. { "ADCR", NULL, "CLK_SYS" },
  802. { "ADCR", NULL, "CLK_DSP" },
  803. { "AIFOUTL Mux", "Left", "ADCL" },
  804. { "AIFOUTL Mux", "Right", "ADCR" },
  805. { "AIFOUTR Mux", "Left", "ADCL" },
  806. { "AIFOUTR Mux", "Right", "ADCR" },
  807. { "AIFOUTL", NULL, "AIFOUTL Mux" },
  808. { "AIFOUTR", NULL, "AIFOUTR Mux" },
  809. { "DACL Mux", "Left", "AIFINL" },
  810. { "DACL Mux", "Right", "AIFINR" },
  811. { "DACR Mux", "Left", "AIFINL" },
  812. { "DACR Mux", "Right", "AIFINR" },
  813. { "DACL Sidetone", "Left", "ADCL" },
  814. { "DACL Sidetone", "Right", "ADCR" },
  815. { "DACR Sidetone", "Left", "ADCL" },
  816. { "DACR Sidetone", "Right", "ADCR" },
  817. { "DACL", NULL, "CLK_SYS" },
  818. { "DACL", NULL, "CLK_DSP" },
  819. { "DACL", NULL, "DACL Mux" },
  820. { "DACL", NULL, "DACL Sidetone" },
  821. { "DACR", NULL, "CLK_SYS" },
  822. { "DACR", NULL, "CLK_DSP" },
  823. { "DACR", NULL, "DACR Mux" },
  824. { "DACR", NULL, "DACR Sidetone" },
  825. { "Left Output Mixer", "DAC Switch", "DACL" },
  826. { "Right Output Mixer", "DAC Switch", "DACR" },
  827. { "Left Output PGA", NULL, "CLK_SYS" },
  828. { "Right Output PGA", NULL, "CLK_SYS" },
  829. { "SPKL", "DAC Switch", "DACL" },
  830. { "SPKL", NULL, "CLK_SYS" },
  831. { "SPKR", "DAC Switch", "DACR" },
  832. { "SPKR", NULL, "CLK_SYS" },
  833. { "Left Headphone Mux", "DAC", "DACL" },
  834. { "Right Headphone Mux", "DAC", "DACR" },
  835. };
  836. static int wm8993_set_bias_level(struct snd_soc_component *component,
  837. enum snd_soc_bias_level level)
  838. {
  839. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  840. int ret;
  841. wm_hubs_set_bias_level(component, level);
  842. switch (level) {
  843. case SND_SOC_BIAS_ON:
  844. case SND_SOC_BIAS_PREPARE:
  845. /* VMID=2*40k */
  846. snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
  847. WM8993_VMID_SEL_MASK, 0x2);
  848. snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
  849. WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
  850. break;
  851. case SND_SOC_BIAS_STANDBY:
  852. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  853. ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
  854. wm8993->supplies);
  855. if (ret != 0)
  856. return ret;
  857. regcache_cache_only(wm8993->regmap, false);
  858. regcache_sync(wm8993->regmap);
  859. wm_hubs_vmid_ena(component);
  860. /* Bring up VMID with fast soft start */
  861. snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
  862. WM8993_STARTUP_BIAS_ENA |
  863. WM8993_VMID_BUF_ENA |
  864. WM8993_VMID_RAMP_MASK |
  865. WM8993_BIAS_SRC,
  866. WM8993_STARTUP_BIAS_ENA |
  867. WM8993_VMID_BUF_ENA |
  868. WM8993_VMID_RAMP_MASK |
  869. WM8993_BIAS_SRC);
  870. /* If either line output is single ended we
  871. * need the VMID buffer */
  872. if (!wm8993->pdata.lineout1_diff ||
  873. !wm8993->pdata.lineout2_diff)
  874. snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
  875. WM8993_LINEOUT_VMID_BUF_ENA,
  876. WM8993_LINEOUT_VMID_BUF_ENA);
  877. /* VMID=2*40k */
  878. snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
  879. WM8993_VMID_SEL_MASK |
  880. WM8993_BIAS_ENA,
  881. WM8993_BIAS_ENA | 0x2);
  882. msleep(32);
  883. /* Switch to normal bias */
  884. snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
  885. WM8993_BIAS_SRC |
  886. WM8993_STARTUP_BIAS_ENA, 0);
  887. }
  888. /* VMID=2*240k */
  889. snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
  890. WM8993_VMID_SEL_MASK, 0x4);
  891. snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
  892. WM8993_TSHUT_ENA, 0);
  893. break;
  894. case SND_SOC_BIAS_OFF:
  895. snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
  896. WM8993_LINEOUT_VMID_BUF_ENA, 0);
  897. snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
  898. WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
  899. 0);
  900. snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
  901. WM8993_STARTUP_BIAS_ENA |
  902. WM8993_VMID_BUF_ENA |
  903. WM8993_VMID_RAMP_MASK |
  904. WM8993_BIAS_SRC, 0);
  905. regcache_cache_only(wm8993->regmap, true);
  906. regcache_mark_dirty(wm8993->regmap);
  907. regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
  908. wm8993->supplies);
  909. break;
  910. }
  911. return 0;
  912. }
  913. static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
  914. int clk_id, unsigned int freq, int dir)
  915. {
  916. struct snd_soc_component *component = codec_dai->component;
  917. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  918. switch (clk_id) {
  919. case WM8993_SYSCLK_MCLK:
  920. wm8993->mclk_rate = freq;
  921. fallthrough;
  922. case WM8993_SYSCLK_FLL:
  923. wm8993->sysclk_source = clk_id;
  924. break;
  925. default:
  926. return -EINVAL;
  927. }
  928. return 0;
  929. }
  930. static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
  931. unsigned int fmt)
  932. {
  933. struct snd_soc_component *component = dai->component;
  934. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  935. unsigned int aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
  936. unsigned int aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
  937. aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
  938. WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
  939. aif4 &= ~WM8993_LRCLK_DIR;
  940. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  941. case SND_SOC_DAIFMT_CBS_CFS:
  942. wm8993->master = 0;
  943. break;
  944. case SND_SOC_DAIFMT_CBS_CFM:
  945. aif4 |= WM8993_LRCLK_DIR;
  946. wm8993->master = 1;
  947. break;
  948. case SND_SOC_DAIFMT_CBM_CFS:
  949. aif1 |= WM8993_BCLK_DIR;
  950. wm8993->master = 1;
  951. break;
  952. case SND_SOC_DAIFMT_CBM_CFM:
  953. aif1 |= WM8993_BCLK_DIR;
  954. aif4 |= WM8993_LRCLK_DIR;
  955. wm8993->master = 1;
  956. break;
  957. default:
  958. return -EINVAL;
  959. }
  960. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  961. case SND_SOC_DAIFMT_DSP_B:
  962. aif1 |= WM8993_AIF_LRCLK_INV;
  963. fallthrough;
  964. case SND_SOC_DAIFMT_DSP_A:
  965. aif1 |= 0x18;
  966. break;
  967. case SND_SOC_DAIFMT_I2S:
  968. aif1 |= 0x10;
  969. break;
  970. case SND_SOC_DAIFMT_RIGHT_J:
  971. break;
  972. case SND_SOC_DAIFMT_LEFT_J:
  973. aif1 |= 0x8;
  974. break;
  975. default:
  976. return -EINVAL;
  977. }
  978. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  979. case SND_SOC_DAIFMT_DSP_A:
  980. case SND_SOC_DAIFMT_DSP_B:
  981. /* frame inversion not valid for DSP modes */
  982. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  983. case SND_SOC_DAIFMT_NB_NF:
  984. break;
  985. case SND_SOC_DAIFMT_IB_NF:
  986. aif1 |= WM8993_AIF_BCLK_INV;
  987. break;
  988. default:
  989. return -EINVAL;
  990. }
  991. break;
  992. case SND_SOC_DAIFMT_I2S:
  993. case SND_SOC_DAIFMT_RIGHT_J:
  994. case SND_SOC_DAIFMT_LEFT_J:
  995. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  996. case SND_SOC_DAIFMT_NB_NF:
  997. break;
  998. case SND_SOC_DAIFMT_IB_IF:
  999. aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
  1000. break;
  1001. case SND_SOC_DAIFMT_IB_NF:
  1002. aif1 |= WM8993_AIF_BCLK_INV;
  1003. break;
  1004. case SND_SOC_DAIFMT_NB_IF:
  1005. aif1 |= WM8993_AIF_LRCLK_INV;
  1006. break;
  1007. default:
  1008. return -EINVAL;
  1009. }
  1010. break;
  1011. default:
  1012. return -EINVAL;
  1013. }
  1014. snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
  1015. snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
  1016. return 0;
  1017. }
  1018. static int wm8993_hw_params(struct snd_pcm_substream *substream,
  1019. struct snd_pcm_hw_params *params,
  1020. struct snd_soc_dai *dai)
  1021. {
  1022. struct snd_soc_component *component = dai->component;
  1023. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  1024. int ret, i, best, best_val, cur_val;
  1025. unsigned int clocking1, clocking3, aif1, aif4;
  1026. clocking1 = snd_soc_component_read(component, WM8993_CLOCKING_1);
  1027. clocking1 &= ~WM8993_BCLK_DIV_MASK;
  1028. clocking3 = snd_soc_component_read(component, WM8993_CLOCKING_3);
  1029. clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
  1030. aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
  1031. aif1 &= ~WM8993_AIF_WL_MASK;
  1032. aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
  1033. aif4 &= ~WM8993_LRCLK_RATE_MASK;
  1034. /* What BCLK do we need? */
  1035. wm8993->fs = params_rate(params);
  1036. wm8993->bclk = 2 * wm8993->fs;
  1037. if (wm8993->tdm_slots) {
  1038. dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
  1039. wm8993->tdm_slots, wm8993->tdm_width);
  1040. wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
  1041. } else {
  1042. switch (params_width(params)) {
  1043. case 16:
  1044. wm8993->bclk *= 16;
  1045. break;
  1046. case 20:
  1047. wm8993->bclk *= 20;
  1048. aif1 |= 0x8;
  1049. break;
  1050. case 24:
  1051. wm8993->bclk *= 24;
  1052. aif1 |= 0x10;
  1053. break;
  1054. case 32:
  1055. wm8993->bclk *= 32;
  1056. aif1 |= 0x18;
  1057. break;
  1058. default:
  1059. return -EINVAL;
  1060. }
  1061. }
  1062. dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8993->bclk);
  1063. ret = configure_clock(component);
  1064. if (ret != 0)
  1065. return ret;
  1066. /* Select nearest CLK_SYS_RATE */
  1067. best = 0;
  1068. best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
  1069. - wm8993->fs);
  1070. for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
  1071. cur_val = abs((wm8993->sysclk_rate /
  1072. clk_sys_rates[i].ratio) - wm8993->fs);
  1073. if (cur_val < best_val) {
  1074. best = i;
  1075. best_val = cur_val;
  1076. }
  1077. }
  1078. dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
  1079. clk_sys_rates[best].ratio);
  1080. clocking3 |= (clk_sys_rates[best].clk_sys_rate
  1081. << WM8993_CLK_SYS_RATE_SHIFT);
  1082. /* SAMPLE_RATE */
  1083. best = 0;
  1084. best_val = abs(wm8993->fs - sample_rates[0].rate);
  1085. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1086. /* Closest match */
  1087. cur_val = abs(wm8993->fs - sample_rates[i].rate);
  1088. if (cur_val < best_val) {
  1089. best = i;
  1090. best_val = cur_val;
  1091. }
  1092. }
  1093. dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
  1094. sample_rates[best].rate);
  1095. clocking3 |= (sample_rates[best].sample_rate
  1096. << WM8993_SAMPLE_RATE_SHIFT);
  1097. /* BCLK_DIV */
  1098. best = 0;
  1099. best_val = INT_MAX;
  1100. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1101. cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
  1102. - wm8993->bclk;
  1103. if (cur_val < 0) /* Table is sorted */
  1104. break;
  1105. if (cur_val < best_val) {
  1106. best = i;
  1107. best_val = cur_val;
  1108. }
  1109. }
  1110. wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
  1111. dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
  1112. bclk_divs[best].div, wm8993->bclk);
  1113. clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
  1114. /* LRCLK is a simple fraction of BCLK */
  1115. dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
  1116. aif4 |= wm8993->bclk / wm8993->fs;
  1117. snd_soc_component_write(component, WM8993_CLOCKING_1, clocking1);
  1118. snd_soc_component_write(component, WM8993_CLOCKING_3, clocking3);
  1119. snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
  1120. snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
  1121. /* ReTune Mobile? */
  1122. if (wm8993->pdata.num_retune_configs) {
  1123. u16 eq1 = snd_soc_component_read(component, WM8993_EQ1);
  1124. struct wm8993_retune_mobile_setting *s;
  1125. best = 0;
  1126. best_val = abs(wm8993->pdata.retune_configs[0].rate
  1127. - wm8993->fs);
  1128. for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
  1129. cur_val = abs(wm8993->pdata.retune_configs[i].rate
  1130. - wm8993->fs);
  1131. if (cur_val < best_val) {
  1132. best_val = cur_val;
  1133. best = i;
  1134. }
  1135. }
  1136. s = &wm8993->pdata.retune_configs[best];
  1137. dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
  1138. s->name, s->rate);
  1139. /* Disable EQ while we reconfigure */
  1140. snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, 0);
  1141. for (i = 1; i < ARRAY_SIZE(s->config); i++)
  1142. snd_soc_component_write(component, WM8993_EQ1 + i, s->config[i]);
  1143. snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, eq1);
  1144. }
  1145. return 0;
  1146. }
  1147. static int wm8993_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  1148. {
  1149. struct snd_soc_component *component = codec_dai->component;
  1150. unsigned int reg;
  1151. reg = snd_soc_component_read(component, WM8993_DAC_CTRL);
  1152. if (mute)
  1153. reg |= WM8993_DAC_MUTE;
  1154. else
  1155. reg &= ~WM8993_DAC_MUTE;
  1156. snd_soc_component_write(component, WM8993_DAC_CTRL, reg);
  1157. return 0;
  1158. }
  1159. static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1160. unsigned int rx_mask, int slots, int slot_width)
  1161. {
  1162. struct snd_soc_component *component = dai->component;
  1163. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  1164. int aif1 = 0;
  1165. int aif2 = 0;
  1166. /* Don't need to validate anything if we're turning off TDM */
  1167. if (slots == 0) {
  1168. wm8993->tdm_slots = 0;
  1169. goto out;
  1170. }
  1171. /* Note that we allow configurations we can't handle ourselves -
  1172. * for example, we can generate clocks for slots 2 and up even if
  1173. * we can't use those slots ourselves.
  1174. */
  1175. aif1 |= WM8993_AIFADC_TDM;
  1176. aif2 |= WM8993_AIFDAC_TDM;
  1177. switch (rx_mask) {
  1178. case 3:
  1179. break;
  1180. case 0xc:
  1181. aif1 |= WM8993_AIFADC_TDM_CHAN;
  1182. break;
  1183. default:
  1184. return -EINVAL;
  1185. }
  1186. switch (tx_mask) {
  1187. case 3:
  1188. break;
  1189. case 0xc:
  1190. aif2 |= WM8993_AIFDAC_TDM_CHAN;
  1191. break;
  1192. default:
  1193. return -EINVAL;
  1194. }
  1195. out:
  1196. wm8993->tdm_width = slot_width;
  1197. wm8993->tdm_slots = slots / 2;
  1198. snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_1,
  1199. WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
  1200. snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_2,
  1201. WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
  1202. return 0;
  1203. }
  1204. static irqreturn_t wm8993_irq(int irq, void *data)
  1205. {
  1206. struct wm8993_priv *wm8993 = data;
  1207. int mask, val, ret;
  1208. ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
  1209. if (ret != 0) {
  1210. dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
  1211. ret);
  1212. return IRQ_NONE;
  1213. }
  1214. ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
  1215. if (ret != 0) {
  1216. dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
  1217. ret);
  1218. return IRQ_NONE;
  1219. }
  1220. /* The IRQ pin status is visible in the register too */
  1221. val &= ~(mask | WM8993_IRQ);
  1222. if (!val)
  1223. return IRQ_NONE;
  1224. if (val & WM8993_TEMPOK_EINT)
  1225. dev_crit(wm8993->dev, "Thermal warning\n");
  1226. if (val & WM8993_FLL_LOCK_EINT) {
  1227. dev_dbg(wm8993->dev, "FLL locked\n");
  1228. complete(&wm8993->fll_lock);
  1229. }
  1230. ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
  1231. if (ret != 0)
  1232. dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
  1233. return IRQ_HANDLED;
  1234. }
  1235. static const struct snd_soc_dai_ops wm8993_ops = {
  1236. .set_sysclk = wm8993_set_sysclk,
  1237. .set_fmt = wm8993_set_dai_fmt,
  1238. .hw_params = wm8993_hw_params,
  1239. .mute_stream = wm8993_mute,
  1240. .set_pll = wm8993_set_fll,
  1241. .set_tdm_slot = wm8993_set_tdm_slot,
  1242. .no_capture_mute = 1,
  1243. };
  1244. #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
  1245. #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1246. SNDRV_PCM_FMTBIT_S20_3LE |\
  1247. SNDRV_PCM_FMTBIT_S24_LE |\
  1248. SNDRV_PCM_FMTBIT_S32_LE)
  1249. static struct snd_soc_dai_driver wm8993_dai = {
  1250. .name = "wm8993-hifi",
  1251. .playback = {
  1252. .stream_name = "Playback",
  1253. .channels_min = 1,
  1254. .channels_max = 2,
  1255. .rates = WM8993_RATES,
  1256. .formats = WM8993_FORMATS,
  1257. .sig_bits = 24,
  1258. },
  1259. .capture = {
  1260. .stream_name = "Capture",
  1261. .channels_min = 1,
  1262. .channels_max = 2,
  1263. .rates = WM8993_RATES,
  1264. .formats = WM8993_FORMATS,
  1265. .sig_bits = 24,
  1266. },
  1267. .ops = &wm8993_ops,
  1268. .symmetric_rates = 1,
  1269. };
  1270. static int wm8993_probe(struct snd_soc_component *component)
  1271. {
  1272. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  1273. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  1274. wm8993->hubs_data.hp_startup_mode = 1;
  1275. wm8993->hubs_data.dcs_codes_l = -2;
  1276. wm8993->hubs_data.dcs_codes_r = -2;
  1277. wm8993->hubs_data.series_startup = 1;
  1278. /* Latch volume update bits and default ZC on */
  1279. snd_soc_component_update_bits(component, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
  1280. WM8993_DAC_VU, WM8993_DAC_VU);
  1281. snd_soc_component_update_bits(component, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
  1282. WM8993_ADC_VU, WM8993_ADC_VU);
  1283. /* Manualy manage the HPOUT sequencing for independent stereo
  1284. * control. */
  1285. snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
  1286. WM8993_HPOUT1_AUTO_PU, 0);
  1287. /* Use automatic clock configuration */
  1288. snd_soc_component_update_bits(component, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
  1289. wm_hubs_handle_analogue_pdata(component, wm8993->pdata.lineout1_diff,
  1290. wm8993->pdata.lineout2_diff,
  1291. wm8993->pdata.lineout1fb,
  1292. wm8993->pdata.lineout2fb,
  1293. wm8993->pdata.jd_scthr,
  1294. wm8993->pdata.jd_thr,
  1295. wm8993->pdata.micbias1_delay,
  1296. wm8993->pdata.micbias2_delay,
  1297. wm8993->pdata.micbias1_lvl,
  1298. wm8993->pdata.micbias2_lvl);
  1299. snd_soc_add_component_controls(component, wm8993_snd_controls,
  1300. ARRAY_SIZE(wm8993_snd_controls));
  1301. if (wm8993->pdata.num_retune_configs != 0) {
  1302. dev_dbg(component->dev, "Using ReTune Mobile\n");
  1303. } else {
  1304. dev_dbg(component->dev, "No ReTune Mobile, using normal EQ\n");
  1305. snd_soc_add_component_controls(component, wm8993_eq_controls,
  1306. ARRAY_SIZE(wm8993_eq_controls));
  1307. }
  1308. snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
  1309. ARRAY_SIZE(wm8993_dapm_widgets));
  1310. wm_hubs_add_analogue_controls(component);
  1311. snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
  1312. wm_hubs_add_analogue_routes(component, wm8993->pdata.lineout1_diff,
  1313. wm8993->pdata.lineout2_diff);
  1314. /* If the line outputs are differential then we aren't presenting
  1315. * VMID as an output and can disable it.
  1316. */
  1317. if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
  1318. dapm->idle_bias_off = 1;
  1319. return 0;
  1320. }
  1321. #ifdef CONFIG_PM
  1322. static int wm8993_suspend(struct snd_soc_component *component)
  1323. {
  1324. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  1325. int fll_fout = wm8993->fll_fout;
  1326. int fll_fref = wm8993->fll_fref;
  1327. int ret;
  1328. /* Stop the FLL in an orderly fashion */
  1329. ret = _wm8993_set_fll(component, 0, 0, 0, 0);
  1330. if (ret != 0) {
  1331. dev_err(component->dev, "Failed to stop FLL\n");
  1332. return ret;
  1333. }
  1334. wm8993->fll_fout = fll_fout;
  1335. wm8993->fll_fref = fll_fref;
  1336. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  1337. return 0;
  1338. }
  1339. static int wm8993_resume(struct snd_soc_component *component)
  1340. {
  1341. struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
  1342. int ret;
  1343. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  1344. /* Restart the FLL? */
  1345. if (wm8993->fll_fout) {
  1346. int fll_fout = wm8993->fll_fout;
  1347. int fll_fref = wm8993->fll_fref;
  1348. wm8993->fll_fref = 0;
  1349. wm8993->fll_fout = 0;
  1350. ret = _wm8993_set_fll(component, 0, wm8993->fll_src,
  1351. fll_fref, fll_fout);
  1352. if (ret != 0)
  1353. dev_err(component->dev, "Failed to restart FLL\n");
  1354. }
  1355. return 0;
  1356. }
  1357. #else
  1358. #define wm8993_suspend NULL
  1359. #define wm8993_resume NULL
  1360. #endif
  1361. /* Tune DC servo configuration */
  1362. static const struct reg_sequence wm8993_regmap_patch[] = {
  1363. { 0x44, 3 },
  1364. { 0x56, 3 },
  1365. { 0x44, 0 },
  1366. };
  1367. static const struct regmap_config wm8993_regmap = {
  1368. .reg_bits = 8,
  1369. .val_bits = 16,
  1370. .max_register = WM8993_MAX_REGISTER,
  1371. .volatile_reg = wm8993_volatile,
  1372. .readable_reg = wm8993_readable,
  1373. .cache_type = REGCACHE_RBTREE,
  1374. .reg_defaults = wm8993_reg_defaults,
  1375. .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
  1376. };
  1377. static const struct snd_soc_component_driver soc_component_dev_wm8993 = {
  1378. .probe = wm8993_probe,
  1379. .suspend = wm8993_suspend,
  1380. .resume = wm8993_resume,
  1381. .set_bias_level = wm8993_set_bias_level,
  1382. .idle_bias_on = 1,
  1383. .use_pmdown_time = 1,
  1384. .endianness = 1,
  1385. .non_legacy_dai_naming = 1,
  1386. };
  1387. static int wm8993_i2c_probe(struct i2c_client *i2c,
  1388. const struct i2c_device_id *id)
  1389. {
  1390. struct wm8993_priv *wm8993;
  1391. unsigned int reg;
  1392. int ret, i;
  1393. wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
  1394. GFP_KERNEL);
  1395. if (wm8993 == NULL)
  1396. return -ENOMEM;
  1397. wm8993->dev = &i2c->dev;
  1398. init_completion(&wm8993->fll_lock);
  1399. wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap);
  1400. if (IS_ERR(wm8993->regmap)) {
  1401. ret = PTR_ERR(wm8993->regmap);
  1402. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  1403. return ret;
  1404. }
  1405. i2c_set_clientdata(i2c, wm8993);
  1406. for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
  1407. wm8993->supplies[i].supply = wm8993_supply_names[i];
  1408. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
  1409. wm8993->supplies);
  1410. if (ret != 0) {
  1411. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  1412. return ret;
  1413. }
  1414. ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
  1415. wm8993->supplies);
  1416. if (ret != 0) {
  1417. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  1418. return ret;
  1419. }
  1420. ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, &reg);
  1421. if (ret != 0) {
  1422. dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
  1423. goto err_enable;
  1424. }
  1425. if (reg != 0x8993) {
  1426. dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
  1427. ret = -EINVAL;
  1428. goto err_enable;
  1429. }
  1430. ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
  1431. if (ret != 0)
  1432. goto err_enable;
  1433. ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
  1434. ARRAY_SIZE(wm8993_regmap_patch));
  1435. if (ret != 0)
  1436. dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
  1437. ret);
  1438. if (i2c->irq) {
  1439. /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
  1440. ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
  1441. WM8993_GPIO1_PD |
  1442. WM8993_GPIO1_SEL_MASK, 7);
  1443. if (ret != 0)
  1444. goto err_enable;
  1445. ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
  1446. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  1447. "wm8993", wm8993);
  1448. if (ret != 0)
  1449. goto err_enable;
  1450. }
  1451. regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
  1452. regcache_cache_only(wm8993->regmap, true);
  1453. ret = devm_snd_soc_register_component(&i2c->dev,
  1454. &soc_component_dev_wm8993, &wm8993_dai, 1);
  1455. if (ret != 0) {
  1456. dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
  1457. goto err_irq;
  1458. }
  1459. return 0;
  1460. err_irq:
  1461. if (i2c->irq)
  1462. free_irq(i2c->irq, wm8993);
  1463. err_enable:
  1464. regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
  1465. return ret;
  1466. }
  1467. static int wm8993_i2c_remove(struct i2c_client *i2c)
  1468. {
  1469. struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
  1470. if (i2c->irq)
  1471. free_irq(i2c->irq, wm8993);
  1472. regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
  1473. return 0;
  1474. }
  1475. static const struct i2c_device_id wm8993_i2c_id[] = {
  1476. { "wm8993", 0 },
  1477. { }
  1478. };
  1479. MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
  1480. static struct i2c_driver wm8993_i2c_driver = {
  1481. .driver = {
  1482. .name = "wm8993",
  1483. },
  1484. .probe = wm8993_i2c_probe,
  1485. .remove = wm8993_i2c_remove,
  1486. .id_table = wm8993_i2c_id,
  1487. };
  1488. module_i2c_driver(wm8993_i2c_driver);
  1489. MODULE_DESCRIPTION("ASoC WM8993 driver");
  1490. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  1491. MODULE_LICENSE("GPL");