wm8991.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm8991.c -- WM8991 ALSA Soc Audio driver
  4. *
  5. * Copyright 2007-2010 Wolfson Microelectronics PLC.
  6. * Author: Graeme Gregory
  7. * Graeme.Gregory@wolfsonmicro.com
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/i2c.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/soc-dapm.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <asm/div64.h>
  26. #include "wm8991.h"
  27. struct wm8991_priv {
  28. struct regmap *regmap;
  29. unsigned int pcmclk;
  30. };
  31. static const struct reg_default wm8991_reg_defaults[] = {
  32. { 1, 0x0000 }, /* R1 - Power Management (1) */
  33. { 2, 0x6000 }, /* R2 - Power Management (2) */
  34. { 3, 0x0000 }, /* R3 - Power Management (3) */
  35. { 4, 0x4050 }, /* R4 - Audio Interface (1) */
  36. { 5, 0x4000 }, /* R5 - Audio Interface (2) */
  37. { 6, 0x01C8 }, /* R6 - Clocking (1) */
  38. { 7, 0x0000 }, /* R7 - Clocking (2) */
  39. { 8, 0x0040 }, /* R8 - Audio Interface (3) */
  40. { 9, 0x0040 }, /* R9 - Audio Interface (4) */
  41. { 10, 0x0004 }, /* R10 - DAC CTRL */
  42. { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
  43. { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
  44. { 13, 0x0000 }, /* R13 - Digital Side Tone */
  45. { 14, 0x0100 }, /* R14 - ADC CTRL */
  46. { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
  47. { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
  48. { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
  49. { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */
  50. { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */
  51. { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */
  52. { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
  53. { 23, 0x0800 }, /* R23 - GPIO_POL */
  54. { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
  55. { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
  56. { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
  57. { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
  58. { 28, 0x0000 }, /* R28 - Left Output Volume */
  59. { 29, 0x0000 }, /* R29 - Right Output Volume */
  60. { 30, 0x0066 }, /* R30 - Line Outputs Volume */
  61. { 31, 0x0022 }, /* R31 - Out3/4 Volume */
  62. { 32, 0x0079 }, /* R32 - Left OPGA Volume */
  63. { 33, 0x0079 }, /* R33 - Right OPGA Volume */
  64. { 34, 0x0003 }, /* R34 - Speaker Volume */
  65. { 35, 0x0003 }, /* R35 - ClassD1 */
  66. { 37, 0x0100 }, /* R37 - ClassD3 */
  67. { 39, 0x0000 }, /* R39 - Input Mixer1 */
  68. { 40, 0x0000 }, /* R40 - Input Mixer2 */
  69. { 41, 0x0000 }, /* R41 - Input Mixer3 */
  70. { 42, 0x0000 }, /* R42 - Input Mixer4 */
  71. { 43, 0x0000 }, /* R43 - Input Mixer5 */
  72. { 44, 0x0000 }, /* R44 - Input Mixer6 */
  73. { 45, 0x0000 }, /* R45 - Output Mixer1 */
  74. { 46, 0x0000 }, /* R46 - Output Mixer2 */
  75. { 47, 0x0000 }, /* R47 - Output Mixer3 */
  76. { 48, 0x0000 }, /* R48 - Output Mixer4 */
  77. { 49, 0x0000 }, /* R49 - Output Mixer5 */
  78. { 50, 0x0000 }, /* R50 - Output Mixer6 */
  79. { 51, 0x0180 }, /* R51 - Out3/4 Mixer */
  80. { 52, 0x0000 }, /* R52 - Line Mixer1 */
  81. { 53, 0x0000 }, /* R53 - Line Mixer2 */
  82. { 54, 0x0000 }, /* R54 - Speaker Mixer */
  83. { 55, 0x0000 }, /* R55 - Additional Control */
  84. { 56, 0x0000 }, /* R56 - AntiPOP1 */
  85. { 57, 0x0000 }, /* R57 - AntiPOP2 */
  86. { 58, 0x0000 }, /* R58 - MICBIAS */
  87. { 60, 0x0008 }, /* R60 - PLL1 */
  88. { 61, 0x0031 }, /* R61 - PLL2 */
  89. { 62, 0x0026 }, /* R62 - PLL3 */
  90. };
  91. static bool wm8991_volatile(struct device *dev, unsigned int reg)
  92. {
  93. switch (reg) {
  94. case WM8991_RESET:
  95. return true;
  96. default:
  97. return false;
  98. }
  99. }
  100. static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_pga_tlv, -1650, 150, 0);
  101. static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(out_mix_tlv, -2100, 300, 0);
  102. static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_pga_tlv,
  103. 0x00, 0x2f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(SNDRV_CTL_TLVD_DB_GAIN_MUTE, 0, 1),
  104. 0x30, 0x7f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-7300, 100, 0),
  105. );
  106. static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_dac_tlv,
  107. 0x00, 0xbf, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1),
  108. 0xc0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0),
  109. );
  110. static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(in_adc_tlv,
  111. 0x00, 0xef, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1),
  112. 0xf0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(17625, 0, 0),
  113. );
  114. static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_sidetone_tlv,
  115. 0x00, 0x0c, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-3600, 300, 0),
  116. 0x0d, 0x0f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0),
  117. );
  118. static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
  119. struct snd_ctl_elem_value *ucontrol)
  120. {
  121. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  122. int reg = kcontrol->private_value & 0xff;
  123. int ret;
  124. u16 val;
  125. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  126. if (ret < 0)
  127. return ret;
  128. /* now hit the volume update bits (always bit 8) */
  129. val = snd_soc_component_read(component, reg);
  130. return snd_soc_component_write(component, reg, val | 0x0100);
  131. }
  132. static const char *wm8991_digital_sidetone[] =
  133. {"None", "Left ADC", "Right ADC", "Reserved"};
  134. static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum,
  135. WM8991_DIGITAL_SIDE_TONE,
  136. WM8991_ADC_TO_DACL_SHIFT,
  137. wm8991_digital_sidetone);
  138. static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum,
  139. WM8991_DIGITAL_SIDE_TONE,
  140. WM8991_ADC_TO_DACR_SHIFT,
  141. wm8991_digital_sidetone);
  142. static const char *wm8991_adcmode[] =
  143. {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
  144. static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum,
  145. WM8991_ADC_CTRL,
  146. WM8991_ADC_HPF_CUT_SHIFT,
  147. wm8991_adcmode);
  148. static const struct snd_kcontrol_new wm8991_snd_controls[] = {
  149. /* INMIXL */
  150. SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0),
  151. SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0),
  152. /* INMIXR */
  153. SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0),
  154. SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0),
  155. /* LOMIX */
  156. SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
  157. WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv),
  158. SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
  159. WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv),
  160. SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
  161. WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv),
  162. SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
  163. WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv),
  164. SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
  165. WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
  166. SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
  167. WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
  168. /* ROMIX */
  169. SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
  170. WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv),
  171. SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
  172. WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv),
  173. SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
  174. WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv),
  175. SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
  176. WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv),
  177. SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
  178. WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv),
  179. SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
  180. WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv),
  181. /* LOUT */
  182. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME,
  183. WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv),
  184. SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0),
  185. /* ROUT */
  186. SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME,
  187. WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv),
  188. SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0),
  189. /* LOPGA */
  190. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME,
  191. WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv),
  192. SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME,
  193. WM8991_LOPGAZC_BIT, 1, 0),
  194. /* ROPGA */
  195. SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME,
  196. WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv),
  197. SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME,
  198. WM8991_ROPGAZC_BIT, 1, 0),
  199. SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  200. WM8991_LONMUTE_BIT, 1, 0),
  201. SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  202. WM8991_LOPMUTE_BIT, 1, 0),
  203. SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
  204. WM8991_LOATTN_BIT, 1, 0),
  205. SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  206. WM8991_RONMUTE_BIT, 1, 0),
  207. SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
  208. WM8991_ROPMUTE_BIT, 1, 0),
  209. SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
  210. WM8991_ROATTN_BIT, 1, 0),
  211. SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME,
  212. WM8991_OUT3MUTE_BIT, 1, 0),
  213. SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME,
  214. WM8991_OUT3ATTN_BIT, 1, 0),
  215. SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME,
  216. WM8991_OUT4MUTE_BIT, 1, 0),
  217. SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME,
  218. WM8991_OUT4ATTN_BIT, 1, 0),
  219. SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1,
  220. WM8991_CDMODE_BIT, 1, 0),
  221. SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME,
  222. WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0),
  223. SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3,
  224. WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0),
  225. SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3,
  226. WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0),
  227. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
  228. WM8991_LEFT_DAC_DIGITAL_VOLUME,
  229. WM8991_DACL_VOL_SHIFT,
  230. WM8991_DACL_VOL_MASK,
  231. 0,
  232. out_dac_tlv),
  233. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
  234. WM8991_RIGHT_DAC_DIGITAL_VOLUME,
  235. WM8991_DACR_VOL_SHIFT,
  236. WM8991_DACR_VOL_MASK,
  237. 0,
  238. out_dac_tlv),
  239. SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum),
  240. SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum),
  241. SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
  242. WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0,
  243. out_sidetone_tlv),
  244. SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
  245. WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0,
  246. out_sidetone_tlv),
  247. SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL,
  248. WM8991_ADC_HPF_ENA_BIT, 1, 0),
  249. SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum),
  250. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
  251. WM8991_LEFT_ADC_DIGITAL_VOLUME,
  252. WM8991_ADCL_VOL_SHIFT,
  253. WM8991_ADCL_VOL_MASK,
  254. 0,
  255. in_adc_tlv),
  256. SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
  257. WM8991_RIGHT_ADC_DIGITAL_VOLUME,
  258. WM8991_ADCR_VOL_SHIFT,
  259. WM8991_ADCR_VOL_MASK,
  260. 0,
  261. in_adc_tlv),
  262. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
  263. WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
  264. WM8991_LIN12VOL_SHIFT,
  265. WM8991_LIN12VOL_MASK,
  266. 0,
  267. in_pga_tlv),
  268. SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
  269. WM8991_LI12ZC_BIT, 1, 0),
  270. SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
  271. WM8991_LI12MUTE_BIT, 1, 0),
  272. SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
  273. WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
  274. WM8991_LIN34VOL_SHIFT,
  275. WM8991_LIN34VOL_MASK,
  276. 0,
  277. in_pga_tlv),
  278. SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
  279. WM8991_LI34ZC_BIT, 1, 0),
  280. SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
  281. WM8991_LI34MUTE_BIT, 1, 0),
  282. SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
  283. WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
  284. WM8991_RIN12VOL_SHIFT,
  285. WM8991_RIN12VOL_MASK,
  286. 0,
  287. in_pga_tlv),
  288. SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
  289. WM8991_RI12ZC_BIT, 1, 0),
  290. SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
  291. WM8991_RI12MUTE_BIT, 1, 0),
  292. SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
  293. WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
  294. WM8991_RIN34VOL_SHIFT,
  295. WM8991_RIN34VOL_MASK,
  296. 0,
  297. in_pga_tlv),
  298. SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
  299. WM8991_RI34ZC_BIT, 1, 0),
  300. SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
  301. WM8991_RI34MUTE_BIT, 1, 0),
  302. };
  303. /*
  304. * _DAPM_ Controls
  305. */
  306. static int outmixer_event(struct snd_soc_dapm_widget *w,
  307. struct snd_kcontrol *kcontrol, int event)
  308. {
  309. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  310. u32 reg_shift = kcontrol->private_value & 0xfff;
  311. int ret = 0;
  312. u16 reg;
  313. switch (reg_shift) {
  314. case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8):
  315. reg = snd_soc_component_read(component, WM8991_OUTPUT_MIXER1);
  316. if (reg & WM8991_LDLO) {
  317. printk(KERN_WARNING
  318. "Cannot set as Output Mixer 1 LDLO Set\n");
  319. ret = -1;
  320. }
  321. break;
  322. case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8):
  323. reg = snd_soc_component_read(component, WM8991_OUTPUT_MIXER2);
  324. if (reg & WM8991_RDRO) {
  325. printk(KERN_WARNING
  326. "Cannot set as Output Mixer 2 RDRO Set\n");
  327. ret = -1;
  328. }
  329. break;
  330. case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8):
  331. reg = snd_soc_component_read(component, WM8991_SPEAKER_MIXER);
  332. if (reg & WM8991_LDSPK) {
  333. printk(KERN_WARNING
  334. "Cannot set as Speaker Mixer LDSPK Set\n");
  335. ret = -1;
  336. }
  337. break;
  338. case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8):
  339. reg = snd_soc_component_read(component, WM8991_SPEAKER_MIXER);
  340. if (reg & WM8991_RDSPK) {
  341. printk(KERN_WARNING
  342. "Cannot set as Speaker Mixer RDSPK Set\n");
  343. ret = -1;
  344. }
  345. break;
  346. }
  347. return ret;
  348. }
  349. /* INMIX dB values */
  350. static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_mix_tlv, -1200, 300, 1);
  351. /* Left In PGA Connections */
  352. static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = {
  353. SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0),
  354. SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0),
  355. };
  356. static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = {
  357. SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0),
  358. SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0),
  359. };
  360. /* Right In PGA Connections */
  361. static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = {
  362. SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0),
  363. SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0),
  364. };
  365. static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = {
  366. SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0),
  367. SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0),
  368. };
  369. /* INMIXL */
  370. static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = {
  371. SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3,
  372. WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv),
  373. SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT,
  374. 7, 0, in_mix_tlv),
  375. SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
  376. 1, 0),
  377. SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
  378. 1, 0),
  379. };
  380. /* INMIXR */
  381. static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = {
  382. SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4,
  383. WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv),
  384. SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT,
  385. 7, 0, in_mix_tlv),
  386. SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
  387. 1, 0),
  388. SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
  389. 1, 0),
  390. };
  391. /* AINLMUX */
  392. static const char *wm8991_ainlmux[] =
  393. {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
  394. static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum,
  395. WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT,
  396. wm8991_ainlmux);
  397. static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls =
  398. SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum);
  399. /* DIFFINL */
  400. /* AINRMUX */
  401. static const char *wm8991_ainrmux[] =
  402. {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
  403. static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum,
  404. WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT,
  405. wm8991_ainrmux);
  406. static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls =
  407. SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum);
  408. /* LOMIX */
  409. static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = {
  410. SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
  411. WM8991_LRBLO_BIT, 1, 0),
  412. SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
  413. WM8991_LLBLO_BIT, 1, 0),
  414. SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
  415. WM8991_LRI3LO_BIT, 1, 0),
  416. SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
  417. WM8991_LLI3LO_BIT, 1, 0),
  418. SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
  419. WM8991_LR12LO_BIT, 1, 0),
  420. SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
  421. WM8991_LL12LO_BIT, 1, 0),
  422. SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1,
  423. WM8991_LDLO_BIT, 1, 0),
  424. };
  425. /* ROMIX */
  426. static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = {
  427. SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
  428. WM8991_RLBRO_BIT, 1, 0),
  429. SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
  430. WM8991_RRBRO_BIT, 1, 0),
  431. SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
  432. WM8991_RLI3RO_BIT, 1, 0),
  433. SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
  434. WM8991_RRI3RO_BIT, 1, 0),
  435. SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
  436. WM8991_RL12RO_BIT, 1, 0),
  437. SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
  438. WM8991_RR12RO_BIT, 1, 0),
  439. SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2,
  440. WM8991_RDRO_BIT, 1, 0),
  441. };
  442. /* LONMIX */
  443. static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = {
  444. SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
  445. WM8991_LLOPGALON_BIT, 1, 0),
  446. SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1,
  447. WM8991_LROPGALON_BIT, 1, 0),
  448. SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1,
  449. WM8991_LOPLON_BIT, 1, 0),
  450. };
  451. /* LOPMIX */
  452. static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = {
  453. SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1,
  454. WM8991_LR12LOP_BIT, 1, 0),
  455. SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1,
  456. WM8991_LL12LOP_BIT, 1, 0),
  457. SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
  458. WM8991_LLOPGALOP_BIT, 1, 0),
  459. };
  460. /* RONMIX */
  461. static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = {
  462. SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
  463. WM8991_RROPGARON_BIT, 1, 0),
  464. SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2,
  465. WM8991_RLOPGARON_BIT, 1, 0),
  466. SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2,
  467. WM8991_ROPRON_BIT, 1, 0),
  468. };
  469. /* ROPMIX */
  470. static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = {
  471. SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2,
  472. WM8991_RL12ROP_BIT, 1, 0),
  473. SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2,
  474. WM8991_RR12ROP_BIT, 1, 0),
  475. SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
  476. WM8991_RROPGAROP_BIT, 1, 0),
  477. };
  478. /* OUT3MIX */
  479. static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = {
  480. SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER,
  481. WM8991_LI4O3_BIT, 1, 0),
  482. SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER,
  483. WM8991_LPGAO3_BIT, 1, 0),
  484. };
  485. /* OUT4MIX */
  486. static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = {
  487. SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER,
  488. WM8991_RPGAO4_BIT, 1, 0),
  489. SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER,
  490. WM8991_RI4O4_BIT, 1, 0),
  491. };
  492. /* SPKMIX */
  493. static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = {
  494. SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
  495. WM8991_LI2SPK_BIT, 1, 0),
  496. SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER,
  497. WM8991_LB2SPK_BIT, 1, 0),
  498. SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER,
  499. WM8991_LOPGASPK_BIT, 1, 0),
  500. SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER,
  501. WM8991_LDSPK_BIT, 1, 0),
  502. SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER,
  503. WM8991_RDSPK_BIT, 1, 0),
  504. SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER,
  505. WM8991_ROPGASPK_BIT, 1, 0),
  506. SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER,
  507. WM8991_RL12ROP_BIT, 1, 0),
  508. SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
  509. WM8991_RI2SPK_BIT, 1, 0),
  510. };
  511. static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = {
  512. /* Input Side */
  513. /* Input Lines */
  514. SND_SOC_DAPM_INPUT("LIN1"),
  515. SND_SOC_DAPM_INPUT("LIN2"),
  516. SND_SOC_DAPM_INPUT("LIN3"),
  517. SND_SOC_DAPM_INPUT("LIN4RXN"),
  518. SND_SOC_DAPM_INPUT("RIN3"),
  519. SND_SOC_DAPM_INPUT("RIN4RXP"),
  520. SND_SOC_DAPM_INPUT("RIN1"),
  521. SND_SOC_DAPM_INPUT("RIN2"),
  522. SND_SOC_DAPM_INPUT("Internal ADC Source"),
  523. SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2,
  524. WM8991_AINL_ENA_BIT, 0, NULL, 0),
  525. SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2,
  526. WM8991_AINR_ENA_BIT, 0, NULL, 0),
  527. /* DACs */
  528. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2,
  529. WM8991_ADCL_ENA_BIT, 0),
  530. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2,
  531. WM8991_ADCR_ENA_BIT, 0),
  532. /* Input PGAs */
  533. SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT,
  534. 0, &wm8991_dapm_lin12_pga_controls[0],
  535. ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)),
  536. SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT,
  537. 0, &wm8991_dapm_lin34_pga_controls[0],
  538. ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)),
  539. SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT,
  540. 0, &wm8991_dapm_rin12_pga_controls[0],
  541. ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)),
  542. SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT,
  543. 0, &wm8991_dapm_rin34_pga_controls[0],
  544. ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)),
  545. /* INMIXL */
  546. SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
  547. &wm8991_dapm_inmixl_controls[0],
  548. ARRAY_SIZE(wm8991_dapm_inmixl_controls)),
  549. /* AINLMUX */
  550. SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0,
  551. &wm8991_dapm_ainlmux_controls),
  552. /* INMIXR */
  553. SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
  554. &wm8991_dapm_inmixr_controls[0],
  555. ARRAY_SIZE(wm8991_dapm_inmixr_controls)),
  556. /* AINRMUX */
  557. SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0,
  558. &wm8991_dapm_ainrmux_controls),
  559. /* Output Side */
  560. /* DACs */
  561. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3,
  562. WM8991_DACL_ENA_BIT, 0),
  563. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3,
  564. WM8991_DACR_ENA_BIT, 0),
  565. /* LOMIX */
  566. SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT,
  567. 0, &wm8991_dapm_lomix_controls[0],
  568. ARRAY_SIZE(wm8991_dapm_lomix_controls),
  569. outmixer_event, SND_SOC_DAPM_PRE_REG),
  570. /* LONMIX */
  571. SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0,
  572. &wm8991_dapm_lonmix_controls[0],
  573. ARRAY_SIZE(wm8991_dapm_lonmix_controls)),
  574. /* LOPMIX */
  575. SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0,
  576. &wm8991_dapm_lopmix_controls[0],
  577. ARRAY_SIZE(wm8991_dapm_lopmix_controls)),
  578. /* OUT3MIX */
  579. SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0,
  580. &wm8991_dapm_out3mix_controls[0],
  581. ARRAY_SIZE(wm8991_dapm_out3mix_controls)),
  582. /* SPKMIX */
  583. SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0,
  584. &wm8991_dapm_spkmix_controls[0],
  585. ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event,
  586. SND_SOC_DAPM_PRE_REG),
  587. /* OUT4MIX */
  588. SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0,
  589. &wm8991_dapm_out4mix_controls[0],
  590. ARRAY_SIZE(wm8991_dapm_out4mix_controls)),
  591. /* ROPMIX */
  592. SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0,
  593. &wm8991_dapm_ropmix_controls[0],
  594. ARRAY_SIZE(wm8991_dapm_ropmix_controls)),
  595. /* RONMIX */
  596. SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0,
  597. &wm8991_dapm_ronmix_controls[0],
  598. ARRAY_SIZE(wm8991_dapm_ronmix_controls)),
  599. /* ROMIX */
  600. SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT,
  601. 0, &wm8991_dapm_romix_controls[0],
  602. ARRAY_SIZE(wm8991_dapm_romix_controls),
  603. outmixer_event, SND_SOC_DAPM_PRE_REG),
  604. /* LOUT PGA */
  605. SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0,
  606. NULL, 0),
  607. /* ROUT PGA */
  608. SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0,
  609. NULL, 0),
  610. /* LOPGA */
  611. SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0,
  612. NULL, 0),
  613. /* ROPGA */
  614. SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0,
  615. NULL, 0),
  616. /* MICBIAS */
  617. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1,
  618. WM8991_MICBIAS_ENA_BIT, 0, NULL, 0),
  619. SND_SOC_DAPM_OUTPUT("LON"),
  620. SND_SOC_DAPM_OUTPUT("LOP"),
  621. SND_SOC_DAPM_OUTPUT("OUT3"),
  622. SND_SOC_DAPM_OUTPUT("LOUT"),
  623. SND_SOC_DAPM_OUTPUT("SPKN"),
  624. SND_SOC_DAPM_OUTPUT("SPKP"),
  625. SND_SOC_DAPM_OUTPUT("ROUT"),
  626. SND_SOC_DAPM_OUTPUT("OUT4"),
  627. SND_SOC_DAPM_OUTPUT("ROP"),
  628. SND_SOC_DAPM_OUTPUT("RON"),
  629. SND_SOC_DAPM_OUTPUT("OUT"),
  630. SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
  631. };
  632. static const struct snd_soc_dapm_route wm8991_dapm_routes[] = {
  633. /* Make DACs turn on when playing even if not mixed into any outputs */
  634. {"Internal DAC Sink", NULL, "Left DAC"},
  635. {"Internal DAC Sink", NULL, "Right DAC"},
  636. /* Make ADCs turn on when recording even if not mixed from any inputs */
  637. {"Left ADC", NULL, "Internal ADC Source"},
  638. {"Right ADC", NULL, "Internal ADC Source"},
  639. /* Input Side */
  640. {"INMIXL", NULL, "INL"},
  641. {"AINLMUX", NULL, "INL"},
  642. {"INMIXR", NULL, "INR"},
  643. {"AINRMUX", NULL, "INR"},
  644. /* LIN12 PGA */
  645. {"LIN12 PGA", "LIN1 Switch", "LIN1"},
  646. {"LIN12 PGA", "LIN2 Switch", "LIN2"},
  647. /* LIN34 PGA */
  648. {"LIN34 PGA", "LIN3 Switch", "LIN3"},
  649. {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"},
  650. /* INMIXL */
  651. {"INMIXL", "Record Left Volume", "LOMIX"},
  652. {"INMIXL", "LIN2 Volume", "LIN2"},
  653. {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
  654. {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
  655. /* AINLMUX */
  656. {"AINLMUX", "INMIXL Mix", "INMIXL"},
  657. {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
  658. {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
  659. {"AINLMUX", "RXVOICE Mix", "LIN4RXN"},
  660. {"AINLMUX", "RXVOICE Mix", "RIN4RXP"},
  661. /* ADC */
  662. {"Left ADC", NULL, "AINLMUX"},
  663. /* RIN12 PGA */
  664. {"RIN12 PGA", "RIN1 Switch", "RIN1"},
  665. {"RIN12 PGA", "RIN2 Switch", "RIN2"},
  666. /* RIN34 PGA */
  667. {"RIN34 PGA", "RIN3 Switch", "RIN3"},
  668. {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"},
  669. /* INMIXL */
  670. {"INMIXR", "Record Right Volume", "ROMIX"},
  671. {"INMIXR", "RIN2 Volume", "RIN2"},
  672. {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
  673. {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
  674. /* AINRMUX */
  675. {"AINRMUX", "INMIXR Mix", "INMIXR"},
  676. {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
  677. {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
  678. {"AINRMUX", "RXVOICE Mix", "LIN4RXN"},
  679. {"AINRMUX", "RXVOICE Mix", "RIN4RXP"},
  680. /* ADC */
  681. {"Right ADC", NULL, "AINRMUX"},
  682. /* LOMIX */
  683. {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
  684. {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
  685. {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
  686. {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
  687. {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
  688. {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
  689. {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
  690. /* ROMIX */
  691. {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
  692. {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
  693. {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
  694. {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
  695. {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
  696. {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
  697. {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
  698. /* SPKMIX */
  699. {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
  700. {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
  701. {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
  702. {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
  703. {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
  704. {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
  705. {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
  706. {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
  707. /* LONMIX */
  708. {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
  709. {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
  710. {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
  711. /* LOPMIX */
  712. {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
  713. {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
  714. {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
  715. /* OUT3MIX */
  716. {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"},
  717. {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
  718. /* OUT4MIX */
  719. {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
  720. {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"},
  721. /* RONMIX */
  722. {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
  723. {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
  724. {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
  725. /* ROPMIX */
  726. {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
  727. {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
  728. {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
  729. /* Out Mixer PGAs */
  730. {"LOPGA", NULL, "LOMIX"},
  731. {"ROPGA", NULL, "ROMIX"},
  732. {"LOUT PGA", NULL, "LOMIX"},
  733. {"ROUT PGA", NULL, "ROMIX"},
  734. /* Output Pins */
  735. {"LON", NULL, "LONMIX"},
  736. {"LOP", NULL, "LOPMIX"},
  737. {"OUT", NULL, "OUT3MIX"},
  738. {"LOUT", NULL, "LOUT PGA"},
  739. {"SPKN", NULL, "SPKMIX"},
  740. {"ROUT", NULL, "ROUT PGA"},
  741. {"OUT4", NULL, "OUT4MIX"},
  742. {"ROP", NULL, "ROPMIX"},
  743. {"RON", NULL, "RONMIX"},
  744. };
  745. /* PLL divisors */
  746. struct _pll_div {
  747. u32 div2;
  748. u32 n;
  749. u32 k;
  750. };
  751. /* The size in bits of the pll divide multiplied by 10
  752. * to allow rounding later */
  753. #define FIXED_PLL_SIZE ((1 << 16) * 10)
  754. static void pll_factors(struct _pll_div *pll_div, unsigned int target,
  755. unsigned int source)
  756. {
  757. u64 Kpart;
  758. unsigned int K, Ndiv, Nmod;
  759. Ndiv = target / source;
  760. if (Ndiv < 6) {
  761. source >>= 1;
  762. pll_div->div2 = 1;
  763. Ndiv = target / source;
  764. } else
  765. pll_div->div2 = 0;
  766. if ((Ndiv < 6) || (Ndiv > 12))
  767. printk(KERN_WARNING
  768. "WM8991 N value outwith recommended range! N = %d\n", Ndiv);
  769. pll_div->n = Ndiv;
  770. Nmod = target % source;
  771. Kpart = FIXED_PLL_SIZE * (long long)Nmod;
  772. do_div(Kpart, source);
  773. K = Kpart & 0xFFFFFFFF;
  774. /* Check if we need to round */
  775. if ((K % 10) >= 5)
  776. K += 5;
  777. /* Move down to proper range now rounding is done */
  778. K /= 10;
  779. pll_div->k = K;
  780. }
  781. static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai,
  782. int pll_id, int src, unsigned int freq_in, unsigned int freq_out)
  783. {
  784. u16 reg;
  785. struct snd_soc_component *component = codec_dai->component;
  786. struct _pll_div pll_div;
  787. if (freq_in && freq_out) {
  788. pll_factors(&pll_div, freq_out * 4, freq_in);
  789. /* Turn on PLL */
  790. reg = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_2);
  791. reg |= WM8991_PLL_ENA;
  792. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg);
  793. /* sysclk comes from PLL */
  794. reg = snd_soc_component_read(component, WM8991_CLOCKING_2);
  795. snd_soc_component_write(component, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC);
  796. /* set up N , fractional mode and pre-divisor if necessary */
  797. snd_soc_component_write(component, WM8991_PLL1, pll_div.n | WM8991_SDM |
  798. (pll_div.div2 ? WM8991_PRESCALE : 0));
  799. snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8));
  800. snd_soc_component_write(component, WM8991_PLL3, (u8)(pll_div.k & 0xFF));
  801. } else {
  802. /* Turn on PLL */
  803. reg = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_2);
  804. reg &= ~WM8991_PLL_ENA;
  805. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg);
  806. }
  807. return 0;
  808. }
  809. /*
  810. * Set's ADC and Voice DAC format.
  811. */
  812. static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai,
  813. unsigned int fmt)
  814. {
  815. struct snd_soc_component *component = codec_dai->component;
  816. u16 audio1, audio3;
  817. audio1 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_1);
  818. audio3 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_3);
  819. /* set master/slave audio interface */
  820. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  821. case SND_SOC_DAIFMT_CBS_CFS:
  822. audio3 &= ~WM8991_AIF_MSTR1;
  823. break;
  824. case SND_SOC_DAIFMT_CBM_CFM:
  825. audio3 |= WM8991_AIF_MSTR1;
  826. break;
  827. default:
  828. return -EINVAL;
  829. }
  830. audio1 &= ~WM8991_AIF_FMT_MASK;
  831. /* interface format */
  832. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  833. case SND_SOC_DAIFMT_I2S:
  834. audio1 |= WM8991_AIF_TMF_I2S;
  835. audio1 &= ~WM8991_AIF_LRCLK_INV;
  836. break;
  837. case SND_SOC_DAIFMT_RIGHT_J:
  838. audio1 |= WM8991_AIF_TMF_RIGHTJ;
  839. audio1 &= ~WM8991_AIF_LRCLK_INV;
  840. break;
  841. case SND_SOC_DAIFMT_LEFT_J:
  842. audio1 |= WM8991_AIF_TMF_LEFTJ;
  843. audio1 &= ~WM8991_AIF_LRCLK_INV;
  844. break;
  845. case SND_SOC_DAIFMT_DSP_A:
  846. audio1 |= WM8991_AIF_TMF_DSP;
  847. audio1 &= ~WM8991_AIF_LRCLK_INV;
  848. break;
  849. case SND_SOC_DAIFMT_DSP_B:
  850. audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV;
  851. break;
  852. default:
  853. return -EINVAL;
  854. }
  855. snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1);
  856. snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_3, audio3);
  857. return 0;
  858. }
  859. static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  860. int div_id, int div)
  861. {
  862. struct snd_soc_component *component = codec_dai->component;
  863. u16 reg;
  864. switch (div_id) {
  865. case WM8991_MCLK_DIV:
  866. reg = snd_soc_component_read(component, WM8991_CLOCKING_2) &
  867. ~WM8991_MCLK_DIV_MASK;
  868. snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div);
  869. break;
  870. case WM8991_DACCLK_DIV:
  871. reg = snd_soc_component_read(component, WM8991_CLOCKING_2) &
  872. ~WM8991_DAC_CLKDIV_MASK;
  873. snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div);
  874. break;
  875. case WM8991_ADCCLK_DIV:
  876. reg = snd_soc_component_read(component, WM8991_CLOCKING_2) &
  877. ~WM8991_ADC_CLKDIV_MASK;
  878. snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div);
  879. break;
  880. case WM8991_BCLK_DIV:
  881. reg = snd_soc_component_read(component, WM8991_CLOCKING_1) &
  882. ~WM8991_BCLK_DIV_MASK;
  883. snd_soc_component_write(component, WM8991_CLOCKING_1, reg | div);
  884. break;
  885. default:
  886. return -EINVAL;
  887. }
  888. return 0;
  889. }
  890. /*
  891. * Set PCM DAI bit size and sample rate.
  892. */
  893. static int wm8991_hw_params(struct snd_pcm_substream *substream,
  894. struct snd_pcm_hw_params *params,
  895. struct snd_soc_dai *dai)
  896. {
  897. struct snd_soc_component *component = dai->component;
  898. u16 audio1 = snd_soc_component_read(component, WM8991_AUDIO_INTERFACE_1);
  899. audio1 &= ~WM8991_AIF_WL_MASK;
  900. /* bit size */
  901. switch (params_width(params)) {
  902. case 16:
  903. break;
  904. case 20:
  905. audio1 |= WM8991_AIF_WL_20BITS;
  906. break;
  907. case 24:
  908. audio1 |= WM8991_AIF_WL_24BITS;
  909. break;
  910. case 32:
  911. audio1 |= WM8991_AIF_WL_32BITS;
  912. break;
  913. }
  914. snd_soc_component_write(component, WM8991_AUDIO_INTERFACE_1, audio1);
  915. return 0;
  916. }
  917. static int wm8991_mute(struct snd_soc_dai *dai, int mute, int direction)
  918. {
  919. struct snd_soc_component *component = dai->component;
  920. u16 val;
  921. val = snd_soc_component_read(component, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE;
  922. if (mute)
  923. snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
  924. else
  925. snd_soc_component_write(component, WM8991_DAC_CTRL, val);
  926. return 0;
  927. }
  928. static int wm8991_set_bias_level(struct snd_soc_component *component,
  929. enum snd_soc_bias_level level)
  930. {
  931. struct wm8991_priv *wm8991 = snd_soc_component_get_drvdata(component);
  932. u16 val;
  933. switch (level) {
  934. case SND_SOC_BIAS_ON:
  935. break;
  936. case SND_SOC_BIAS_PREPARE:
  937. /* VMID=2*50k */
  938. val = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_1) &
  939. ~WM8991_VMID_MODE_MASK;
  940. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x2);
  941. break;
  942. case SND_SOC_BIAS_STANDBY:
  943. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  944. regcache_sync(wm8991->regmap);
  945. /* Enable all output discharge bits */
  946. snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
  947. WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
  948. WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
  949. WM8991_DIS_ROUT);
  950. /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
  951. snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
  952. WM8991_BUFDCOPEN | WM8991_POBCTRL |
  953. WM8991_VMIDTOG);
  954. /* Delay to allow output caps to discharge */
  955. msleep(300);
  956. /* Disable VMIDTOG */
  957. snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
  958. WM8991_BUFDCOPEN | WM8991_POBCTRL);
  959. /* disable all output discharge bits */
  960. snd_soc_component_write(component, WM8991_ANTIPOP1, 0);
  961. /* Enable outputs */
  962. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1b00);
  963. msleep(50);
  964. /* Enable VMID at 2x50k */
  965. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f02);
  966. msleep(100);
  967. /* Enable VREF */
  968. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03);
  969. msleep(600);
  970. /* Enable BUFIOEN */
  971. snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
  972. WM8991_BUFDCOPEN | WM8991_POBCTRL |
  973. WM8991_BUFIOEN);
  974. /* Disable outputs */
  975. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x3);
  976. /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
  977. snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_BUFIOEN);
  978. }
  979. /* VMID=2*250k */
  980. val = snd_soc_component_read(component, WM8991_POWER_MANAGEMENT_1) &
  981. ~WM8991_VMID_MODE_MASK;
  982. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, val | 0x4);
  983. break;
  984. case SND_SOC_BIAS_OFF:
  985. /* Enable POBCTRL and SOFT_ST */
  986. snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
  987. WM8991_POBCTRL | WM8991_BUFIOEN);
  988. /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
  989. snd_soc_component_write(component, WM8991_ANTIPOP2, WM8991_SOFTST |
  990. WM8991_BUFDCOPEN | WM8991_POBCTRL |
  991. WM8991_BUFIOEN);
  992. /* mute DAC */
  993. val = snd_soc_component_read(component, WM8991_DAC_CTRL);
  994. snd_soc_component_write(component, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
  995. /* Enable any disabled outputs */
  996. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f03);
  997. /* Disable VMID */
  998. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x1f01);
  999. msleep(300);
  1000. /* Enable all output discharge bits */
  1001. snd_soc_component_write(component, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
  1002. WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
  1003. WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
  1004. WM8991_DIS_ROUT);
  1005. /* Disable VREF */
  1006. snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_1, 0x0);
  1007. /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
  1008. snd_soc_component_write(component, WM8991_ANTIPOP2, 0x0);
  1009. regcache_mark_dirty(wm8991->regmap);
  1010. break;
  1011. }
  1012. return 0;
  1013. }
  1014. #define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1015. SNDRV_PCM_FMTBIT_S24_LE)
  1016. static const struct snd_soc_dai_ops wm8991_ops = {
  1017. .hw_params = wm8991_hw_params,
  1018. .mute_stream = wm8991_mute,
  1019. .set_fmt = wm8991_set_dai_fmt,
  1020. .set_clkdiv = wm8991_set_dai_clkdiv,
  1021. .set_pll = wm8991_set_dai_pll,
  1022. .no_capture_mute = 1,
  1023. };
  1024. /*
  1025. * The WM8991 supports 2 different and mutually exclusive DAI
  1026. * configurations.
  1027. *
  1028. * 1. ADC/DAC on Primary Interface
  1029. * 2. ADC on Primary Interface/DAC on secondary
  1030. */
  1031. static struct snd_soc_dai_driver wm8991_dai = {
  1032. /* ADC/DAC on primary */
  1033. .name = "wm8991",
  1034. .id = 1,
  1035. .playback = {
  1036. .stream_name = "Playback",
  1037. .channels_min = 1,
  1038. .channels_max = 2,
  1039. .rates = SNDRV_PCM_RATE_8000_96000,
  1040. .formats = WM8991_FORMATS
  1041. },
  1042. .capture = {
  1043. .stream_name = "Capture",
  1044. .channels_min = 1,
  1045. .channels_max = 2,
  1046. .rates = SNDRV_PCM_RATE_8000_96000,
  1047. .formats = WM8991_FORMATS
  1048. },
  1049. .ops = &wm8991_ops
  1050. };
  1051. static const struct snd_soc_component_driver soc_component_dev_wm8991 = {
  1052. .set_bias_level = wm8991_set_bias_level,
  1053. .controls = wm8991_snd_controls,
  1054. .num_controls = ARRAY_SIZE(wm8991_snd_controls),
  1055. .dapm_widgets = wm8991_dapm_widgets,
  1056. .num_dapm_widgets = ARRAY_SIZE(wm8991_dapm_widgets),
  1057. .dapm_routes = wm8991_dapm_routes,
  1058. .num_dapm_routes = ARRAY_SIZE(wm8991_dapm_routes),
  1059. .suspend_bias_off = 1,
  1060. .idle_bias_on = 1,
  1061. .use_pmdown_time = 1,
  1062. .endianness = 1,
  1063. .non_legacy_dai_naming = 1,
  1064. };
  1065. static const struct regmap_config wm8991_regmap = {
  1066. .reg_bits = 8,
  1067. .val_bits = 16,
  1068. .max_register = WM8991_PLL3,
  1069. .volatile_reg = wm8991_volatile,
  1070. .reg_defaults = wm8991_reg_defaults,
  1071. .num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults),
  1072. .cache_type = REGCACHE_RBTREE,
  1073. };
  1074. static int wm8991_i2c_probe(struct i2c_client *i2c,
  1075. const struct i2c_device_id *id)
  1076. {
  1077. struct wm8991_priv *wm8991;
  1078. unsigned int val;
  1079. int ret;
  1080. wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL);
  1081. if (!wm8991)
  1082. return -ENOMEM;
  1083. wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap);
  1084. if (IS_ERR(wm8991->regmap))
  1085. return PTR_ERR(wm8991->regmap);
  1086. i2c_set_clientdata(i2c, wm8991);
  1087. ret = regmap_read(wm8991->regmap, WM8991_RESET, &val);
  1088. if (ret != 0) {
  1089. dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret);
  1090. return ret;
  1091. }
  1092. if (val != 0x8991) {
  1093. dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val);
  1094. return -EINVAL;
  1095. }
  1096. ret = regmap_write(wm8991->regmap, WM8991_RESET, 0);
  1097. if (ret < 0) {
  1098. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  1099. return ret;
  1100. }
  1101. regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4,
  1102. WM8991_ALRCGPIO1, WM8991_ALRCGPIO1);
  1103. regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2,
  1104. WM8991_GPIO1_SEL_MASK, 1);
  1105. regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1,
  1106. WM8991_VREF_ENA | WM8991_VMID_MODE_MASK,
  1107. WM8991_VREF_ENA | WM8991_VMID_MODE_MASK);
  1108. regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2,
  1109. WM8991_OPCLK_ENA, WM8991_OPCLK_ENA);
  1110. regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0);
  1111. regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME,
  1112. 0x50 | (1<<8));
  1113. regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME,
  1114. 0x50 | (1<<8));
  1115. ret = devm_snd_soc_register_component(&i2c->dev,
  1116. &soc_component_dev_wm8991, &wm8991_dai, 1);
  1117. return ret;
  1118. }
  1119. static const struct i2c_device_id wm8991_i2c_id[] = {
  1120. { "wm8991", 0 },
  1121. { }
  1122. };
  1123. MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id);
  1124. static struct i2c_driver wm8991_i2c_driver = {
  1125. .driver = {
  1126. .name = "wm8991",
  1127. },
  1128. .probe = wm8991_i2c_probe,
  1129. .id_table = wm8991_i2c_id,
  1130. };
  1131. module_i2c_driver(wm8991_i2c_driver);
  1132. MODULE_DESCRIPTION("ASoC WM8991 driver");
  1133. MODULE_AUTHOR("Graeme Gregory");
  1134. MODULE_LICENSE("GPL");