wm8985.h 60 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * wm8985.h -- WM8985 ASoC driver
  4. *
  5. * Copyright 2010 Wolfson Microelectronics plc
  6. *
  7. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  8. */
  9. #ifndef _WM8985_H
  10. #define _WM8985_H
  11. #define WM8985_SOFTWARE_RESET 0x00
  12. #define WM8985_POWER_MANAGEMENT_1 0x01
  13. #define WM8985_POWER_MANAGEMENT_2 0x02
  14. #define WM8985_POWER_MANAGEMENT_3 0x03
  15. #define WM8985_AUDIO_INTERFACE 0x04
  16. #define WM8985_COMPANDING_CONTROL 0x05
  17. #define WM8985_CLOCK_GEN_CONTROL 0x06
  18. #define WM8985_ADDITIONAL_CONTROL 0x07
  19. #define WM8985_GPIO_CONTROL 0x08
  20. #define WM8985_JACK_DETECT_CONTROL_1 0x09
  21. #define WM8985_DAC_CONTROL 0x0A
  22. #define WM8985_LEFT_DAC_DIGITAL_VOL 0x0B
  23. #define WM8985_RIGHT_DAC_DIGITAL_VOL 0x0C
  24. #define WM8985_JACK_DETECT_CONTROL_2 0x0D
  25. #define WM8985_ADC_CONTROL 0x0E
  26. #define WM8985_LEFT_ADC_DIGITAL_VOL 0x0F
  27. #define WM8985_RIGHT_ADC_DIGITAL_VOL 0x10
  28. #define WM8985_EQ1_LOW_SHELF 0x12
  29. #define WM8985_EQ2_PEAK_1 0x13
  30. #define WM8985_EQ3_PEAK_2 0x14
  31. #define WM8985_EQ4_PEAK_3 0x15
  32. #define WM8985_EQ5_HIGH_SHELF 0x16
  33. #define WM8985_DAC_LIMITER_1 0x18
  34. #define WM8985_DAC_LIMITER_2 0x19
  35. #define WM8985_NOTCH_FILTER_1 0x1B
  36. #define WM8985_NOTCH_FILTER_2 0x1C
  37. #define WM8985_NOTCH_FILTER_3 0x1D
  38. #define WM8985_NOTCH_FILTER_4 0x1E
  39. #define WM8985_ALC_CONTROL_1 0x20
  40. #define WM8985_ALC_CONTROL_2 0x21
  41. #define WM8985_ALC_CONTROL_3 0x22
  42. #define WM8985_NOISE_GATE 0x23
  43. #define WM8985_PLL_N 0x24
  44. #define WM8985_PLL_K_1 0x25
  45. #define WM8985_PLL_K_2 0x26
  46. #define WM8985_PLL_K_3 0x27
  47. #define WM8985_3D_CONTROL 0x29
  48. #define WM8985_OUT4_TO_ADC 0x2A
  49. #define WM8985_BEEP_CONTROL 0x2B
  50. #define WM8985_INPUT_CTRL 0x2C
  51. #define WM8985_LEFT_INP_PGA_GAIN_CTRL 0x2D
  52. #define WM8985_RIGHT_INP_PGA_GAIN_CTRL 0x2E
  53. #define WM8985_LEFT_ADC_BOOST_CTRL 0x2F
  54. #define WM8985_RIGHT_ADC_BOOST_CTRL 0x30
  55. #define WM8985_OUTPUT_CTRL0 0x31
  56. #define WM8985_LEFT_MIXER_CTRL 0x32
  57. #define WM8985_RIGHT_MIXER_CTRL 0x33
  58. #define WM8985_LOUT1_HP_VOLUME_CTRL 0x34
  59. #define WM8985_ROUT1_HP_VOLUME_CTRL 0x35
  60. #define WM8985_LOUT2_SPK_VOLUME_CTRL 0x36
  61. #define WM8985_ROUT2_SPK_VOLUME_CTRL 0x37
  62. #define WM8985_OUT3_MIXER_CTRL 0x38
  63. #define WM8985_OUT4_MONO_MIX_CTRL 0x39
  64. #define WM8985_OUTPUT_CTRL1 0x3C
  65. #define WM8985_BIAS_CTRL 0x3D
  66. #define WM8985_REGISTER_COUNT 59
  67. #define WM8985_MAX_REGISTER 0x3F
  68. /*
  69. * Field Definitions.
  70. */
  71. /*
  72. * R0 (0x00) - Software Reset
  73. */
  74. #define WM8985_SOFTWARE_RESET_MASK 0x01FF /* SOFTWARE_RESET - [8:0] */
  75. #define WM8985_SOFTWARE_RESET_SHIFT 0 /* SOFTWARE_RESET - [8:0] */
  76. #define WM8985_SOFTWARE_RESET_WIDTH 9 /* SOFTWARE_RESET - [8:0] */
  77. /*
  78. * R1 (0x01) - Power management 1
  79. */
  80. #define WM8985_OUT4MIXEN 0x0080 /* OUT4MIXEN */
  81. #define WM8985_OUT4MIXEN_MASK 0x0080 /* OUT4MIXEN */
  82. #define WM8985_OUT4MIXEN_SHIFT 7 /* OUT4MIXEN */
  83. #define WM8985_OUT4MIXEN_WIDTH 1 /* OUT4MIXEN */
  84. #define WM8985_OUT3MIXEN 0x0040 /* OUT3MIXEN */
  85. #define WM8985_OUT3MIXEN_MASK 0x0040 /* OUT3MIXEN */
  86. #define WM8985_OUT3MIXEN_SHIFT 6 /* OUT3MIXEN */
  87. #define WM8985_OUT3MIXEN_WIDTH 1 /* OUT3MIXEN */
  88. #define WM8985_PLLEN 0x0020 /* PLLEN */
  89. #define WM8985_PLLEN_MASK 0x0020 /* PLLEN */
  90. #define WM8985_PLLEN_SHIFT 5 /* PLLEN */
  91. #define WM8985_PLLEN_WIDTH 1 /* PLLEN */
  92. #define WM8985_MICBEN 0x0010 /* MICBEN */
  93. #define WM8985_MICBEN_MASK 0x0010 /* MICBEN */
  94. #define WM8985_MICBEN_SHIFT 4 /* MICBEN */
  95. #define WM8985_MICBEN_WIDTH 1 /* MICBEN */
  96. #define WM8985_BIASEN 0x0008 /* BIASEN */
  97. #define WM8985_BIASEN_MASK 0x0008 /* BIASEN */
  98. #define WM8985_BIASEN_SHIFT 3 /* BIASEN */
  99. #define WM8985_BIASEN_WIDTH 1 /* BIASEN */
  100. #define WM8985_BUFIOEN 0x0004 /* BUFIOEN */
  101. #define WM8985_BUFIOEN_MASK 0x0004 /* BUFIOEN */
  102. #define WM8985_BUFIOEN_SHIFT 2 /* BUFIOEN */
  103. #define WM8985_BUFIOEN_WIDTH 1 /* BUFIOEN */
  104. #define WM8985_VMIDSEL 0x0003 /* VMIDSEL */
  105. #define WM8985_VMIDSEL_MASK 0x0003 /* VMIDSEL - [1:0] */
  106. #define WM8985_VMIDSEL_SHIFT 0 /* VMIDSEL - [1:0] */
  107. #define WM8985_VMIDSEL_WIDTH 2 /* VMIDSEL - [1:0] */
  108. /*
  109. * R2 (0x02) - Power management 2
  110. */
  111. #define WM8985_ROUT1EN 0x0100 /* ROUT1EN */
  112. #define WM8985_ROUT1EN_MASK 0x0100 /* ROUT1EN */
  113. #define WM8985_ROUT1EN_SHIFT 8 /* ROUT1EN */
  114. #define WM8985_ROUT1EN_WIDTH 1 /* ROUT1EN */
  115. #define WM8985_LOUT1EN 0x0080 /* LOUT1EN */
  116. #define WM8985_LOUT1EN_MASK 0x0080 /* LOUT1EN */
  117. #define WM8985_LOUT1EN_SHIFT 7 /* LOUT1EN */
  118. #define WM8985_LOUT1EN_WIDTH 1 /* LOUT1EN */
  119. #define WM8985_SLEEP 0x0040 /* SLEEP */
  120. #define WM8985_SLEEP_MASK 0x0040 /* SLEEP */
  121. #define WM8985_SLEEP_SHIFT 6 /* SLEEP */
  122. #define WM8985_SLEEP_WIDTH 1 /* SLEEP */
  123. #define WM8985_BOOSTENR 0x0020 /* BOOSTENR */
  124. #define WM8985_BOOSTENR_MASK 0x0020 /* BOOSTENR */
  125. #define WM8985_BOOSTENR_SHIFT 5 /* BOOSTENR */
  126. #define WM8985_BOOSTENR_WIDTH 1 /* BOOSTENR */
  127. #define WM8985_BOOSTENL 0x0010 /* BOOSTENL */
  128. #define WM8985_BOOSTENL_MASK 0x0010 /* BOOSTENL */
  129. #define WM8985_BOOSTENL_SHIFT 4 /* BOOSTENL */
  130. #define WM8985_BOOSTENL_WIDTH 1 /* BOOSTENL */
  131. #define WM8985_INPGAENR 0x0008 /* INPGAENR */
  132. #define WM8985_INPGAENR_MASK 0x0008 /* INPGAENR */
  133. #define WM8985_INPGAENR_SHIFT 3 /* INPGAENR */
  134. #define WM8985_INPGAENR_WIDTH 1 /* INPGAENR */
  135. #define WM8985_INPPGAENL 0x0004 /* INPPGAENL */
  136. #define WM8985_INPPGAENL_MASK 0x0004 /* INPPGAENL */
  137. #define WM8985_INPPGAENL_SHIFT 2 /* INPPGAENL */
  138. #define WM8985_INPPGAENL_WIDTH 1 /* INPPGAENL */
  139. #define WM8985_ADCENR 0x0002 /* ADCENR */
  140. #define WM8985_ADCENR_MASK 0x0002 /* ADCENR */
  141. #define WM8985_ADCENR_SHIFT 1 /* ADCENR */
  142. #define WM8985_ADCENR_WIDTH 1 /* ADCENR */
  143. #define WM8985_ADCENL 0x0001 /* ADCENL */
  144. #define WM8985_ADCENL_MASK 0x0001 /* ADCENL */
  145. #define WM8985_ADCENL_SHIFT 0 /* ADCENL */
  146. #define WM8985_ADCENL_WIDTH 1 /* ADCENL */
  147. /*
  148. * R3 (0x03) - Power management 3
  149. */
  150. #define WM8985_OUT4EN 0x0100 /* OUT4EN */
  151. #define WM8985_OUT4EN_MASK 0x0100 /* OUT4EN */
  152. #define WM8985_OUT4EN_SHIFT 8 /* OUT4EN */
  153. #define WM8985_OUT4EN_WIDTH 1 /* OUT4EN */
  154. #define WM8985_OUT3EN 0x0080 /* OUT3EN */
  155. #define WM8985_OUT3EN_MASK 0x0080 /* OUT3EN */
  156. #define WM8985_OUT3EN_SHIFT 7 /* OUT3EN */
  157. #define WM8985_OUT3EN_WIDTH 1 /* OUT3EN */
  158. #define WM8985_ROUT2EN 0x0040 /* ROUT2EN */
  159. #define WM8985_ROUT2EN_MASK 0x0040 /* ROUT2EN */
  160. #define WM8985_ROUT2EN_SHIFT 6 /* ROUT2EN */
  161. #define WM8985_ROUT2EN_WIDTH 1 /* ROUT2EN */
  162. #define WM8985_LOUT2EN 0x0020 /* LOUT2EN */
  163. #define WM8985_LOUT2EN_MASK 0x0020 /* LOUT2EN */
  164. #define WM8985_LOUT2EN_SHIFT 5 /* LOUT2EN */
  165. #define WM8985_LOUT2EN_WIDTH 1 /* LOUT2EN */
  166. #define WM8985_RMIXEN 0x0008 /* RMIXEN */
  167. #define WM8985_RMIXEN_MASK 0x0008 /* RMIXEN */
  168. #define WM8985_RMIXEN_SHIFT 3 /* RMIXEN */
  169. #define WM8985_RMIXEN_WIDTH 1 /* RMIXEN */
  170. #define WM8985_LMIXEN 0x0004 /* LMIXEN */
  171. #define WM8985_LMIXEN_MASK 0x0004 /* LMIXEN */
  172. #define WM8985_LMIXEN_SHIFT 2 /* LMIXEN */
  173. #define WM8985_LMIXEN_WIDTH 1 /* LMIXEN */
  174. #define WM8985_DACENR 0x0002 /* DACENR */
  175. #define WM8985_DACENR_MASK 0x0002 /* DACENR */
  176. #define WM8985_DACENR_SHIFT 1 /* DACENR */
  177. #define WM8985_DACENR_WIDTH 1 /* DACENR */
  178. #define WM8985_DACENL 0x0001 /* DACENL */
  179. #define WM8985_DACENL_MASK 0x0001 /* DACENL */
  180. #define WM8985_DACENL_SHIFT 0 /* DACENL */
  181. #define WM8985_DACENL_WIDTH 1 /* DACENL */
  182. /*
  183. * R4 (0x04) - Audio Interface
  184. */
  185. #define WM8985_BCP 0x0100 /* BCP */
  186. #define WM8985_BCP_MASK 0x0100 /* BCP */
  187. #define WM8985_BCP_SHIFT 8 /* BCP */
  188. #define WM8985_BCP_WIDTH 1 /* BCP */
  189. #define WM8985_LRP 0x0080 /* LRP */
  190. #define WM8985_LRP_MASK 0x0080 /* LRP */
  191. #define WM8985_LRP_SHIFT 7 /* LRP */
  192. #define WM8985_LRP_WIDTH 1 /* LRP */
  193. #define WM8985_WL_MASK 0x0060 /* WL - [6:5] */
  194. #define WM8985_WL_SHIFT 5 /* WL - [6:5] */
  195. #define WM8985_WL_WIDTH 2 /* WL - [6:5] */
  196. #define WM8985_FMT_MASK 0x0018 /* FMT - [4:3] */
  197. #define WM8985_FMT_SHIFT 3 /* FMT - [4:3] */
  198. #define WM8985_FMT_WIDTH 2 /* FMT - [4:3] */
  199. #define WM8985_DLRSWAP 0x0004 /* DLRSWAP */
  200. #define WM8985_DLRSWAP_MASK 0x0004 /* DLRSWAP */
  201. #define WM8985_DLRSWAP_SHIFT 2 /* DLRSWAP */
  202. #define WM8985_DLRSWAP_WIDTH 1 /* DLRSWAP */
  203. #define WM8985_ALRSWAP 0x0002 /* ALRSWAP */
  204. #define WM8985_ALRSWAP_MASK 0x0002 /* ALRSWAP */
  205. #define WM8985_ALRSWAP_SHIFT 1 /* ALRSWAP */
  206. #define WM8985_ALRSWAP_WIDTH 1 /* ALRSWAP */
  207. #define WM8985_MONO 0x0001 /* MONO */
  208. #define WM8985_MONO_MASK 0x0001 /* MONO */
  209. #define WM8985_MONO_SHIFT 0 /* MONO */
  210. #define WM8985_MONO_WIDTH 1 /* MONO */
  211. /*
  212. * R5 (0x05) - Companding control
  213. */
  214. #define WM8985_WL8 0x0020 /* WL8 */
  215. #define WM8985_WL8_MASK 0x0020 /* WL8 */
  216. #define WM8985_WL8_SHIFT 5 /* WL8 */
  217. #define WM8985_WL8_WIDTH 1 /* WL8 */
  218. #define WM8985_DAC_COMP_MASK 0x0018 /* DAC_COMP - [4:3] */
  219. #define WM8985_DAC_COMP_SHIFT 3 /* DAC_COMP - [4:3] */
  220. #define WM8985_DAC_COMP_WIDTH 2 /* DAC_COMP - [4:3] */
  221. #define WM8985_ADC_COMP_MASK 0x0006 /* ADC_COMP - [2:1] */
  222. #define WM8985_ADC_COMP_SHIFT 1 /* ADC_COMP - [2:1] */
  223. #define WM8985_ADC_COMP_WIDTH 2 /* ADC_COMP - [2:1] */
  224. #define WM8985_LOOPBACK 0x0001 /* LOOPBACK */
  225. #define WM8985_LOOPBACK_MASK 0x0001 /* LOOPBACK */
  226. #define WM8985_LOOPBACK_SHIFT 0 /* LOOPBACK */
  227. #define WM8985_LOOPBACK_WIDTH 1 /* LOOPBACK */
  228. /*
  229. * R6 (0x06) - Clock Gen control
  230. */
  231. #define WM8985_CLKSEL 0x0100 /* CLKSEL */
  232. #define WM8985_CLKSEL_MASK 0x0100 /* CLKSEL */
  233. #define WM8985_CLKSEL_SHIFT 8 /* CLKSEL */
  234. #define WM8985_CLKSEL_WIDTH 1 /* CLKSEL */
  235. #define WM8985_MCLKDIV_MASK 0x00E0 /* MCLKDIV - [7:5] */
  236. #define WM8985_MCLKDIV_SHIFT 5 /* MCLKDIV - [7:5] */
  237. #define WM8985_MCLKDIV_WIDTH 3 /* MCLKDIV - [7:5] */
  238. #define WM8985_BCLKDIV_MASK 0x001C /* BCLKDIV - [4:2] */
  239. #define WM8985_BCLKDIV_SHIFT 2 /* BCLKDIV - [4:2] */
  240. #define WM8985_BCLKDIV_WIDTH 3 /* BCLKDIV - [4:2] */
  241. #define WM8985_MS 0x0001 /* MS */
  242. #define WM8985_MS_MASK 0x0001 /* MS */
  243. #define WM8985_MS_SHIFT 0 /* MS */
  244. #define WM8985_MS_WIDTH 1 /* MS */
  245. /*
  246. * R7 (0x07) - Additional control
  247. */
  248. #define WM8985_M128ENB 0x0100 /* M128ENB */
  249. #define WM8985_M128ENB_MASK 0x0100 /* M128ENB */
  250. #define WM8985_M128ENB_SHIFT 8 /* M128ENB */
  251. #define WM8985_M128ENB_WIDTH 1 /* M128ENB */
  252. #define WM8985_DCLKDIV_MASK 0x00F0 /* DCLKDIV - [7:4] */
  253. #define WM8985_DCLKDIV_SHIFT 4 /* DCLKDIV - [7:4] */
  254. #define WM8985_DCLKDIV_WIDTH 4 /* DCLKDIV - [7:4] */
  255. #define WM8985_SR_MASK 0x000E /* SR - [3:1] */
  256. #define WM8985_SR_SHIFT 1 /* SR - [3:1] */
  257. #define WM8985_SR_WIDTH 3 /* SR - [3:1] */
  258. #define WM8985_SLOWCLKEN 0x0001 /* SLOWCLKEN */
  259. #define WM8985_SLOWCLKEN_MASK 0x0001 /* SLOWCLKEN */
  260. #define WM8985_SLOWCLKEN_SHIFT 0 /* SLOWCLKEN */
  261. #define WM8985_SLOWCLKEN_WIDTH 1 /* SLOWCLKEN */
  262. /*
  263. * R8 (0x08) - GPIO Control
  264. */
  265. #define WM8985_GPIO1GP 0x0100 /* GPIO1GP */
  266. #define WM8985_GPIO1GP_MASK 0x0100 /* GPIO1GP */
  267. #define WM8985_GPIO1GP_SHIFT 8 /* GPIO1GP */
  268. #define WM8985_GPIO1GP_WIDTH 1 /* GPIO1GP */
  269. #define WM8985_GPIO1GPU 0x0080 /* GPIO1GPU */
  270. #define WM8985_GPIO1GPU_MASK 0x0080 /* GPIO1GPU */
  271. #define WM8985_GPIO1GPU_SHIFT 7 /* GPIO1GPU */
  272. #define WM8985_GPIO1GPU_WIDTH 1 /* GPIO1GPU */
  273. #define WM8985_GPIO1GPD 0x0040 /* GPIO1GPD */
  274. #define WM8985_GPIO1GPD_MASK 0x0040 /* GPIO1GPD */
  275. #define WM8985_GPIO1GPD_SHIFT 6 /* GPIO1GPD */
  276. #define WM8985_GPIO1GPD_WIDTH 1 /* GPIO1GPD */
  277. #define WM8758_OPCLKDIV_MASK 0x0030 /* OPCLKDIV - [1:0] */
  278. #define WM8758_OPCLKDIV_SHIFT 4 /* OPCLKDIV - [1:0] */
  279. #define WM8758_OPCLKDIV_WIDTH 2 /* OPCLKDIV - [1:0] */
  280. #define WM8985_GPIO1POL 0x0008 /* GPIO1POL */
  281. #define WM8985_GPIO1POL_MASK 0x0008 /* GPIO1POL */
  282. #define WM8985_GPIO1POL_SHIFT 3 /* GPIO1POL */
  283. #define WM8985_GPIO1POL_WIDTH 1 /* GPIO1POL */
  284. #define WM8985_GPIO1SEL_MASK 0x0007 /* GPIO1SEL - [2:0] */
  285. #define WM8985_GPIO1SEL_SHIFT 0 /* GPIO1SEL - [2:0] */
  286. #define WM8985_GPIO1SEL_WIDTH 3 /* GPIO1SEL - [2:0] */
  287. /*
  288. * R9 (0x09) - Jack Detect Control 1
  289. */
  290. #define WM8758_JD_VMID1_MASK 0x0100 /* JD_VMID1 */
  291. #define WM8758_JD_VMID1_SHIFT 8 /* JD_VMID1 */
  292. #define WM8758_JD_VMID1_WIDTH 1 /* JD_VMID1 */
  293. #define WM8758_JD_VMID0_MASK 0x0080 /* JD_VMID0 */
  294. #define WM8758_JD_VMID0_SHIFT 7 /* JD_VMID0 */
  295. #define WM8758_JD_VMID0_WIDTH 1 /* JD_VMID0 */
  296. #define WM8985_JD_EN 0x0040 /* JD_EN */
  297. #define WM8985_JD_EN_MASK 0x0040 /* JD_EN */
  298. #define WM8985_JD_EN_SHIFT 6 /* JD_EN */
  299. #define WM8985_JD_EN_WIDTH 1 /* JD_EN */
  300. #define WM8985_JD_SEL_MASK 0x0030 /* JD_SEL - [5:4] */
  301. #define WM8985_JD_SEL_SHIFT 4 /* JD_SEL - [5:4] */
  302. #define WM8985_JD_SEL_WIDTH 2 /* JD_SEL - [5:4] */
  303. /*
  304. * R10 (0x0A) - DAC Control
  305. */
  306. #define WM8985_SOFTMUTE 0x0040 /* SOFTMUTE */
  307. #define WM8985_SOFTMUTE_MASK 0x0040 /* SOFTMUTE */
  308. #define WM8985_SOFTMUTE_SHIFT 6 /* SOFTMUTE */
  309. #define WM8985_SOFTMUTE_WIDTH 1 /* SOFTMUTE */
  310. #define WM8985_DACOSR128 0x0008 /* DACOSR128 */
  311. #define WM8985_DACOSR128_MASK 0x0008 /* DACOSR128 */
  312. #define WM8985_DACOSR128_SHIFT 3 /* DACOSR128 */
  313. #define WM8985_DACOSR128_WIDTH 1 /* DACOSR128 */
  314. #define WM8985_AMUTE 0x0004 /* AMUTE */
  315. #define WM8985_AMUTE_MASK 0x0004 /* AMUTE */
  316. #define WM8985_AMUTE_SHIFT 2 /* AMUTE */
  317. #define WM8985_AMUTE_WIDTH 1 /* AMUTE */
  318. #define WM8985_DACPOLR 0x0002 /* DACPOLR */
  319. #define WM8985_DACPOLR_MASK 0x0002 /* DACPOLR */
  320. #define WM8985_DACPOLR_SHIFT 1 /* DACPOLR */
  321. #define WM8985_DACPOLR_WIDTH 1 /* DACPOLR */
  322. #define WM8985_DACPOLL 0x0001 /* DACPOLL */
  323. #define WM8985_DACPOLL_MASK 0x0001 /* DACPOLL */
  324. #define WM8985_DACPOLL_SHIFT 0 /* DACPOLL */
  325. #define WM8985_DACPOLL_WIDTH 1 /* DACPOLL */
  326. /*
  327. * R11 (0x0B) - Left DAC digital Vol
  328. */
  329. #define WM8985_DACVU 0x0100 /* DACVU */
  330. #define WM8985_DACVU_MASK 0x0100 /* DACVU */
  331. #define WM8985_DACVU_SHIFT 8 /* DACVU */
  332. #define WM8985_DACVU_WIDTH 1 /* DACVU */
  333. #define WM8985_DACVOLL_MASK 0x00FF /* DACVOLL - [7:0] */
  334. #define WM8985_DACVOLL_SHIFT 0 /* DACVOLL - [7:0] */
  335. #define WM8985_DACVOLL_WIDTH 8 /* DACVOLL - [7:0] */
  336. /*
  337. * R12 (0x0C) - Right DAC digital vol
  338. */
  339. #define WM8985_DACVU 0x0100 /* DACVU */
  340. #define WM8985_DACVU_MASK 0x0100 /* DACVU */
  341. #define WM8985_DACVU_SHIFT 8 /* DACVU */
  342. #define WM8985_DACVU_WIDTH 1 /* DACVU */
  343. #define WM8985_DACVOLR_MASK 0x00FF /* DACVOLR - [7:0] */
  344. #define WM8985_DACVOLR_SHIFT 0 /* DACVOLR - [7:0] */
  345. #define WM8985_DACVOLR_WIDTH 8 /* DACVOLR - [7:0] */
  346. /*
  347. * R13 (0x0D) - Jack Detect Control 2
  348. */
  349. #define WM8985_JD_EN1_MASK 0x00F0 /* JD_EN1 - [7:4] */
  350. #define WM8985_JD_EN1_SHIFT 4 /* JD_EN1 - [7:4] */
  351. #define WM8985_JD_EN1_WIDTH 4 /* JD_EN1 - [7:4] */
  352. #define WM8985_JD_EN0_MASK 0x000F /* JD_EN0 - [3:0] */
  353. #define WM8985_JD_EN0_SHIFT 0 /* JD_EN0 - [3:0] */
  354. #define WM8985_JD_EN0_WIDTH 4 /* JD_EN0 - [3:0] */
  355. /*
  356. * R14 (0x0E) - ADC Control
  357. */
  358. #define WM8985_HPFEN 0x0100 /* HPFEN */
  359. #define WM8985_HPFEN_MASK 0x0100 /* HPFEN */
  360. #define WM8985_HPFEN_SHIFT 8 /* HPFEN */
  361. #define WM8985_HPFEN_WIDTH 1 /* HPFEN */
  362. #define WM8985_HPFAPP 0x0080 /* HPFAPP */
  363. #define WM8985_HPFAPP_MASK 0x0080 /* HPFAPP */
  364. #define WM8985_HPFAPP_SHIFT 7 /* HPFAPP */
  365. #define WM8985_HPFAPP_WIDTH 1 /* HPFAPP */
  366. #define WM8985_HPFCUT_MASK 0x0070 /* HPFCUT - [6:4] */
  367. #define WM8985_HPFCUT_SHIFT 4 /* HPFCUT - [6:4] */
  368. #define WM8985_HPFCUT_WIDTH 3 /* HPFCUT - [6:4] */
  369. #define WM8985_ADCOSR128 0x0008 /* ADCOSR128 */
  370. #define WM8985_ADCOSR128_MASK 0x0008 /* ADCOSR128 */
  371. #define WM8985_ADCOSR128_SHIFT 3 /* ADCOSR128 */
  372. #define WM8985_ADCOSR128_WIDTH 1 /* ADCOSR128 */
  373. #define WM8985_ADCRPOL 0x0002 /* ADCRPOL */
  374. #define WM8985_ADCRPOL_MASK 0x0002 /* ADCRPOL */
  375. #define WM8985_ADCRPOL_SHIFT 1 /* ADCRPOL */
  376. #define WM8985_ADCRPOL_WIDTH 1 /* ADCRPOL */
  377. #define WM8985_ADCLPOL 0x0001 /* ADCLPOL */
  378. #define WM8985_ADCLPOL_MASK 0x0001 /* ADCLPOL */
  379. #define WM8985_ADCLPOL_SHIFT 0 /* ADCLPOL */
  380. #define WM8985_ADCLPOL_WIDTH 1 /* ADCLPOL */
  381. /*
  382. * R15 (0x0F) - Left ADC Digital Vol
  383. */
  384. #define WM8985_ADCVU 0x0100 /* ADCVU */
  385. #define WM8985_ADCVU_MASK 0x0100 /* ADCVU */
  386. #define WM8985_ADCVU_SHIFT 8 /* ADCVU */
  387. #define WM8985_ADCVU_WIDTH 1 /* ADCVU */
  388. #define WM8985_ADCVOLL_MASK 0x00FF /* ADCVOLL - [7:0] */
  389. #define WM8985_ADCVOLL_SHIFT 0 /* ADCVOLL - [7:0] */
  390. #define WM8985_ADCVOLL_WIDTH 8 /* ADCVOLL - [7:0] */
  391. /*
  392. * R16 (0x10) - Right ADC Digital Vol
  393. */
  394. #define WM8985_ADCVU 0x0100 /* ADCVU */
  395. #define WM8985_ADCVU_MASK 0x0100 /* ADCVU */
  396. #define WM8985_ADCVU_SHIFT 8 /* ADCVU */
  397. #define WM8985_ADCVU_WIDTH 1 /* ADCVU */
  398. #define WM8985_ADCVOLR_MASK 0x00FF /* ADCVOLR - [7:0] */
  399. #define WM8985_ADCVOLR_SHIFT 0 /* ADCVOLR - [7:0] */
  400. #define WM8985_ADCVOLR_WIDTH 8 /* ADCVOLR - [7:0] */
  401. /*
  402. * R18 (0x12) - EQ1 - low shelf
  403. */
  404. #define WM8985_EQ3DMODE 0x0100 /* EQ3DMODE */
  405. #define WM8985_EQ3DMODE_MASK 0x0100 /* EQ3DMODE */
  406. #define WM8985_EQ3DMODE_SHIFT 8 /* EQ3DMODE */
  407. #define WM8985_EQ3DMODE_WIDTH 1 /* EQ3DMODE */
  408. #define WM8985_EQ1C_MASK 0x0060 /* EQ1C - [6:5] */
  409. #define WM8985_EQ1C_SHIFT 5 /* EQ1C - [6:5] */
  410. #define WM8985_EQ1C_WIDTH 2 /* EQ1C - [6:5] */
  411. #define WM8985_EQ1G_MASK 0x001F /* EQ1G - [4:0] */
  412. #define WM8985_EQ1G_SHIFT 0 /* EQ1G - [4:0] */
  413. #define WM8985_EQ1G_WIDTH 5 /* EQ1G - [4:0] */
  414. /*
  415. * R19 (0x13) - EQ2 - peak 1
  416. */
  417. #define WM8985_EQ2BW 0x0100 /* EQ2BW */
  418. #define WM8985_EQ2BW_MASK 0x0100 /* EQ2BW */
  419. #define WM8985_EQ2BW_SHIFT 8 /* EQ2BW */
  420. #define WM8985_EQ2BW_WIDTH 1 /* EQ2BW */
  421. #define WM8985_EQ2C_MASK 0x0060 /* EQ2C - [6:5] */
  422. #define WM8985_EQ2C_SHIFT 5 /* EQ2C - [6:5] */
  423. #define WM8985_EQ2C_WIDTH 2 /* EQ2C - [6:5] */
  424. #define WM8985_EQ2G_MASK 0x001F /* EQ2G - [4:0] */
  425. #define WM8985_EQ2G_SHIFT 0 /* EQ2G - [4:0] */
  426. #define WM8985_EQ2G_WIDTH 5 /* EQ2G - [4:0] */
  427. /*
  428. * R20 (0x14) - EQ3 - peak 2
  429. */
  430. #define WM8985_EQ3BW 0x0100 /* EQ3BW */
  431. #define WM8985_EQ3BW_MASK 0x0100 /* EQ3BW */
  432. #define WM8985_EQ3BW_SHIFT 8 /* EQ3BW */
  433. #define WM8985_EQ3BW_WIDTH 1 /* EQ3BW */
  434. #define WM8985_EQ3C_MASK 0x0060 /* EQ3C - [6:5] */
  435. #define WM8985_EQ3C_SHIFT 5 /* EQ3C - [6:5] */
  436. #define WM8985_EQ3C_WIDTH 2 /* EQ3C - [6:5] */
  437. #define WM8985_EQ3G_MASK 0x001F /* EQ3G - [4:0] */
  438. #define WM8985_EQ3G_SHIFT 0 /* EQ3G - [4:0] */
  439. #define WM8985_EQ3G_WIDTH 5 /* EQ3G - [4:0] */
  440. /*
  441. * R21 (0x15) - EQ4 - peak 3
  442. */
  443. #define WM8985_EQ4BW 0x0100 /* EQ4BW */
  444. #define WM8985_EQ4BW_MASK 0x0100 /* EQ4BW */
  445. #define WM8985_EQ4BW_SHIFT 8 /* EQ4BW */
  446. #define WM8985_EQ4BW_WIDTH 1 /* EQ4BW */
  447. #define WM8985_EQ4C_MASK 0x0060 /* EQ4C - [6:5] */
  448. #define WM8985_EQ4C_SHIFT 5 /* EQ4C - [6:5] */
  449. #define WM8985_EQ4C_WIDTH 2 /* EQ4C - [6:5] */
  450. #define WM8985_EQ4G_MASK 0x001F /* EQ4G - [4:0] */
  451. #define WM8985_EQ4G_SHIFT 0 /* EQ4G - [4:0] */
  452. #define WM8985_EQ4G_WIDTH 5 /* EQ4G - [4:0] */
  453. /*
  454. * R22 (0x16) - EQ5 - high shelf
  455. */
  456. #define WM8985_EQ5C_MASK 0x0060 /* EQ5C - [6:5] */
  457. #define WM8985_EQ5C_SHIFT 5 /* EQ5C - [6:5] */
  458. #define WM8985_EQ5C_WIDTH 2 /* EQ5C - [6:5] */
  459. #define WM8985_EQ5G_MASK 0x001F /* EQ5G - [4:0] */
  460. #define WM8985_EQ5G_SHIFT 0 /* EQ5G - [4:0] */
  461. #define WM8985_EQ5G_WIDTH 5 /* EQ5G - [4:0] */
  462. /*
  463. * R24 (0x18) - DAC Limiter 1
  464. */
  465. #define WM8985_LIMEN 0x0100 /* LIMEN */
  466. #define WM8985_LIMEN_MASK 0x0100 /* LIMEN */
  467. #define WM8985_LIMEN_SHIFT 8 /* LIMEN */
  468. #define WM8985_LIMEN_WIDTH 1 /* LIMEN */
  469. #define WM8985_LIMDCY_MASK 0x00F0 /* LIMDCY - [7:4] */
  470. #define WM8985_LIMDCY_SHIFT 4 /* LIMDCY - [7:4] */
  471. #define WM8985_LIMDCY_WIDTH 4 /* LIMDCY - [7:4] */
  472. #define WM8985_LIMATK_MASK 0x000F /* LIMATK - [3:0] */
  473. #define WM8985_LIMATK_SHIFT 0 /* LIMATK - [3:0] */
  474. #define WM8985_LIMATK_WIDTH 4 /* LIMATK - [3:0] */
  475. /*
  476. * R25 (0x19) - DAC Limiter 2
  477. */
  478. #define WM8985_LIMLVL_MASK 0x0070 /* LIMLVL - [6:4] */
  479. #define WM8985_LIMLVL_SHIFT 4 /* LIMLVL - [6:4] */
  480. #define WM8985_LIMLVL_WIDTH 3 /* LIMLVL - [6:4] */
  481. #define WM8985_LIMBOOST_MASK 0x000F /* LIMBOOST - [3:0] */
  482. #define WM8985_LIMBOOST_SHIFT 0 /* LIMBOOST - [3:0] */
  483. #define WM8985_LIMBOOST_WIDTH 4 /* LIMBOOST - [3:0] */
  484. /*
  485. * R27 (0x1B) - Notch Filter 1
  486. */
  487. #define WM8985_NFU 0x0100 /* NFU */
  488. #define WM8985_NFU_MASK 0x0100 /* NFU */
  489. #define WM8985_NFU_SHIFT 8 /* NFU */
  490. #define WM8985_NFU_WIDTH 1 /* NFU */
  491. #define WM8985_NFEN 0x0080 /* NFEN */
  492. #define WM8985_NFEN_MASK 0x0080 /* NFEN */
  493. #define WM8985_NFEN_SHIFT 7 /* NFEN */
  494. #define WM8985_NFEN_WIDTH 1 /* NFEN */
  495. #define WM8985_NFA0_13_7_MASK 0x007F /* NFA0(13:7) - [6:0] */
  496. #define WM8985_NFA0_13_7_SHIFT 0 /* NFA0(13:7) - [6:0] */
  497. #define WM8985_NFA0_13_7_WIDTH 7 /* NFA0(13:7) - [6:0] */
  498. /*
  499. * R28 (0x1C) - Notch Filter 2
  500. */
  501. #define WM8985_NFU 0x0100 /* NFU */
  502. #define WM8985_NFU_MASK 0x0100 /* NFU */
  503. #define WM8985_NFU_SHIFT 8 /* NFU */
  504. #define WM8985_NFU_WIDTH 1 /* NFU */
  505. #define WM8985_NFA0_6_0_MASK 0x007F /* NFA0(6:0) - [6:0] */
  506. #define WM8985_NFA0_6_0_SHIFT 0 /* NFA0(6:0) - [6:0] */
  507. #define WM8985_NFA0_6_0_WIDTH 7 /* NFA0(6:0) - [6:0] */
  508. /*
  509. * R29 (0x1D) - Notch Filter 3
  510. */
  511. #define WM8985_NFU 0x0100 /* NFU */
  512. #define WM8985_NFU_MASK 0x0100 /* NFU */
  513. #define WM8985_NFU_SHIFT 8 /* NFU */
  514. #define WM8985_NFU_WIDTH 1 /* NFU */
  515. #define WM8985_NFA1_13_7_MASK 0x007F /* NFA1(13:7) - [6:0] */
  516. #define WM8985_NFA1_13_7_SHIFT 0 /* NFA1(13:7) - [6:0] */
  517. #define WM8985_NFA1_13_7_WIDTH 7 /* NFA1(13:7) - [6:0] */
  518. /*
  519. * R30 (0x1E) - Notch Filter 4
  520. */
  521. #define WM8985_NFU 0x0100 /* NFU */
  522. #define WM8985_NFU_MASK 0x0100 /* NFU */
  523. #define WM8985_NFU_SHIFT 8 /* NFU */
  524. #define WM8985_NFU_WIDTH 1 /* NFU */
  525. #define WM8985_NFA1_6_0_MASK 0x007F /* NFA1(6:0) - [6:0] */
  526. #define WM8985_NFA1_6_0_SHIFT 0 /* NFA1(6:0) - [6:0] */
  527. #define WM8985_NFA1_6_0_WIDTH 7 /* NFA1(6:0) - [6:0] */
  528. /*
  529. * R32 (0x20) - ALC control 1
  530. */
  531. #define WM8985_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */
  532. #define WM8985_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */
  533. #define WM8985_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */
  534. #define WM8985_ALCMAX_MASK 0x0038 /* ALCMAX - [5:3] */
  535. #define WM8985_ALCMAX_SHIFT 3 /* ALCMAX - [5:3] */
  536. #define WM8985_ALCMAX_WIDTH 3 /* ALCMAX - [5:3] */
  537. #define WM8985_ALCMIN_MASK 0x0007 /* ALCMIN - [2:0] */
  538. #define WM8985_ALCMIN_SHIFT 0 /* ALCMIN - [2:0] */
  539. #define WM8985_ALCMIN_WIDTH 3 /* ALCMIN - [2:0] */
  540. /*
  541. * R33 (0x21) - ALC control 2
  542. */
  543. #define WM8985_ALCHLD_MASK 0x00F0 /* ALCHLD - [7:4] */
  544. #define WM8985_ALCHLD_SHIFT 4 /* ALCHLD - [7:4] */
  545. #define WM8985_ALCHLD_WIDTH 4 /* ALCHLD - [7:4] */
  546. #define WM8985_ALCLVL_MASK 0x000F /* ALCLVL - [3:0] */
  547. #define WM8985_ALCLVL_SHIFT 0 /* ALCLVL - [3:0] */
  548. #define WM8985_ALCLVL_WIDTH 4 /* ALCLVL - [3:0] */
  549. /*
  550. * R34 (0x22) - ALC control 3
  551. */
  552. #define WM8985_ALCMODE 0x0100 /* ALCMODE */
  553. #define WM8985_ALCMODE_MASK 0x0100 /* ALCMODE */
  554. #define WM8985_ALCMODE_SHIFT 8 /* ALCMODE */
  555. #define WM8985_ALCMODE_WIDTH 1 /* ALCMODE */
  556. #define WM8985_ALCDCY_MASK 0x00F0 /* ALCDCY - [7:4] */
  557. #define WM8985_ALCDCY_SHIFT 4 /* ALCDCY - [7:4] */
  558. #define WM8985_ALCDCY_WIDTH 4 /* ALCDCY - [7:4] */
  559. #define WM8985_ALCATK_MASK 0x000F /* ALCATK - [3:0] */
  560. #define WM8985_ALCATK_SHIFT 0 /* ALCATK - [3:0] */
  561. #define WM8985_ALCATK_WIDTH 4 /* ALCATK - [3:0] */
  562. /*
  563. * R35 (0x23) - Noise Gate
  564. */
  565. #define WM8985_NGEN 0x0008 /* NGEN */
  566. #define WM8985_NGEN_MASK 0x0008 /* NGEN */
  567. #define WM8985_NGEN_SHIFT 3 /* NGEN */
  568. #define WM8985_NGEN_WIDTH 1 /* NGEN */
  569. #define WM8985_NGTH_MASK 0x0007 /* NGTH - [2:0] */
  570. #define WM8985_NGTH_SHIFT 0 /* NGTH - [2:0] */
  571. #define WM8985_NGTH_WIDTH 3 /* NGTH - [2:0] */
  572. /*
  573. * R36 (0x24) - PLL N
  574. */
  575. #define WM8985_PLL_PRESCALE 0x0010 /* PLL_PRESCALE */
  576. #define WM8985_PLL_PRESCALE_MASK 0x0010 /* PLL_PRESCALE */
  577. #define WM8985_PLL_PRESCALE_SHIFT 4 /* PLL_PRESCALE */
  578. #define WM8985_PLL_PRESCALE_WIDTH 1 /* PLL_PRESCALE */
  579. #define WM8985_PLLN_MASK 0x000F /* PLLN - [3:0] */
  580. #define WM8985_PLLN_SHIFT 0 /* PLLN - [3:0] */
  581. #define WM8985_PLLN_WIDTH 4 /* PLLN - [3:0] */
  582. /*
  583. * R37 (0x25) - PLL K 1
  584. */
  585. #define WM8985_PLLK_23_18_MASK 0x003F /* PLLK(23:18) - [5:0] */
  586. #define WM8985_PLLK_23_18_SHIFT 0 /* PLLK(23:18) - [5:0] */
  587. #define WM8985_PLLK_23_18_WIDTH 6 /* PLLK(23:18) - [5:0] */
  588. /*
  589. * R38 (0x26) - PLL K 2
  590. */
  591. #define WM8985_PLLK_17_9_MASK 0x01FF /* PLLK(17:9) - [8:0] */
  592. #define WM8985_PLLK_17_9_SHIFT 0 /* PLLK(17:9) - [8:0] */
  593. #define WM8985_PLLK_17_9_WIDTH 9 /* PLLK(17:9) - [8:0] */
  594. /*
  595. * R39 (0x27) - PLL K 3
  596. */
  597. #define WM8985_PLLK_8_0_MASK 0x01FF /* PLLK(8:0) - [8:0] */
  598. #define WM8985_PLLK_8_0_SHIFT 0 /* PLLK(8:0) - [8:0] */
  599. #define WM8985_PLLK_8_0_WIDTH 9 /* PLLK(8:0) - [8:0] */
  600. /*
  601. * R41 (0x29) - 3D control
  602. */
  603. #define WM8985_DEPTH3D_MASK 0x000F /* DEPTH3D - [3:0] */
  604. #define WM8985_DEPTH3D_SHIFT 0 /* DEPTH3D - [3:0] */
  605. #define WM8985_DEPTH3D_WIDTH 4 /* DEPTH3D - [3:0] */
  606. /*
  607. * R42 (0x2A) - OUT4 to ADC
  608. */
  609. #define WM8985_OUT4_2ADCVOL_MASK 0x01C0 /* OUT4_2ADCVOL - [8:6] */
  610. #define WM8985_OUT4_2ADCVOL_SHIFT 6 /* OUT4_2ADCVOL - [8:6] */
  611. #define WM8985_OUT4_2ADCVOL_WIDTH 3 /* OUT4_2ADCVOL - [8:6] */
  612. #define WM8985_OUT4_2LNR 0x0020 /* OUT4_2LNR */
  613. #define WM8985_OUT4_2LNR_MASK 0x0020 /* OUT4_2LNR */
  614. #define WM8985_OUT4_2LNR_SHIFT 5 /* OUT4_2LNR */
  615. #define WM8985_OUT4_2LNR_WIDTH 1 /* OUT4_2LNR */
  616. #define WM8758_VMIDTOG_MASK 0x0010 /* VMIDTOG */
  617. #define WM8758_VMIDTOG_SHIFT 4 /* VMIDTOG */
  618. #define WM8758_VMIDTOG_WIDTH 1 /* VMIDTOG */
  619. #define WM8758_OUT2DEL_MASK 0x0008 /* OUT2DEL */
  620. #define WM8758_OUT2DEL_SHIFT 3 /* OUT2DEL */
  621. #define WM8758_OUT2DEL_WIDTH 1 /* OUT2DEL */
  622. #define WM8985_POBCTRL 0x0004 /* POBCTRL */
  623. #define WM8985_POBCTRL_MASK 0x0004 /* POBCTRL */
  624. #define WM8985_POBCTRL_SHIFT 2 /* POBCTRL */
  625. #define WM8985_POBCTRL_WIDTH 1 /* POBCTRL */
  626. #define WM8985_DELEN 0x0002 /* DELEN */
  627. #define WM8985_DELEN_MASK 0x0002 /* DELEN */
  628. #define WM8985_DELEN_SHIFT 1 /* DELEN */
  629. #define WM8985_DELEN_WIDTH 1 /* DELEN */
  630. #define WM8985_OUT1DEL 0x0001 /* OUT1DEL */
  631. #define WM8985_OUT1DEL_MASK 0x0001 /* OUT1DEL */
  632. #define WM8985_OUT1DEL_SHIFT 0 /* OUT1DEL */
  633. #define WM8985_OUT1DEL_WIDTH 1 /* OUT1DEL */
  634. /*
  635. * R43 (0x2B) - Beep control
  636. */
  637. #define WM8985_BYPL2RMIX 0x0100 /* BYPL2RMIX */
  638. #define WM8985_BYPL2RMIX_MASK 0x0100 /* BYPL2RMIX */
  639. #define WM8985_BYPL2RMIX_SHIFT 8 /* BYPL2RMIX */
  640. #define WM8985_BYPL2RMIX_WIDTH 1 /* BYPL2RMIX */
  641. #define WM8985_BYPR2LMIX 0x0080 /* BYPR2LMIX */
  642. #define WM8985_BYPR2LMIX_MASK 0x0080 /* BYPR2LMIX */
  643. #define WM8985_BYPR2LMIX_SHIFT 7 /* BYPR2LMIX */
  644. #define WM8985_BYPR2LMIX_WIDTH 1 /* BYPR2LMIX */
  645. #define WM8985_MUTERPGA2INV 0x0020 /* MUTERPGA2INV */
  646. #define WM8985_MUTERPGA2INV_MASK 0x0020 /* MUTERPGA2INV */
  647. #define WM8985_MUTERPGA2INV_SHIFT 5 /* MUTERPGA2INV */
  648. #define WM8985_MUTERPGA2INV_WIDTH 1 /* MUTERPGA2INV */
  649. #define WM8985_INVROUT2 0x0010 /* INVROUT2 */
  650. #define WM8985_INVROUT2_MASK 0x0010 /* INVROUT2 */
  651. #define WM8985_INVROUT2_SHIFT 4 /* INVROUT2 */
  652. #define WM8985_INVROUT2_WIDTH 1 /* INVROUT2 */
  653. #define WM8985_BEEPVOL_MASK 0x000E /* BEEPVOL - [3:1] */
  654. #define WM8985_BEEPVOL_SHIFT 1 /* BEEPVOL - [3:1] */
  655. #define WM8985_BEEPVOL_WIDTH 3 /* BEEPVOL - [3:1] */
  656. #define WM8758_DELEN2_MASK 0x0004 /* DELEN2 */
  657. #define WM8758_DELEN2_SHIFT 2 /* DELEN2 */
  658. #define WM8758_DELEN2_WIDTH 1 /* DELEN2 */
  659. #define WM8985_BEEPEN 0x0001 /* BEEPEN */
  660. #define WM8985_BEEPEN_MASK 0x0001 /* BEEPEN */
  661. #define WM8985_BEEPEN_SHIFT 0 /* BEEPEN */
  662. #define WM8985_BEEPEN_WIDTH 1 /* BEEPEN */
  663. /*
  664. * R44 (0x2C) - Input ctrl
  665. */
  666. #define WM8985_MBVSEL 0x0100 /* MBVSEL */
  667. #define WM8985_MBVSEL_MASK 0x0100 /* MBVSEL */
  668. #define WM8985_MBVSEL_SHIFT 8 /* MBVSEL */
  669. #define WM8985_MBVSEL_WIDTH 1 /* MBVSEL */
  670. #define WM8985_R2_2INPPGA 0x0040 /* R2_2INPPGA */
  671. #define WM8985_R2_2INPPGA_MASK 0x0040 /* R2_2INPPGA */
  672. #define WM8985_R2_2INPPGA_SHIFT 6 /* R2_2INPPGA */
  673. #define WM8985_R2_2INPPGA_WIDTH 1 /* R2_2INPPGA */
  674. #define WM8985_RIN2INPPGA 0x0020 /* RIN2INPPGA */
  675. #define WM8985_RIN2INPPGA_MASK 0x0020 /* RIN2INPPGA */
  676. #define WM8985_RIN2INPPGA_SHIFT 5 /* RIN2INPPGA */
  677. #define WM8985_RIN2INPPGA_WIDTH 1 /* RIN2INPPGA */
  678. #define WM8985_RIP2INPPGA 0x0010 /* RIP2INPPGA */
  679. #define WM8985_RIP2INPPGA_MASK 0x0010 /* RIP2INPPGA */
  680. #define WM8985_RIP2INPPGA_SHIFT 4 /* RIP2INPPGA */
  681. #define WM8985_RIP2INPPGA_WIDTH 1 /* RIP2INPPGA */
  682. #define WM8985_L2_2INPPGA 0x0004 /* L2_2INPPGA */
  683. #define WM8985_L2_2INPPGA_MASK 0x0004 /* L2_2INPPGA */
  684. #define WM8985_L2_2INPPGA_SHIFT 2 /* L2_2INPPGA */
  685. #define WM8985_L2_2INPPGA_WIDTH 1 /* L2_2INPPGA */
  686. #define WM8985_LIN2INPPGA 0x0002 /* LIN2INPPGA */
  687. #define WM8985_LIN2INPPGA_MASK 0x0002 /* LIN2INPPGA */
  688. #define WM8985_LIN2INPPGA_SHIFT 1 /* LIN2INPPGA */
  689. #define WM8985_LIN2INPPGA_WIDTH 1 /* LIN2INPPGA */
  690. #define WM8985_LIP2INPPGA 0x0001 /* LIP2INPPGA */
  691. #define WM8985_LIP2INPPGA_MASK 0x0001 /* LIP2INPPGA */
  692. #define WM8985_LIP2INPPGA_SHIFT 0 /* LIP2INPPGA */
  693. #define WM8985_LIP2INPPGA_WIDTH 1 /* LIP2INPPGA */
  694. /*
  695. * R45 (0x2D) - Left INP PGA gain ctrl
  696. */
  697. #define WM8985_INPGAVU 0x0100 /* INPGAVU */
  698. #define WM8985_INPGAVU_MASK 0x0100 /* INPGAVU */
  699. #define WM8985_INPGAVU_SHIFT 8 /* INPGAVU */
  700. #define WM8985_INPGAVU_WIDTH 1 /* INPGAVU */
  701. #define WM8985_INPPGAZCL 0x0080 /* INPPGAZCL */
  702. #define WM8985_INPPGAZCL_MASK 0x0080 /* INPPGAZCL */
  703. #define WM8985_INPPGAZCL_SHIFT 7 /* INPPGAZCL */
  704. #define WM8985_INPPGAZCL_WIDTH 1 /* INPPGAZCL */
  705. #define WM8985_INPPGAMUTEL 0x0040 /* INPPGAMUTEL */
  706. #define WM8985_INPPGAMUTEL_MASK 0x0040 /* INPPGAMUTEL */
  707. #define WM8985_INPPGAMUTEL_SHIFT 6 /* INPPGAMUTEL */
  708. #define WM8985_INPPGAMUTEL_WIDTH 1 /* INPPGAMUTEL */
  709. #define WM8985_INPPGAVOLL_MASK 0x003F /* INPPGAVOLL - [5:0] */
  710. #define WM8985_INPPGAVOLL_SHIFT 0 /* INPPGAVOLL - [5:0] */
  711. #define WM8985_INPPGAVOLL_WIDTH 6 /* INPPGAVOLL - [5:0] */
  712. /*
  713. * R46 (0x2E) - Right INP PGA gain ctrl
  714. */
  715. #define WM8985_INPGAVU 0x0100 /* INPGAVU */
  716. #define WM8985_INPGAVU_MASK 0x0100 /* INPGAVU */
  717. #define WM8985_INPGAVU_SHIFT 8 /* INPGAVU */
  718. #define WM8985_INPGAVU_WIDTH 1 /* INPGAVU */
  719. #define WM8985_INPPGAZCR 0x0080 /* INPPGAZCR */
  720. #define WM8985_INPPGAZCR_MASK 0x0080 /* INPPGAZCR */
  721. #define WM8985_INPPGAZCR_SHIFT 7 /* INPPGAZCR */
  722. #define WM8985_INPPGAZCR_WIDTH 1 /* INPPGAZCR */
  723. #define WM8985_INPPGAMUTER 0x0040 /* INPPGAMUTER */
  724. #define WM8985_INPPGAMUTER_MASK 0x0040 /* INPPGAMUTER */
  725. #define WM8985_INPPGAMUTER_SHIFT 6 /* INPPGAMUTER */
  726. #define WM8985_INPPGAMUTER_WIDTH 1 /* INPPGAMUTER */
  727. #define WM8985_INPPGAVOLR_MASK 0x003F /* INPPGAVOLR - [5:0] */
  728. #define WM8985_INPPGAVOLR_SHIFT 0 /* INPPGAVOLR - [5:0] */
  729. #define WM8985_INPPGAVOLR_WIDTH 6 /* INPPGAVOLR - [5:0] */
  730. /*
  731. * R47 (0x2F) - Left ADC BOOST ctrl
  732. */
  733. #define WM8985_PGABOOSTL 0x0100 /* PGABOOSTL */
  734. #define WM8985_PGABOOSTL_MASK 0x0100 /* PGABOOSTL */
  735. #define WM8985_PGABOOSTL_SHIFT 8 /* PGABOOSTL */
  736. #define WM8985_PGABOOSTL_WIDTH 1 /* PGABOOSTL */
  737. #define WM8985_L2_2BOOSTVOL_MASK 0x0070 /* L2_2BOOSTVOL - [6:4] */
  738. #define WM8985_L2_2BOOSTVOL_SHIFT 4 /* L2_2BOOSTVOL - [6:4] */
  739. #define WM8985_L2_2BOOSTVOL_WIDTH 3 /* L2_2BOOSTVOL - [6:4] */
  740. #define WM8985_AUXL2BOOSTVOL_MASK 0x0007 /* AUXL2BOOSTVOL - [2:0] */
  741. #define WM8985_AUXL2BOOSTVOL_SHIFT 0 /* AUXL2BOOSTVOL - [2:0] */
  742. #define WM8985_AUXL2BOOSTVOL_WIDTH 3 /* AUXL2BOOSTVOL - [2:0] */
  743. /*
  744. * R48 (0x30) - Right ADC BOOST ctrl
  745. */
  746. #define WM8985_PGABOOSTR 0x0100 /* PGABOOSTR */
  747. #define WM8985_PGABOOSTR_MASK 0x0100 /* PGABOOSTR */
  748. #define WM8985_PGABOOSTR_SHIFT 8 /* PGABOOSTR */
  749. #define WM8985_PGABOOSTR_WIDTH 1 /* PGABOOSTR */
  750. #define WM8985_R2_2BOOSTVOL_MASK 0x0070 /* R2_2BOOSTVOL - [6:4] */
  751. #define WM8985_R2_2BOOSTVOL_SHIFT 4 /* R2_2BOOSTVOL - [6:4] */
  752. #define WM8985_R2_2BOOSTVOL_WIDTH 3 /* R2_2BOOSTVOL - [6:4] */
  753. #define WM8985_AUXR2BOOSTVOL_MASK 0x0007 /* AUXR2BOOSTVOL - [2:0] */
  754. #define WM8985_AUXR2BOOSTVOL_SHIFT 0 /* AUXR2BOOSTVOL - [2:0] */
  755. #define WM8985_AUXR2BOOSTVOL_WIDTH 3 /* AUXR2BOOSTVOL - [2:0] */
  756. /*
  757. * R49 (0x31) - Output ctrl
  758. */
  759. #define WM8758_HP_COM 0x0100 /* HP_COM */
  760. #define WM8758_HP_COM_MASK 0x0100 /* HP_COM */
  761. #define WM8758_HP_COM_SHIFT 8 /* HP_COM */
  762. #define WM8758_HP_COM_WIDTH 1 /* HP_COM */
  763. #define WM8758_LINE_COM 0x0080 /* LINE_COM */
  764. #define WM8758_LINE_COM_MASK 0x0080 /* LINE_COM */
  765. #define WM8758_LINE_COM_SHIFT 7 /* LINE_COM */
  766. #define WM8758_LINE_COM_WIDTH 1 /* LINE_COM */
  767. #define WM8985_DACL2RMIX 0x0040 /* DACL2RMIX */
  768. #define WM8985_DACL2RMIX_MASK 0x0040 /* DACL2RMIX */
  769. #define WM8985_DACL2RMIX_SHIFT 6 /* DACL2RMIX */
  770. #define WM8985_DACL2RMIX_WIDTH 1 /* DACL2RMIX */
  771. #define WM8985_DACR2LMIX 0x0020 /* DACR2LMIX */
  772. #define WM8985_DACR2LMIX_MASK 0x0020 /* DACR2LMIX */
  773. #define WM8985_DACR2LMIX_SHIFT 5 /* DACR2LMIX */
  774. #define WM8985_DACR2LMIX_WIDTH 1 /* DACR2LMIX */
  775. #define WM8985_OUT4BOOST 0x0010 /* OUT4BOOST */
  776. #define WM8985_OUT4BOOST_MASK 0x0010 /* OUT4BOOST */
  777. #define WM8985_OUT4BOOST_SHIFT 4 /* OUT4BOOST */
  778. #define WM8985_OUT4BOOST_WIDTH 1 /* OUT4BOOST */
  779. #define WM8985_OUT3BOOST 0x0008 /* OUT3BOOST */
  780. #define WM8985_OUT3BOOST_MASK 0x0008 /* OUT3BOOST */
  781. #define WM8985_OUT3BOOST_SHIFT 3 /* OUT3BOOST */
  782. #define WM8985_OUT3BOOST_WIDTH 1 /* OUT3BOOST */
  783. #define WM8758_OUT4ENDEL 0x0010 /* OUT4ENDEL */
  784. #define WM8758_OUT4ENDEL_MASK 0x0010 /* OUT4ENDEL */
  785. #define WM8758_OUT4ENDEL_SHIFT 4 /* OUT4ENDEL */
  786. #define WM8758_OUT4ENDEL_WIDTH 1 /* OUT4ENDEL */
  787. #define WM8758_OUT3ENDEL 0x0008 /* OUT3ENDEL */
  788. #define WM8758_OUT3ENDEL_MASK 0x0008 /* OUT3ENDEL */
  789. #define WM8758_OUT3ENDEL_SHIFT 3 /* OUT3ENDEL */
  790. #define WM8758_OUT3ENDEL_WIDTH 1 /* OUT3ENDEL */
  791. #define WM8985_TSOPCTRL 0x0004 /* TSOPCTRL */
  792. #define WM8985_TSOPCTRL_MASK 0x0004 /* TSOPCTRL */
  793. #define WM8985_TSOPCTRL_SHIFT 2 /* TSOPCTRL */
  794. #define WM8985_TSOPCTRL_WIDTH 1 /* TSOPCTRL */
  795. #define WM8985_TSDEN 0x0002 /* TSDEN */
  796. #define WM8985_TSDEN_MASK 0x0002 /* TSDEN */
  797. #define WM8985_TSDEN_SHIFT 1 /* TSDEN */
  798. #define WM8985_TSDEN_WIDTH 1 /* TSDEN */
  799. #define WM8985_VROI 0x0001 /* VROI */
  800. #define WM8985_VROI_MASK 0x0001 /* VROI */
  801. #define WM8985_VROI_SHIFT 0 /* VROI */
  802. #define WM8985_VROI_WIDTH 1 /* VROI */
  803. /*
  804. * R50 (0x32) - Left mixer ctrl
  805. */
  806. #define WM8985_AUXLMIXVOL_MASK 0x01C0 /* AUXLMIXVOL - [8:6] */
  807. #define WM8985_AUXLMIXVOL_SHIFT 6 /* AUXLMIXVOL - [8:6] */
  808. #define WM8985_AUXLMIXVOL_WIDTH 3 /* AUXLMIXVOL - [8:6] */
  809. #define WM8985_AUXL2LMIX 0x0020 /* AUXL2LMIX */
  810. #define WM8985_AUXL2LMIX_MASK 0x0020 /* AUXL2LMIX */
  811. #define WM8985_AUXL2LMIX_SHIFT 5 /* AUXL2LMIX */
  812. #define WM8985_AUXL2LMIX_WIDTH 1 /* AUXL2LMIX */
  813. #define WM8985_BYPLMIXVOL_MASK 0x001C /* BYPLMIXVOL - [4:2] */
  814. #define WM8985_BYPLMIXVOL_SHIFT 2 /* BYPLMIXVOL - [4:2] */
  815. #define WM8985_BYPLMIXVOL_WIDTH 3 /* BYPLMIXVOL - [4:2] */
  816. #define WM8985_BYPL2LMIX 0x0002 /* BYPL2LMIX */
  817. #define WM8985_BYPL2LMIX_MASK 0x0002 /* BYPL2LMIX */
  818. #define WM8985_BYPL2LMIX_SHIFT 1 /* BYPL2LMIX */
  819. #define WM8985_BYPL2LMIX_WIDTH 1 /* BYPL2LMIX */
  820. #define WM8985_DACL2LMIX 0x0001 /* DACL2LMIX */
  821. #define WM8985_DACL2LMIX_MASK 0x0001 /* DACL2LMIX */
  822. #define WM8985_DACL2LMIX_SHIFT 0 /* DACL2LMIX */
  823. #define WM8985_DACL2LMIX_WIDTH 1 /* DACL2LMIX */
  824. /*
  825. * R51 (0x33) - Right mixer ctrl
  826. */
  827. #define WM8985_AUXRMIXVOL_MASK 0x01C0 /* AUXRMIXVOL - [8:6] */
  828. #define WM8985_AUXRMIXVOL_SHIFT 6 /* AUXRMIXVOL - [8:6] */
  829. #define WM8985_AUXRMIXVOL_WIDTH 3 /* AUXRMIXVOL - [8:6] */
  830. #define WM8985_AUXR2RMIX 0x0020 /* AUXR2RMIX */
  831. #define WM8985_AUXR2RMIX_MASK 0x0020 /* AUXR2RMIX */
  832. #define WM8985_AUXR2RMIX_SHIFT 5 /* AUXR2RMIX */
  833. #define WM8985_AUXR2RMIX_WIDTH 1 /* AUXR2RMIX */
  834. #define WM8985_BYPRMIXVOL_MASK 0x001C /* BYPRMIXVOL - [4:2] */
  835. #define WM8985_BYPRMIXVOL_SHIFT 2 /* BYPRMIXVOL - [4:2] */
  836. #define WM8985_BYPRMIXVOL_WIDTH 3 /* BYPRMIXVOL - [4:2] */
  837. #define WM8985_BYPR2RMIX 0x0002 /* BYPR2RMIX */
  838. #define WM8985_BYPR2RMIX_MASK 0x0002 /* BYPR2RMIX */
  839. #define WM8985_BYPR2RMIX_SHIFT 1 /* BYPR2RMIX */
  840. #define WM8985_BYPR2RMIX_WIDTH 1 /* BYPR2RMIX */
  841. #define WM8985_DACR2RMIX 0x0001 /* DACR2RMIX */
  842. #define WM8985_DACR2RMIX_MASK 0x0001 /* DACR2RMIX */
  843. #define WM8985_DACR2RMIX_SHIFT 0 /* DACR2RMIX */
  844. #define WM8985_DACR2RMIX_WIDTH 1 /* DACR2RMIX */
  845. /*
  846. * R52 (0x34) - LOUT1 (HP) volume ctrl
  847. */
  848. #define WM8985_OUT1VU 0x0100 /* OUT1VU */
  849. #define WM8985_OUT1VU_MASK 0x0100 /* OUT1VU */
  850. #define WM8985_OUT1VU_SHIFT 8 /* OUT1VU */
  851. #define WM8985_OUT1VU_WIDTH 1 /* OUT1VU */
  852. #define WM8985_LOUT1ZC 0x0080 /* LOUT1ZC */
  853. #define WM8985_LOUT1ZC_MASK 0x0080 /* LOUT1ZC */
  854. #define WM8985_LOUT1ZC_SHIFT 7 /* LOUT1ZC */
  855. #define WM8985_LOUT1ZC_WIDTH 1 /* LOUT1ZC */
  856. #define WM8985_LOUT1MUTE 0x0040 /* LOUT1MUTE */
  857. #define WM8985_LOUT1MUTE_MASK 0x0040 /* LOUT1MUTE */
  858. #define WM8985_LOUT1MUTE_SHIFT 6 /* LOUT1MUTE */
  859. #define WM8985_LOUT1MUTE_WIDTH 1 /* LOUT1MUTE */
  860. #define WM8985_LOUT1VOL_MASK 0x003F /* LOUT1VOL - [5:0] */
  861. #define WM8985_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [5:0] */
  862. #define WM8985_LOUT1VOL_WIDTH 6 /* LOUT1VOL - [5:0] */
  863. /*
  864. * R53 (0x35) - ROUT1 (HP) volume ctrl
  865. */
  866. #define WM8985_OUT1VU 0x0100 /* OUT1VU */
  867. #define WM8985_OUT1VU_MASK 0x0100 /* OUT1VU */
  868. #define WM8985_OUT1VU_SHIFT 8 /* OUT1VU */
  869. #define WM8985_OUT1VU_WIDTH 1 /* OUT1VU */
  870. #define WM8985_ROUT1ZC 0x0080 /* ROUT1ZC */
  871. #define WM8985_ROUT1ZC_MASK 0x0080 /* ROUT1ZC */
  872. #define WM8985_ROUT1ZC_SHIFT 7 /* ROUT1ZC */
  873. #define WM8985_ROUT1ZC_WIDTH 1 /* ROUT1ZC */
  874. #define WM8985_ROUT1MUTE 0x0040 /* ROUT1MUTE */
  875. #define WM8985_ROUT1MUTE_MASK 0x0040 /* ROUT1MUTE */
  876. #define WM8985_ROUT1MUTE_SHIFT 6 /* ROUT1MUTE */
  877. #define WM8985_ROUT1MUTE_WIDTH 1 /* ROUT1MUTE */
  878. #define WM8985_ROUT1VOL_MASK 0x003F /* ROUT1VOL - [5:0] */
  879. #define WM8985_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [5:0] */
  880. #define WM8985_ROUT1VOL_WIDTH 6 /* ROUT1VOL - [5:0] */
  881. /*
  882. * R54 (0x36) - LOUT2 (SPK) volume ctrl
  883. */
  884. #define WM8985_OUT2VU 0x0100 /* OUT2VU */
  885. #define WM8985_OUT2VU_MASK 0x0100 /* OUT2VU */
  886. #define WM8985_OUT2VU_SHIFT 8 /* OUT2VU */
  887. #define WM8985_OUT2VU_WIDTH 1 /* OUT2VU */
  888. #define WM8985_LOUT2ZC 0x0080 /* LOUT2ZC */
  889. #define WM8985_LOUT2ZC_MASK 0x0080 /* LOUT2ZC */
  890. #define WM8985_LOUT2ZC_SHIFT 7 /* LOUT2ZC */
  891. #define WM8985_LOUT2ZC_WIDTH 1 /* LOUT2ZC */
  892. #define WM8985_LOUT2MUTE 0x0040 /* LOUT2MUTE */
  893. #define WM8985_LOUT2MUTE_MASK 0x0040 /* LOUT2MUTE */
  894. #define WM8985_LOUT2MUTE_SHIFT 6 /* LOUT2MUTE */
  895. #define WM8985_LOUT2MUTE_WIDTH 1 /* LOUT2MUTE */
  896. #define WM8985_LOUT2VOL_MASK 0x003F /* LOUT2VOL - [5:0] */
  897. #define WM8985_LOUT2VOL_SHIFT 0 /* LOUT2VOL - [5:0] */
  898. #define WM8985_LOUT2VOL_WIDTH 6 /* LOUT2VOL - [5:0] */
  899. /*
  900. * R55 (0x37) - ROUT2 (SPK) volume ctrl
  901. */
  902. #define WM8985_OUT2VU 0x0100 /* OUT2VU */
  903. #define WM8985_OUT2VU_MASK 0x0100 /* OUT2VU */
  904. #define WM8985_OUT2VU_SHIFT 8 /* OUT2VU */
  905. #define WM8985_OUT2VU_WIDTH 1 /* OUT2VU */
  906. #define WM8985_ROUT2ZC 0x0080 /* ROUT2ZC */
  907. #define WM8985_ROUT2ZC_MASK 0x0080 /* ROUT2ZC */
  908. #define WM8985_ROUT2ZC_SHIFT 7 /* ROUT2ZC */
  909. #define WM8985_ROUT2ZC_WIDTH 1 /* ROUT2ZC */
  910. #define WM8985_ROUT2MUTE 0x0040 /* ROUT2MUTE */
  911. #define WM8985_ROUT2MUTE_MASK 0x0040 /* ROUT2MUTE */
  912. #define WM8985_ROUT2MUTE_SHIFT 6 /* ROUT2MUTE */
  913. #define WM8985_ROUT2MUTE_WIDTH 1 /* ROUT2MUTE */
  914. #define WM8985_ROUT2VOL_MASK 0x003F /* ROUT2VOL - [5:0] */
  915. #define WM8985_ROUT2VOL_SHIFT 0 /* ROUT2VOL - [5:0] */
  916. #define WM8985_ROUT2VOL_WIDTH 6 /* ROUT2VOL - [5:0] */
  917. /*
  918. * R56 (0x38) - OUT3 mixer ctrl
  919. */
  920. #define WM8985_OUT3MUTE 0x0040 /* OUT3MUTE */
  921. #define WM8985_OUT3MUTE_MASK 0x0040 /* OUT3MUTE */
  922. #define WM8985_OUT3MUTE_SHIFT 6 /* OUT3MUTE */
  923. #define WM8985_OUT3MUTE_WIDTH 1 /* OUT3MUTE */
  924. #define WM8985_OUT4_2OUT3 0x0008 /* OUT4_2OUT3 */
  925. #define WM8985_OUT4_2OUT3_MASK 0x0008 /* OUT4_2OUT3 */
  926. #define WM8985_OUT4_2OUT3_SHIFT 3 /* OUT4_2OUT3 */
  927. #define WM8985_OUT4_2OUT3_WIDTH 1 /* OUT4_2OUT3 */
  928. #define WM8985_BYPL2OUT3 0x0004 /* BYPL2OUT3 */
  929. #define WM8985_BYPL2OUT3_MASK 0x0004 /* BYPL2OUT3 */
  930. #define WM8985_BYPL2OUT3_SHIFT 2 /* BYPL2OUT3 */
  931. #define WM8985_BYPL2OUT3_WIDTH 1 /* BYPL2OUT3 */
  932. #define WM8985_LMIX2OUT3 0x0002 /* LMIX2OUT3 */
  933. #define WM8985_LMIX2OUT3_MASK 0x0002 /* LMIX2OUT3 */
  934. #define WM8985_LMIX2OUT3_SHIFT 1 /* LMIX2OUT3 */
  935. #define WM8985_LMIX2OUT3_WIDTH 1 /* LMIX2OUT3 */
  936. #define WM8985_LDAC2OUT3 0x0001 /* LDAC2OUT3 */
  937. #define WM8985_LDAC2OUT3_MASK 0x0001 /* LDAC2OUT3 */
  938. #define WM8985_LDAC2OUT3_SHIFT 0 /* LDAC2OUT3 */
  939. #define WM8985_LDAC2OUT3_WIDTH 1 /* LDAC2OUT3 */
  940. /*
  941. * R57 (0x39) - OUT4 (MONO) mix ctrl
  942. */
  943. #define WM8985_OUT3_2OUT4 0x0080 /* OUT3_2OUT4 */
  944. #define WM8985_OUT3_2OUT4_MASK 0x0080 /* OUT3_2OUT4 */
  945. #define WM8985_OUT3_2OUT4_SHIFT 7 /* OUT3_2OUT4 */
  946. #define WM8985_OUT3_2OUT4_WIDTH 1 /* OUT3_2OUT4 */
  947. #define WM8985_OUT4MUTE 0x0040 /* OUT4MUTE */
  948. #define WM8985_OUT4MUTE_MASK 0x0040 /* OUT4MUTE */
  949. #define WM8985_OUT4MUTE_SHIFT 6 /* OUT4MUTE */
  950. #define WM8985_OUT4MUTE_WIDTH 1 /* OUT4MUTE */
  951. #define WM8985_OUT4ATTN 0x0020 /* OUT4ATTN */
  952. #define WM8985_OUT4ATTN_MASK 0x0020 /* OUT4ATTN */
  953. #define WM8985_OUT4ATTN_SHIFT 5 /* OUT4ATTN */
  954. #define WM8985_OUT4ATTN_WIDTH 1 /* OUT4ATTN */
  955. #define WM8985_LMIX2OUT4 0x0010 /* LMIX2OUT4 */
  956. #define WM8985_LMIX2OUT4_MASK 0x0010 /* LMIX2OUT4 */
  957. #define WM8985_LMIX2OUT4_SHIFT 4 /* LMIX2OUT4 */
  958. #define WM8985_LMIX2OUT4_WIDTH 1 /* LMIX2OUT4 */
  959. #define WM8985_LDAC2OUT4 0x0008 /* LDAC2OUT4 */
  960. #define WM8985_LDAC2OUT4_MASK 0x0008 /* LDAC2OUT4 */
  961. #define WM8985_LDAC2OUT4_SHIFT 3 /* LDAC2OUT4 */
  962. #define WM8985_LDAC2OUT4_WIDTH 1 /* LDAC2OUT4 */
  963. #define WM8985_BYPR2OUT4 0x0004 /* BYPR2OUT4 */
  964. #define WM8985_BYPR2OUT4_MASK 0x0004 /* BYPR2OUT4 */
  965. #define WM8985_BYPR2OUT4_SHIFT 2 /* BYPR2OUT4 */
  966. #define WM8985_BYPR2OUT4_WIDTH 1 /* BYPR2OUT4 */
  967. #define WM8985_RMIX2OUT4 0x0002 /* RMIX2OUT4 */
  968. #define WM8985_RMIX2OUT4_MASK 0x0002 /* RMIX2OUT4 */
  969. #define WM8985_RMIX2OUT4_SHIFT 1 /* RMIX2OUT4 */
  970. #define WM8985_RMIX2OUT4_WIDTH 1 /* RMIX2OUT4 */
  971. #define WM8985_RDAC2OUT4 0x0001 /* RDAC2OUT4 */
  972. #define WM8985_RDAC2OUT4_MASK 0x0001 /* RDAC2OUT4 */
  973. #define WM8985_RDAC2OUT4_SHIFT 0 /* RDAC2OUT4 */
  974. #define WM8985_RDAC2OUT4_WIDTH 1 /* RDAC2OUT4 */
  975. /*
  976. * R60 (0x3C) - OUTPUT ctrl
  977. */
  978. #define WM8985_VIDBUFFTST_MASK 0x01E0 /* VIDBUFFTST - [8:5] */
  979. #define WM8985_VIDBUFFTST_SHIFT 5 /* VIDBUFFTST - [8:5] */
  980. #define WM8985_VIDBUFFTST_WIDTH 4 /* VIDBUFFTST - [8:5] */
  981. #define WM8985_HPTOG 0x0008 /* HPTOG */
  982. #define WM8985_HPTOG_MASK 0x0008 /* HPTOG */
  983. #define WM8985_HPTOG_SHIFT 3 /* HPTOG */
  984. #define WM8985_HPTOG_WIDTH 1 /* HPTOG */
  985. /*
  986. * R61 (0x3D) - BIAS CTRL
  987. */
  988. #define WM8985_BIASCUT 0x0100 /* BIASCUT */
  989. #define WM8985_BIASCUT_MASK 0x0100 /* BIASCUT */
  990. #define WM8985_BIASCUT_SHIFT 8 /* BIASCUT */
  991. #define WM8985_BIASCUT_WIDTH 1 /* BIASCUT */
  992. #define WM8985_HALFIPBIAS 0x0080 /* HALFIPBIAS */
  993. #define WM8985_HALFIPBIAS_MASK 0x0080 /* HALFIPBIAS */
  994. #define WM8985_HALFIPBIAS_SHIFT 7 /* HALFIPBIAS */
  995. #define WM8985_HALFIPBIAS_WIDTH 1 /* HALFIPBIAS */
  996. #define WM8758_HALFIPBIAS 0x0040 /* HALFI_IPGA */
  997. #define WM8758_HALFI_IPGA_MASK 0x0040 /* HALFI_IPGA */
  998. #define WM8758_HALFI_IPGA_SHIFT 6 /* HALFI_IPGA */
  999. #define WM8758_HALFI_IPGA_WIDTH 1 /* HALFI_IPGA */
  1000. #define WM8985_VBBIASTST_MASK 0x0060 /* VBBIASTST - [6:5] */
  1001. #define WM8985_VBBIASTST_SHIFT 5 /* VBBIASTST - [6:5] */
  1002. #define WM8985_VBBIASTST_WIDTH 2 /* VBBIASTST - [6:5] */
  1003. #define WM8985_BUFBIAS_MASK 0x0018 /* BUFBIAS - [4:3] */
  1004. #define WM8985_BUFBIAS_SHIFT 3 /* BUFBIAS - [4:3] */
  1005. #define WM8985_BUFBIAS_WIDTH 2 /* BUFBIAS - [4:3] */
  1006. #define WM8985_ADCBIAS_MASK 0x0006 /* ADCBIAS - [2:1] */
  1007. #define WM8985_ADCBIAS_SHIFT 1 /* ADCBIAS - [2:1] */
  1008. #define WM8985_ADCBIAS_WIDTH 2 /* ADCBIAS - [2:1] */
  1009. #define WM8985_HALFOPBIAS 0x0001 /* HALFOPBIAS */
  1010. #define WM8985_HALFOPBIAS_MASK 0x0001 /* HALFOPBIAS */
  1011. #define WM8985_HALFOPBIAS_SHIFT 0 /* HALFOPBIAS */
  1012. #define WM8985_HALFOPBIAS_WIDTH 1 /* HALFOPBIAS */
  1013. enum clk_src {
  1014. WM8985_CLKSRC_MCLK,
  1015. WM8985_CLKSRC_PLL
  1016. };
  1017. #define WM8985_PLL 0
  1018. #endif