wm8985.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8985.c -- WM8985 / WM8758 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010 Wolfson Microelectronics plc
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * WM8758 support:
  9. * Copyright: 2016 Barix AG
  10. * Author: Petr Kulhavy <petr@barix.com>
  11. *
  12. * TODO:
  13. * o Add OUT3/OUT4 mixer controls.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/pm.h>
  20. #include <linux/i2c.h>
  21. #include <linux/regmap.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/slab.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/soc.h>
  29. #include <sound/initval.h>
  30. #include <sound/tlv.h>
  31. #include "wm8985.h"
  32. #define WM8985_NUM_SUPPLIES 4
  33. static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
  34. "DCVDD",
  35. "DBVDD",
  36. "AVDD1",
  37. "AVDD2"
  38. };
  39. enum wm8985_type {
  40. WM8985,
  41. WM8758,
  42. };
  43. static const struct reg_default wm8985_reg_defaults[] = {
  44. { 1, 0x0000 }, /* R1 - Power management 1 */
  45. { 2, 0x0000 }, /* R2 - Power management 2 */
  46. { 3, 0x0000 }, /* R3 - Power management 3 */
  47. { 4, 0x0050 }, /* R4 - Audio Interface */
  48. { 5, 0x0000 }, /* R5 - Companding control */
  49. { 6, 0x0140 }, /* R6 - Clock Gen control */
  50. { 7, 0x0000 }, /* R7 - Additional control */
  51. { 8, 0x0000 }, /* R8 - GPIO Control */
  52. { 9, 0x0000 }, /* R9 - Jack Detect Control 1 */
  53. { 10, 0x0000 }, /* R10 - DAC Control */
  54. { 11, 0x00FF }, /* R11 - Left DAC digital Vol */
  55. { 12, 0x00FF }, /* R12 - Right DAC digital vol */
  56. { 13, 0x0000 }, /* R13 - Jack Detect Control 2 */
  57. { 14, 0x0100 }, /* R14 - ADC Control */
  58. { 15, 0x00FF }, /* R15 - Left ADC Digital Vol */
  59. { 16, 0x00FF }, /* R16 - Right ADC Digital Vol */
  60. { 18, 0x012C }, /* R18 - EQ1 - low shelf */
  61. { 19, 0x002C }, /* R19 - EQ2 - peak 1 */
  62. { 20, 0x002C }, /* R20 - EQ3 - peak 2 */
  63. { 21, 0x002C }, /* R21 - EQ4 - peak 3 */
  64. { 22, 0x002C }, /* R22 - EQ5 - high shelf */
  65. { 24, 0x0032 }, /* R24 - DAC Limiter 1 */
  66. { 25, 0x0000 }, /* R25 - DAC Limiter 2 */
  67. { 27, 0x0000 }, /* R27 - Notch Filter 1 */
  68. { 28, 0x0000 }, /* R28 - Notch Filter 2 */
  69. { 29, 0x0000 }, /* R29 - Notch Filter 3 */
  70. { 30, 0x0000 }, /* R30 - Notch Filter 4 */
  71. { 32, 0x0038 }, /* R32 - ALC control 1 */
  72. { 33, 0x000B }, /* R33 - ALC control 2 */
  73. { 34, 0x0032 }, /* R34 - ALC control 3 */
  74. { 35, 0x0000 }, /* R35 - Noise Gate */
  75. { 36, 0x0008 }, /* R36 - PLL N */
  76. { 37, 0x000C }, /* R37 - PLL K 1 */
  77. { 38, 0x0093 }, /* R38 - PLL K 2 */
  78. { 39, 0x00E9 }, /* R39 - PLL K 3 */
  79. { 41, 0x0000 }, /* R41 - 3D control */
  80. { 42, 0x0000 }, /* R42 - OUT4 to ADC */
  81. { 43, 0x0000 }, /* R43 - Beep control */
  82. { 44, 0x0033 }, /* R44 - Input ctrl */
  83. { 45, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
  84. { 46, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
  85. { 47, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
  86. { 48, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
  87. { 49, 0x0002 }, /* R49 - Output ctrl */
  88. { 50, 0x0001 }, /* R50 - Left mixer ctrl */
  89. { 51, 0x0001 }, /* R51 - Right mixer ctrl */
  90. { 52, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
  91. { 53, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
  92. { 54, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
  93. { 55, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
  94. { 56, 0x0001 }, /* R56 - OUT3 mixer ctrl */
  95. { 57, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
  96. { 60, 0x0004 }, /* R60 - OUTPUT ctrl */
  97. { 61, 0x0000 }, /* R61 - BIAS CTRL */
  98. };
  99. static bool wm8985_writeable(struct device *dev, unsigned int reg)
  100. {
  101. switch (reg) {
  102. case WM8985_SOFTWARE_RESET:
  103. case WM8985_POWER_MANAGEMENT_1:
  104. case WM8985_POWER_MANAGEMENT_2:
  105. case WM8985_POWER_MANAGEMENT_3:
  106. case WM8985_AUDIO_INTERFACE:
  107. case WM8985_COMPANDING_CONTROL:
  108. case WM8985_CLOCK_GEN_CONTROL:
  109. case WM8985_ADDITIONAL_CONTROL:
  110. case WM8985_GPIO_CONTROL:
  111. case WM8985_JACK_DETECT_CONTROL_1:
  112. case WM8985_DAC_CONTROL:
  113. case WM8985_LEFT_DAC_DIGITAL_VOL:
  114. case WM8985_RIGHT_DAC_DIGITAL_VOL:
  115. case WM8985_JACK_DETECT_CONTROL_2:
  116. case WM8985_ADC_CONTROL:
  117. case WM8985_LEFT_ADC_DIGITAL_VOL:
  118. case WM8985_RIGHT_ADC_DIGITAL_VOL:
  119. case WM8985_EQ1_LOW_SHELF:
  120. case WM8985_EQ2_PEAK_1:
  121. case WM8985_EQ3_PEAK_2:
  122. case WM8985_EQ4_PEAK_3:
  123. case WM8985_EQ5_HIGH_SHELF:
  124. case WM8985_DAC_LIMITER_1:
  125. case WM8985_DAC_LIMITER_2:
  126. case WM8985_NOTCH_FILTER_1:
  127. case WM8985_NOTCH_FILTER_2:
  128. case WM8985_NOTCH_FILTER_3:
  129. case WM8985_NOTCH_FILTER_4:
  130. case WM8985_ALC_CONTROL_1:
  131. case WM8985_ALC_CONTROL_2:
  132. case WM8985_ALC_CONTROL_3:
  133. case WM8985_NOISE_GATE:
  134. case WM8985_PLL_N:
  135. case WM8985_PLL_K_1:
  136. case WM8985_PLL_K_2:
  137. case WM8985_PLL_K_3:
  138. case WM8985_3D_CONTROL:
  139. case WM8985_OUT4_TO_ADC:
  140. case WM8985_BEEP_CONTROL:
  141. case WM8985_INPUT_CTRL:
  142. case WM8985_LEFT_INP_PGA_GAIN_CTRL:
  143. case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
  144. case WM8985_LEFT_ADC_BOOST_CTRL:
  145. case WM8985_RIGHT_ADC_BOOST_CTRL:
  146. case WM8985_OUTPUT_CTRL0:
  147. case WM8985_LEFT_MIXER_CTRL:
  148. case WM8985_RIGHT_MIXER_CTRL:
  149. case WM8985_LOUT1_HP_VOLUME_CTRL:
  150. case WM8985_ROUT1_HP_VOLUME_CTRL:
  151. case WM8985_LOUT2_SPK_VOLUME_CTRL:
  152. case WM8985_ROUT2_SPK_VOLUME_CTRL:
  153. case WM8985_OUT3_MIXER_CTRL:
  154. case WM8985_OUT4_MONO_MIX_CTRL:
  155. case WM8985_OUTPUT_CTRL1:
  156. case WM8985_BIAS_CTRL:
  157. return true;
  158. default:
  159. return false;
  160. }
  161. }
  162. /*
  163. * latch bit 8 of these registers to ensure instant
  164. * volume updates
  165. */
  166. static const int volume_update_regs[] = {
  167. WM8985_LEFT_DAC_DIGITAL_VOL,
  168. WM8985_RIGHT_DAC_DIGITAL_VOL,
  169. WM8985_LEFT_ADC_DIGITAL_VOL,
  170. WM8985_RIGHT_ADC_DIGITAL_VOL,
  171. WM8985_LOUT2_SPK_VOLUME_CTRL,
  172. WM8985_ROUT2_SPK_VOLUME_CTRL,
  173. WM8985_LOUT1_HP_VOLUME_CTRL,
  174. WM8985_ROUT1_HP_VOLUME_CTRL,
  175. WM8985_LEFT_INP_PGA_GAIN_CTRL,
  176. WM8985_RIGHT_INP_PGA_GAIN_CTRL
  177. };
  178. struct wm8985_priv {
  179. struct regmap *regmap;
  180. struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
  181. enum wm8985_type dev_type;
  182. unsigned int sysclk;
  183. unsigned int bclk;
  184. };
  185. static const struct {
  186. int div;
  187. int ratio;
  188. } fs_ratios[] = {
  189. { 10, 128 },
  190. { 15, 192 },
  191. { 20, 256 },
  192. { 30, 384 },
  193. { 40, 512 },
  194. { 60, 768 },
  195. { 80, 1024 },
  196. { 120, 1536 }
  197. };
  198. static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
  199. static const int bclk_divs[] = {
  200. 1, 2, 4, 8, 16, 32
  201. };
  202. static int eqmode_get(struct snd_kcontrol *kcontrol,
  203. struct snd_ctl_elem_value *ucontrol);
  204. static int eqmode_put(struct snd_kcontrol *kcontrol,
  205. struct snd_ctl_elem_value *ucontrol);
  206. static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
  207. static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
  208. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  209. static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
  210. static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
  211. static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
  212. static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
  213. static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
  214. static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
  215. static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
  216. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  217. static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
  218. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  219. static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
  220. static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
  221. static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
  222. static const char *alc_mode_text[] = { "ALC", "Limiter" };
  223. static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
  224. static const char *filter_mode_text[] = { "Audio", "Application" };
  225. static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
  226. filter_mode_text);
  227. static const char *eq_bw_text[] = { "Narrow", "Wide" };
  228. static const char *eqmode_text[] = { "Capture", "Playback" };
  229. static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
  230. static const char *eq1_cutoff_text[] = {
  231. "80Hz", "105Hz", "135Hz", "175Hz"
  232. };
  233. static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
  234. eq1_cutoff_text);
  235. static const char *eq2_cutoff_text[] = {
  236. "230Hz", "300Hz", "385Hz", "500Hz"
  237. };
  238. static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
  239. static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
  240. static const char *eq3_cutoff_text[] = {
  241. "650Hz", "850Hz", "1.1kHz", "1.4kHz"
  242. };
  243. static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
  244. static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
  245. eq3_cutoff_text);
  246. static const char *eq4_cutoff_text[] = {
  247. "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
  248. };
  249. static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
  250. static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
  251. static const char *eq5_cutoff_text[] = {
  252. "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
  253. };
  254. static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
  255. eq5_cutoff_text);
  256. static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
  257. static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
  258. static const char *depth_3d_text[] = {
  259. "Off",
  260. "6.67%",
  261. "13.3%",
  262. "20%",
  263. "26.7%",
  264. "33.3%",
  265. "40%",
  266. "46.6%",
  267. "53.3%",
  268. "60%",
  269. "66.7%",
  270. "73.3%",
  271. "80%",
  272. "86.7%",
  273. "93.3%",
  274. "100%"
  275. };
  276. static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
  277. static const struct snd_kcontrol_new wm8985_common_snd_controls[] = {
  278. SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
  279. 0, 1, 0),
  280. SOC_ENUM("ALC Capture Function", alc_sel),
  281. SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
  282. 3, 7, 0, alc_max_tlv),
  283. SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
  284. 0, 7, 0, alc_min_tlv),
  285. SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
  286. 0, 15, 0, alc_tar_tlv),
  287. SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
  288. SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
  289. SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
  290. SOC_ENUM("ALC Mode", alc_mode),
  291. SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
  292. 3, 1, 0),
  293. SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
  294. 0, 7, 1),
  295. SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
  296. WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
  297. SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
  298. WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
  299. SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
  300. WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
  301. SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
  302. WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
  303. 8, 1, 0, pga_boost_tlv),
  304. SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
  305. SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
  306. SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
  307. WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
  308. SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
  309. SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
  310. SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
  311. SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
  312. 4, 7, 1, lim_thresh_tlv),
  313. SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
  314. 0, 12, 0, lim_boost_tlv),
  315. SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
  316. SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
  317. SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
  318. SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
  319. WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
  320. SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
  321. WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
  322. SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
  323. WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
  324. SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
  325. WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
  326. SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
  327. WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
  328. SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
  329. WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
  330. SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
  331. SOC_ENUM("High Pass Filter Mode", filter_mode),
  332. SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
  333. SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
  334. WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
  335. bypass_tlv),
  336. SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
  337. SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
  338. SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
  339. SOC_ENUM("EQ2 Bandwidth", eq2_bw),
  340. SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
  341. SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
  342. SOC_ENUM("EQ3 Bandwidth", eq3_bw),
  343. SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
  344. SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
  345. SOC_ENUM("EQ4 Bandwidth", eq4_bw),
  346. SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
  347. SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
  348. SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
  349. SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
  350. SOC_ENUM("3D Depth", depth_3d),
  351. };
  352. static const struct snd_kcontrol_new wm8985_specific_snd_controls[] = {
  353. SOC_DOUBLE_R_TLV("Aux Bypass Volume",
  354. WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
  355. aux_tlv),
  356. SOC_ENUM("Speaker Mode", speaker_mode)
  357. };
  358. static const struct snd_kcontrol_new left_out_mixer[] = {
  359. SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
  360. SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
  361. /* --- WM8985 only --- */
  362. SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
  363. };
  364. static const struct snd_kcontrol_new right_out_mixer[] = {
  365. SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
  366. SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
  367. /* --- WM8985 only --- */
  368. SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
  369. };
  370. static const struct snd_kcontrol_new left_input_mixer[] = {
  371. SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
  372. SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
  373. SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
  374. };
  375. static const struct snd_kcontrol_new right_input_mixer[] = {
  376. SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
  377. SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
  378. SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
  379. };
  380. static const struct snd_kcontrol_new left_boost_mixer[] = {
  381. SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
  382. 4, 7, 0, boost_tlv),
  383. /* --- WM8985 only --- */
  384. SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
  385. 0, 7, 0, boost_tlv)
  386. };
  387. static const struct snd_kcontrol_new right_boost_mixer[] = {
  388. SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
  389. 4, 7, 0, boost_tlv),
  390. /* --- WM8985 only --- */
  391. SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
  392. 0, 7, 0, boost_tlv)
  393. };
  394. static const struct snd_soc_dapm_widget wm8985_common_dapm_widgets[] = {
  395. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
  396. 0, 0),
  397. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
  398. 1, 0),
  399. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
  400. 0, 0),
  401. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
  402. 1, 0),
  403. SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
  404. 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
  405. SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
  406. 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
  407. SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
  408. 6, 1, NULL, 0),
  409. SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
  410. 6, 1, NULL, 0),
  411. SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
  412. 7, 0, NULL, 0),
  413. SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
  414. 8, 0, NULL, 0),
  415. SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
  416. 5, 0, NULL, 0),
  417. SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
  418. 6, 0, NULL, 0),
  419. SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
  420. NULL, 0),
  421. SND_SOC_DAPM_INPUT("LIN"),
  422. SND_SOC_DAPM_INPUT("LIP"),
  423. SND_SOC_DAPM_INPUT("RIN"),
  424. SND_SOC_DAPM_INPUT("RIP"),
  425. SND_SOC_DAPM_INPUT("L2"),
  426. SND_SOC_DAPM_INPUT("R2"),
  427. SND_SOC_DAPM_OUTPUT("HPL"),
  428. SND_SOC_DAPM_OUTPUT("HPR"),
  429. SND_SOC_DAPM_OUTPUT("SPKL"),
  430. SND_SOC_DAPM_OUTPUT("SPKR")
  431. };
  432. static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
  433. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
  434. 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
  435. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
  436. 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
  437. SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
  438. 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
  439. SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
  440. 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
  441. SND_SOC_DAPM_INPUT("AUXL"),
  442. SND_SOC_DAPM_INPUT("AUXR"),
  443. };
  444. static const struct snd_soc_dapm_widget wm8758_dapm_widgets[] = {
  445. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
  446. 2, 0, left_out_mixer,
  447. ARRAY_SIZE(left_out_mixer) - 1),
  448. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
  449. 3, 0, right_out_mixer,
  450. ARRAY_SIZE(right_out_mixer) - 1),
  451. SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
  452. 4, 0, left_boost_mixer,
  453. ARRAY_SIZE(left_boost_mixer) - 1),
  454. SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
  455. 5, 0, right_boost_mixer,
  456. ARRAY_SIZE(right_boost_mixer) - 1),
  457. };
  458. static const struct snd_soc_dapm_route wm8985_common_dapm_routes[] = {
  459. { "Right Output Mixer", "PCM Switch", "Right DAC" },
  460. { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
  461. { "Left Output Mixer", "PCM Switch", "Left DAC" },
  462. { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
  463. { "Right Headphone Out", NULL, "Right Output Mixer" },
  464. { "HPR", NULL, "Right Headphone Out" },
  465. { "Left Headphone Out", NULL, "Left Output Mixer" },
  466. { "HPL", NULL, "Left Headphone Out" },
  467. { "Right Speaker Out", NULL, "Right Output Mixer" },
  468. { "SPKR", NULL, "Right Speaker Out" },
  469. { "Left Speaker Out", NULL, "Left Output Mixer" },
  470. { "SPKL", NULL, "Left Speaker Out" },
  471. { "Right ADC", NULL, "Right Boost Mixer" },
  472. { "Right Boost Mixer", NULL, "Right Capture PGA" },
  473. { "Right Boost Mixer", "R2 Volume", "R2" },
  474. { "Left ADC", NULL, "Left Boost Mixer" },
  475. { "Left Boost Mixer", NULL, "Left Capture PGA" },
  476. { "Left Boost Mixer", "L2 Volume", "L2" },
  477. { "Right Capture PGA", NULL, "Right Input Mixer" },
  478. { "Left Capture PGA", NULL, "Left Input Mixer" },
  479. { "Right Input Mixer", "R2 Switch", "R2" },
  480. { "Right Input Mixer", "MicN Switch", "RIN" },
  481. { "Right Input Mixer", "MicP Switch", "RIP" },
  482. { "Left Input Mixer", "L2 Switch", "L2" },
  483. { "Left Input Mixer", "MicN Switch", "LIN" },
  484. { "Left Input Mixer", "MicP Switch", "LIP" },
  485. };
  486. static const struct snd_soc_dapm_route wm8985_aux_dapm_routes[] = {
  487. { "Right Output Mixer", "Aux Switch", "AUXR" },
  488. { "Left Output Mixer", "Aux Switch", "AUXL" },
  489. { "Right Boost Mixer", "AUXR Volume", "AUXR" },
  490. { "Left Boost Mixer", "AUXL Volume", "AUXL" },
  491. };
  492. static int wm8985_add_widgets(struct snd_soc_component *component)
  493. {
  494. struct wm8985_priv *wm8985 = snd_soc_component_get_drvdata(component);
  495. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  496. switch (wm8985->dev_type) {
  497. case WM8758:
  498. snd_soc_dapm_new_controls(dapm, wm8758_dapm_widgets,
  499. ARRAY_SIZE(wm8758_dapm_widgets));
  500. break;
  501. case WM8985:
  502. snd_soc_add_component_controls(component, wm8985_specific_snd_controls,
  503. ARRAY_SIZE(wm8985_specific_snd_controls));
  504. snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
  505. ARRAY_SIZE(wm8985_dapm_widgets));
  506. snd_soc_dapm_add_routes(dapm, wm8985_aux_dapm_routes,
  507. ARRAY_SIZE(wm8985_aux_dapm_routes));
  508. break;
  509. }
  510. return 0;
  511. }
  512. static int eqmode_get(struct snd_kcontrol *kcontrol,
  513. struct snd_ctl_elem_value *ucontrol)
  514. {
  515. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  516. unsigned int reg;
  517. reg = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
  518. if (reg & WM8985_EQ3DMODE)
  519. ucontrol->value.enumerated.item[0] = 1;
  520. else
  521. ucontrol->value.enumerated.item[0] = 0;
  522. return 0;
  523. }
  524. static int eqmode_put(struct snd_kcontrol *kcontrol,
  525. struct snd_ctl_elem_value *ucontrol)
  526. {
  527. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  528. unsigned int regpwr2, regpwr3;
  529. unsigned int reg_eq;
  530. if (ucontrol->value.enumerated.item[0] != 0
  531. && ucontrol->value.enumerated.item[0] != 1)
  532. return -EINVAL;
  533. reg_eq = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
  534. switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
  535. case 0:
  536. if (!ucontrol->value.enumerated.item[0])
  537. return 0;
  538. break;
  539. case 1:
  540. if (ucontrol->value.enumerated.item[0])
  541. return 0;
  542. break;
  543. }
  544. regpwr2 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_2);
  545. regpwr3 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_3);
  546. /* disable the DACs and ADCs */
  547. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_2,
  548. WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
  549. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_3,
  550. WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
  551. snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
  552. WM8985_M128ENB_MASK, WM8985_M128ENB);
  553. /* set the desired eqmode */
  554. snd_soc_component_update_bits(component, WM8985_EQ1_LOW_SHELF,
  555. WM8985_EQ3DMODE_MASK,
  556. ucontrol->value.enumerated.item[0]
  557. << WM8985_EQ3DMODE_SHIFT);
  558. /* restore DAC/ADC configuration */
  559. snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, regpwr2);
  560. snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, regpwr3);
  561. return 0;
  562. }
  563. static int wm8985_reset(struct snd_soc_component *component)
  564. {
  565. return snd_soc_component_write(component, WM8985_SOFTWARE_RESET, 0x0);
  566. }
  567. static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
  568. {
  569. struct snd_soc_component *component = dai->component;
  570. return snd_soc_component_update_bits(component, WM8985_DAC_CONTROL,
  571. WM8985_SOFTMUTE_MASK,
  572. !!mute << WM8985_SOFTMUTE_SHIFT);
  573. }
  574. static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  575. {
  576. struct snd_soc_component *component;
  577. u16 format, master, bcp, lrp;
  578. component = dai->component;
  579. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  580. case SND_SOC_DAIFMT_I2S:
  581. format = 0x2;
  582. break;
  583. case SND_SOC_DAIFMT_RIGHT_J:
  584. format = 0x0;
  585. break;
  586. case SND_SOC_DAIFMT_LEFT_J:
  587. format = 0x1;
  588. break;
  589. case SND_SOC_DAIFMT_DSP_A:
  590. case SND_SOC_DAIFMT_DSP_B:
  591. format = 0x3;
  592. break;
  593. default:
  594. dev_err(dai->dev, "Unknown dai format\n");
  595. return -EINVAL;
  596. }
  597. snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
  598. WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
  599. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  600. case SND_SOC_DAIFMT_CBM_CFM:
  601. master = 1;
  602. break;
  603. case SND_SOC_DAIFMT_CBS_CFS:
  604. master = 0;
  605. break;
  606. default:
  607. dev_err(dai->dev, "Unknown master/slave configuration\n");
  608. return -EINVAL;
  609. }
  610. snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
  611. WM8985_MS_MASK, master << WM8985_MS_SHIFT);
  612. /* frame inversion is not valid for dsp modes */
  613. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  614. case SND_SOC_DAIFMT_DSP_A:
  615. case SND_SOC_DAIFMT_DSP_B:
  616. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  617. case SND_SOC_DAIFMT_IB_IF:
  618. case SND_SOC_DAIFMT_NB_IF:
  619. return -EINVAL;
  620. default:
  621. break;
  622. }
  623. break;
  624. default:
  625. break;
  626. }
  627. bcp = lrp = 0;
  628. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  629. case SND_SOC_DAIFMT_NB_NF:
  630. break;
  631. case SND_SOC_DAIFMT_IB_IF:
  632. bcp = lrp = 1;
  633. break;
  634. case SND_SOC_DAIFMT_IB_NF:
  635. bcp = 1;
  636. break;
  637. case SND_SOC_DAIFMT_NB_IF:
  638. lrp = 1;
  639. break;
  640. default:
  641. dev_err(dai->dev, "Unknown polarity configuration\n");
  642. return -EINVAL;
  643. }
  644. snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
  645. WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
  646. snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
  647. WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
  648. return 0;
  649. }
  650. static int wm8985_hw_params(struct snd_pcm_substream *substream,
  651. struct snd_pcm_hw_params *params,
  652. struct snd_soc_dai *dai)
  653. {
  654. int i;
  655. struct snd_soc_component *component;
  656. struct wm8985_priv *wm8985;
  657. u16 blen, srate_idx;
  658. unsigned int tmp;
  659. int srate_best;
  660. component = dai->component;
  661. wm8985 = snd_soc_component_get_drvdata(component);
  662. wm8985->bclk = snd_soc_params_to_bclk(params);
  663. if ((int)wm8985->bclk < 0)
  664. return wm8985->bclk;
  665. switch (params_width(params)) {
  666. case 16:
  667. blen = 0x0;
  668. break;
  669. case 20:
  670. blen = 0x1;
  671. break;
  672. case 24:
  673. blen = 0x2;
  674. break;
  675. case 32:
  676. blen = 0x3;
  677. break;
  678. default:
  679. dev_err(dai->dev, "Unsupported word length %u\n",
  680. params_width(params));
  681. return -EINVAL;
  682. }
  683. snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
  684. WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
  685. /*
  686. * match to the nearest possible sample rate and rely
  687. * on the array index to configure the SR register
  688. */
  689. srate_idx = 0;
  690. srate_best = abs(srates[0] - params_rate(params));
  691. for (i = 1; i < ARRAY_SIZE(srates); ++i) {
  692. if (abs(srates[i] - params_rate(params)) >= srate_best)
  693. continue;
  694. srate_idx = i;
  695. srate_best = abs(srates[i] - params_rate(params));
  696. }
  697. dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
  698. snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
  699. WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
  700. dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
  701. dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
  702. for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
  703. if (wm8985->sysclk / params_rate(params)
  704. == fs_ratios[i].ratio)
  705. break;
  706. }
  707. if (i == ARRAY_SIZE(fs_ratios)) {
  708. dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
  709. wm8985->sysclk, params_rate(params));
  710. return -EINVAL;
  711. }
  712. dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
  713. snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
  714. WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
  715. /* select the appropriate bclk divider */
  716. tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
  717. for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
  718. if (wm8985->bclk == tmp / bclk_divs[i])
  719. break;
  720. }
  721. if (i == ARRAY_SIZE(bclk_divs)) {
  722. dev_err(dai->dev, "No matching BCLK divider found\n");
  723. return -EINVAL;
  724. }
  725. dev_dbg(dai->dev, "BCLK div = %d\n", i);
  726. snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
  727. WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
  728. return 0;
  729. }
  730. struct pll_div {
  731. u32 div2:1;
  732. u32 n:4;
  733. u32 k:24;
  734. };
  735. #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
  736. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  737. unsigned int source)
  738. {
  739. u64 Kpart;
  740. unsigned long int K, Ndiv, Nmod;
  741. pll_div->div2 = 0;
  742. Ndiv = target / source;
  743. if (Ndiv < 6) {
  744. source >>= 1;
  745. pll_div->div2 = 1;
  746. Ndiv = target / source;
  747. }
  748. if (Ndiv < 6 || Ndiv > 12) {
  749. printk(KERN_ERR "%s: WM8985 N value is not within"
  750. " the recommended range: %lu\n", __func__, Ndiv);
  751. return -EINVAL;
  752. }
  753. pll_div->n = Ndiv;
  754. Nmod = target % source;
  755. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  756. do_div(Kpart, source);
  757. K = Kpart & 0xffffffff;
  758. if ((K % 10) >= 5)
  759. K += 5;
  760. K /= 10;
  761. pll_div->k = K;
  762. return 0;
  763. }
  764. static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
  765. int source, unsigned int freq_in,
  766. unsigned int freq_out)
  767. {
  768. int ret;
  769. struct snd_soc_component *component;
  770. struct pll_div pll_div;
  771. component = dai->component;
  772. if (!freq_in || !freq_out) {
  773. /* disable the PLL */
  774. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  775. WM8985_PLLEN_MASK, 0);
  776. } else {
  777. ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
  778. if (ret)
  779. return ret;
  780. /* set PLLN and PRESCALE */
  781. snd_soc_component_write(component, WM8985_PLL_N,
  782. (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
  783. | pll_div.n);
  784. /* set PLLK */
  785. snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff);
  786. snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
  787. snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18));
  788. /* set the source of the clock to be the PLL */
  789. snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
  790. WM8985_CLKSEL_MASK, WM8985_CLKSEL);
  791. /* enable the PLL */
  792. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  793. WM8985_PLLEN_MASK, WM8985_PLLEN);
  794. }
  795. return 0;
  796. }
  797. static int wm8985_set_sysclk(struct snd_soc_dai *dai,
  798. int clk_id, unsigned int freq, int dir)
  799. {
  800. struct snd_soc_component *component;
  801. struct wm8985_priv *wm8985;
  802. component = dai->component;
  803. wm8985 = snd_soc_component_get_drvdata(component);
  804. switch (clk_id) {
  805. case WM8985_CLKSRC_MCLK:
  806. snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
  807. WM8985_CLKSEL_MASK, 0);
  808. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  809. WM8985_PLLEN_MASK, 0);
  810. break;
  811. case WM8985_CLKSRC_PLL:
  812. snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
  813. WM8985_CLKSEL_MASK, WM8985_CLKSEL);
  814. break;
  815. default:
  816. dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
  817. return -EINVAL;
  818. }
  819. wm8985->sysclk = freq;
  820. return 0;
  821. }
  822. static int wm8985_set_bias_level(struct snd_soc_component *component,
  823. enum snd_soc_bias_level level)
  824. {
  825. int ret;
  826. struct wm8985_priv *wm8985;
  827. wm8985 = snd_soc_component_get_drvdata(component);
  828. switch (level) {
  829. case SND_SOC_BIAS_ON:
  830. case SND_SOC_BIAS_PREPARE:
  831. /* VMID at 75k */
  832. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  833. WM8985_VMIDSEL_MASK,
  834. 1 << WM8985_VMIDSEL_SHIFT);
  835. break;
  836. case SND_SOC_BIAS_STANDBY:
  837. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  838. ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
  839. wm8985->supplies);
  840. if (ret) {
  841. dev_err(component->dev,
  842. "Failed to enable supplies: %d\n",
  843. ret);
  844. return ret;
  845. }
  846. regcache_sync(wm8985->regmap);
  847. /* enable anti-pop features */
  848. snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
  849. WM8985_POBCTRL_MASK,
  850. WM8985_POBCTRL);
  851. /* enable thermal shutdown */
  852. snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
  853. WM8985_TSDEN_MASK, WM8985_TSDEN);
  854. snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
  855. WM8985_TSOPCTRL_MASK,
  856. WM8985_TSOPCTRL);
  857. /* enable BIASEN */
  858. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  859. WM8985_BIASEN_MASK, WM8985_BIASEN);
  860. /* VMID at 75k */
  861. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  862. WM8985_VMIDSEL_MASK,
  863. 1 << WM8985_VMIDSEL_SHIFT);
  864. msleep(500);
  865. /* disable anti-pop features */
  866. snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
  867. WM8985_POBCTRL_MASK, 0);
  868. }
  869. /* VMID at 300k */
  870. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  871. WM8985_VMIDSEL_MASK,
  872. 2 << WM8985_VMIDSEL_SHIFT);
  873. break;
  874. case SND_SOC_BIAS_OFF:
  875. /* disable thermal shutdown */
  876. snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
  877. WM8985_TSOPCTRL_MASK, 0);
  878. snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
  879. WM8985_TSDEN_MASK, 0);
  880. /* disable VMIDSEL and BIASEN */
  881. snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
  882. WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
  883. 0);
  884. snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_1, 0);
  885. snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, 0);
  886. snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, 0);
  887. regcache_mark_dirty(wm8985->regmap);
  888. regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
  889. wm8985->supplies);
  890. break;
  891. }
  892. return 0;
  893. }
  894. static int wm8985_probe(struct snd_soc_component *component)
  895. {
  896. size_t i;
  897. struct wm8985_priv *wm8985;
  898. int ret;
  899. wm8985 = snd_soc_component_get_drvdata(component);
  900. for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
  901. wm8985->supplies[i].supply = wm8985_supply_names[i];
  902. ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8985->supplies),
  903. wm8985->supplies);
  904. if (ret) {
  905. dev_err(component->dev, "Failed to request supplies: %d\n", ret);
  906. return ret;
  907. }
  908. ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
  909. wm8985->supplies);
  910. if (ret) {
  911. dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
  912. return ret;
  913. }
  914. ret = wm8985_reset(component);
  915. if (ret < 0) {
  916. dev_err(component->dev, "Failed to issue reset: %d\n", ret);
  917. goto err_reg_enable;
  918. }
  919. /* latch volume update bits */
  920. for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
  921. snd_soc_component_update_bits(component, volume_update_regs[i],
  922. 0x100, 0x100);
  923. /* enable BIASCUT */
  924. snd_soc_component_update_bits(component, WM8985_BIAS_CTRL, WM8985_BIASCUT,
  925. WM8985_BIASCUT);
  926. wm8985_add_widgets(component);
  927. return 0;
  928. err_reg_enable:
  929. regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
  930. return ret;
  931. }
  932. static const struct snd_soc_dai_ops wm8985_dai_ops = {
  933. .mute_stream = wm8985_dac_mute,
  934. .hw_params = wm8985_hw_params,
  935. .set_fmt = wm8985_set_fmt,
  936. .set_sysclk = wm8985_set_sysclk,
  937. .set_pll = wm8985_set_pll,
  938. .no_capture_mute = 1,
  939. };
  940. #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  941. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  942. static struct snd_soc_dai_driver wm8985_dai = {
  943. .name = "wm8985-hifi",
  944. .playback = {
  945. .stream_name = "Playback",
  946. .channels_min = 2,
  947. .channels_max = 2,
  948. .rates = SNDRV_PCM_RATE_8000_48000,
  949. .formats = WM8985_FORMATS,
  950. },
  951. .capture = {
  952. .stream_name = "Capture",
  953. .channels_min = 2,
  954. .channels_max = 2,
  955. .rates = SNDRV_PCM_RATE_8000_48000,
  956. .formats = WM8985_FORMATS,
  957. },
  958. .ops = &wm8985_dai_ops,
  959. .symmetric_rates = 1
  960. };
  961. static const struct snd_soc_component_driver soc_component_dev_wm8985 = {
  962. .probe = wm8985_probe,
  963. .set_bias_level = wm8985_set_bias_level,
  964. .controls = wm8985_common_snd_controls,
  965. .num_controls = ARRAY_SIZE(wm8985_common_snd_controls),
  966. .dapm_widgets = wm8985_common_dapm_widgets,
  967. .num_dapm_widgets = ARRAY_SIZE(wm8985_common_dapm_widgets),
  968. .dapm_routes = wm8985_common_dapm_routes,
  969. .num_dapm_routes = ARRAY_SIZE(wm8985_common_dapm_routes),
  970. .suspend_bias_off = 1,
  971. .idle_bias_on = 1,
  972. .use_pmdown_time = 1,
  973. .endianness = 1,
  974. .non_legacy_dai_naming = 1,
  975. };
  976. static const struct regmap_config wm8985_regmap = {
  977. .reg_bits = 7,
  978. .val_bits = 9,
  979. .max_register = WM8985_MAX_REGISTER,
  980. .writeable_reg = wm8985_writeable,
  981. .cache_type = REGCACHE_RBTREE,
  982. .reg_defaults = wm8985_reg_defaults,
  983. .num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
  984. };
  985. #if defined(CONFIG_SPI_MASTER)
  986. static int wm8985_spi_probe(struct spi_device *spi)
  987. {
  988. struct wm8985_priv *wm8985;
  989. int ret;
  990. wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
  991. if (!wm8985)
  992. return -ENOMEM;
  993. spi_set_drvdata(spi, wm8985);
  994. wm8985->dev_type = WM8985;
  995. wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
  996. if (IS_ERR(wm8985->regmap)) {
  997. ret = PTR_ERR(wm8985->regmap);
  998. dev_err(&spi->dev, "Failed to allocate register map: %d\n",
  999. ret);
  1000. return ret;
  1001. }
  1002. ret = devm_snd_soc_register_component(&spi->dev,
  1003. &soc_component_dev_wm8985, &wm8985_dai, 1);
  1004. return ret;
  1005. }
  1006. static struct spi_driver wm8985_spi_driver = {
  1007. .driver = {
  1008. .name = "wm8985",
  1009. },
  1010. .probe = wm8985_spi_probe,
  1011. };
  1012. #endif
  1013. #if IS_ENABLED(CONFIG_I2C)
  1014. static int wm8985_i2c_probe(struct i2c_client *i2c,
  1015. const struct i2c_device_id *id)
  1016. {
  1017. struct wm8985_priv *wm8985;
  1018. int ret;
  1019. wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
  1020. if (!wm8985)
  1021. return -ENOMEM;
  1022. i2c_set_clientdata(i2c, wm8985);
  1023. wm8985->dev_type = id->driver_data;
  1024. wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
  1025. if (IS_ERR(wm8985->regmap)) {
  1026. ret = PTR_ERR(wm8985->regmap);
  1027. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1028. ret);
  1029. return ret;
  1030. }
  1031. ret = devm_snd_soc_register_component(&i2c->dev,
  1032. &soc_component_dev_wm8985, &wm8985_dai, 1);
  1033. return ret;
  1034. }
  1035. static const struct i2c_device_id wm8985_i2c_id[] = {
  1036. { "wm8985", WM8985 },
  1037. { "wm8758", WM8758 },
  1038. { }
  1039. };
  1040. MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
  1041. static struct i2c_driver wm8985_i2c_driver = {
  1042. .driver = {
  1043. .name = "wm8985",
  1044. },
  1045. .probe = wm8985_i2c_probe,
  1046. .id_table = wm8985_i2c_id
  1047. };
  1048. #endif
  1049. static int __init wm8985_modinit(void)
  1050. {
  1051. int ret = 0;
  1052. #if IS_ENABLED(CONFIG_I2C)
  1053. ret = i2c_add_driver(&wm8985_i2c_driver);
  1054. if (ret) {
  1055. printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
  1056. ret);
  1057. }
  1058. #endif
  1059. #if defined(CONFIG_SPI_MASTER)
  1060. ret = spi_register_driver(&wm8985_spi_driver);
  1061. if (ret != 0) {
  1062. printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
  1063. ret);
  1064. }
  1065. #endif
  1066. return ret;
  1067. }
  1068. module_init(wm8985_modinit);
  1069. static void __exit wm8985_exit(void)
  1070. {
  1071. #if IS_ENABLED(CONFIG_I2C)
  1072. i2c_del_driver(&wm8985_i2c_driver);
  1073. #endif
  1074. #if defined(CONFIG_SPI_MASTER)
  1075. spi_unregister_driver(&wm8985_spi_driver);
  1076. #endif
  1077. }
  1078. module_exit(wm8985_exit);
  1079. MODULE_DESCRIPTION("ASoC WM8985 / WM8758 driver");
  1080. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  1081. MODULE_LICENSE("GPL");