wm8983.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8983.c -- WM8983 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Wolfson Microelectronics plc
  6. *
  7. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/slab.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include <sound/initval.h>
  23. #include <sound/tlv.h>
  24. #include "wm8983.h"
  25. static const struct reg_default wm8983_defaults[] = {
  26. { 0x01, 0x0000 }, /* R1 - Power management 1 */
  27. { 0x02, 0x0000 }, /* R2 - Power management 2 */
  28. { 0x03, 0x0000 }, /* R3 - Power management 3 */
  29. { 0x04, 0x0050 }, /* R4 - Audio Interface */
  30. { 0x05, 0x0000 }, /* R5 - Companding control */
  31. { 0x06, 0x0140 }, /* R6 - Clock Gen control */
  32. { 0x07, 0x0000 }, /* R7 - Additional control */
  33. { 0x08, 0x0000 }, /* R8 - GPIO Control */
  34. { 0x09, 0x0000 }, /* R9 - Jack Detect Control 1 */
  35. { 0x0A, 0x0000 }, /* R10 - DAC Control */
  36. { 0x0B, 0x00FF }, /* R11 - Left DAC digital Vol */
  37. { 0x0C, 0x00FF }, /* R12 - Right DAC digital vol */
  38. { 0x0D, 0x0000 }, /* R13 - Jack Detect Control 2 */
  39. { 0x0E, 0x0100 }, /* R14 - ADC Control */
  40. { 0x0F, 0x00FF }, /* R15 - Left ADC Digital Vol */
  41. { 0x10, 0x00FF }, /* R16 - Right ADC Digital Vol */
  42. { 0x12, 0x012C }, /* R18 - EQ1 - low shelf */
  43. { 0x13, 0x002C }, /* R19 - EQ2 - peak 1 */
  44. { 0x14, 0x002C }, /* R20 - EQ3 - peak 2 */
  45. { 0x15, 0x002C }, /* R21 - EQ4 - peak 3 */
  46. { 0x16, 0x002C }, /* R22 - EQ5 - high shelf */
  47. { 0x18, 0x0032 }, /* R24 - DAC Limiter 1 */
  48. { 0x19, 0x0000 }, /* R25 - DAC Limiter 2 */
  49. { 0x1B, 0x0000 }, /* R27 - Notch Filter 1 */
  50. { 0x1C, 0x0000 }, /* R28 - Notch Filter 2 */
  51. { 0x1D, 0x0000 }, /* R29 - Notch Filter 3 */
  52. { 0x1E, 0x0000 }, /* R30 - Notch Filter 4 */
  53. { 0x20, 0x0038 }, /* R32 - ALC control 1 */
  54. { 0x21, 0x000B }, /* R33 - ALC control 2 */
  55. { 0x22, 0x0032 }, /* R34 - ALC control 3 */
  56. { 0x23, 0x0000 }, /* R35 - Noise Gate */
  57. { 0x24, 0x0008 }, /* R36 - PLL N */
  58. { 0x25, 0x000C }, /* R37 - PLL K 1 */
  59. { 0x26, 0x0093 }, /* R38 - PLL K 2 */
  60. { 0x27, 0x00E9 }, /* R39 - PLL K 3 */
  61. { 0x29, 0x0000 }, /* R41 - 3D control */
  62. { 0x2A, 0x0000 }, /* R42 - OUT4 to ADC */
  63. { 0x2B, 0x0000 }, /* R43 - Beep control */
  64. { 0x2C, 0x0033 }, /* R44 - Input ctrl */
  65. { 0x2D, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
  66. { 0x2E, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
  67. { 0x2F, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
  68. { 0x30, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
  69. { 0x31, 0x0002 }, /* R49 - Output ctrl */
  70. { 0x32, 0x0001 }, /* R50 - Left mixer ctrl */
  71. { 0x33, 0x0001 }, /* R51 - Right mixer ctrl */
  72. { 0x34, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
  73. { 0x35, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
  74. { 0x36, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
  75. { 0x37, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
  76. { 0x38, 0x0001 }, /* R56 - OUT3 mixer ctrl */
  77. { 0x39, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
  78. { 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
  79. };
  80. /* vol/gain update regs */
  81. static const int vol_update_regs[] = {
  82. WM8983_LEFT_DAC_DIGITAL_VOL,
  83. WM8983_RIGHT_DAC_DIGITAL_VOL,
  84. WM8983_LEFT_ADC_DIGITAL_VOL,
  85. WM8983_RIGHT_ADC_DIGITAL_VOL,
  86. WM8983_LOUT1_HP_VOLUME_CTRL,
  87. WM8983_ROUT1_HP_VOLUME_CTRL,
  88. WM8983_LOUT2_SPK_VOLUME_CTRL,
  89. WM8983_ROUT2_SPK_VOLUME_CTRL,
  90. WM8983_LEFT_INP_PGA_GAIN_CTRL,
  91. WM8983_RIGHT_INP_PGA_GAIN_CTRL
  92. };
  93. struct wm8983_priv {
  94. struct regmap *regmap;
  95. u32 sysclk;
  96. u32 bclk;
  97. };
  98. static const struct {
  99. int div;
  100. int ratio;
  101. } fs_ratios[] = {
  102. { 10, 128 },
  103. { 15, 192 },
  104. { 20, 256 },
  105. { 30, 384 },
  106. { 40, 512 },
  107. { 60, 768 },
  108. { 80, 1024 },
  109. { 120, 1536 }
  110. };
  111. static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
  112. static const int bclk_divs[] = {
  113. 1, 2, 4, 8, 16, 32
  114. };
  115. static int eqmode_get(struct snd_kcontrol *kcontrol,
  116. struct snd_ctl_elem_value *ucontrol);
  117. static int eqmode_put(struct snd_kcontrol *kcontrol,
  118. struct snd_ctl_elem_value *ucontrol);
  119. static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
  120. static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
  121. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  122. static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
  123. static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
  124. static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
  125. static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
  126. static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
  127. static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
  128. static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
  129. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  130. static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
  131. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  132. static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
  133. static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
  134. static SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, alc_sel_text);
  135. static const char *alc_mode_text[] = { "ALC", "Limiter" };
  136. static SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, alc_mode_text);
  137. static const char *filter_mode_text[] = { "Audio", "Application" };
  138. static SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
  139. filter_mode_text);
  140. static const char *eq_bw_text[] = { "Narrow", "Wide" };
  141. static const char *eqmode_text[] = { "Capture", "Playback" };
  142. static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
  143. static const char *eq1_cutoff_text[] = {
  144. "80Hz", "105Hz", "135Hz", "175Hz"
  145. };
  146. static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
  147. eq1_cutoff_text);
  148. static const char *eq2_cutoff_text[] = {
  149. "230Hz", "300Hz", "385Hz", "500Hz"
  150. };
  151. static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
  152. static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, eq2_cutoff_text);
  153. static const char *eq3_cutoff_text[] = {
  154. "650Hz", "850Hz", "1.1kHz", "1.4kHz"
  155. };
  156. static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
  157. static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, eq3_cutoff_text);
  158. static const char *eq4_cutoff_text[] = {
  159. "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
  160. };
  161. static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
  162. static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, eq4_cutoff_text);
  163. static const char *eq5_cutoff_text[] = {
  164. "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
  165. };
  166. static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
  167. eq5_cutoff_text);
  168. static const char *depth_3d_text[] = {
  169. "Off",
  170. "6.67%",
  171. "13.3%",
  172. "20%",
  173. "26.7%",
  174. "33.3%",
  175. "40%",
  176. "46.6%",
  177. "53.3%",
  178. "60%",
  179. "66.7%",
  180. "73.3%",
  181. "80%",
  182. "86.7%",
  183. "93.3%",
  184. "100%"
  185. };
  186. static SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
  187. depth_3d_text);
  188. static const struct snd_kcontrol_new wm8983_snd_controls[] = {
  189. SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
  190. 0, 1, 0),
  191. SOC_ENUM("ALC Capture Function", alc_sel),
  192. SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
  193. 3, 7, 0, alc_max_tlv),
  194. SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
  195. 0, 7, 0, alc_min_tlv),
  196. SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
  197. 0, 15, 0, alc_tar_tlv),
  198. SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
  199. SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
  200. SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
  201. SOC_ENUM("ALC Mode", alc_mode),
  202. SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
  203. 3, 1, 0),
  204. SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
  205. 0, 7, 1),
  206. SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
  207. WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
  208. SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
  209. WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
  210. SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
  211. WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
  212. SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
  213. WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
  214. 8, 1, 0, pga_boost_tlv),
  215. SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
  216. SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
  217. SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
  218. WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
  219. SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
  220. SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
  221. SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
  222. SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
  223. 4, 7, 1, lim_thresh_tlv),
  224. SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
  225. 0, 12, 0, lim_boost_tlv),
  226. SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
  227. SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
  228. SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
  229. SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
  230. WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
  231. SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
  232. WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
  233. SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
  234. WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
  235. SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
  236. WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
  237. SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
  238. WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
  239. SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
  240. WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
  241. SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
  242. 6, 1, 1),
  243. SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
  244. 6, 1, 1),
  245. SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
  246. SOC_ENUM("High Pass Filter Mode", filter_mode),
  247. SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
  248. SOC_DOUBLE_R_TLV("Aux Bypass Volume",
  249. WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
  250. aux_tlv),
  251. SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
  252. WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
  253. bypass_tlv),
  254. SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
  255. SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
  256. SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
  257. SOC_ENUM("EQ2 Bandwidth", eq2_bw),
  258. SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
  259. SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
  260. SOC_ENUM("EQ3 Bandwidth", eq3_bw),
  261. SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
  262. SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
  263. SOC_ENUM("EQ4 Bandwidth", eq4_bw),
  264. SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
  265. SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
  266. SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
  267. SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
  268. SOC_ENUM("3D Depth", depth_3d),
  269. };
  270. static const struct snd_kcontrol_new left_out_mixer[] = {
  271. SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
  272. SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
  273. SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
  274. };
  275. static const struct snd_kcontrol_new right_out_mixer[] = {
  276. SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
  277. SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
  278. SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
  279. };
  280. static const struct snd_kcontrol_new left_input_mixer[] = {
  281. SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
  282. SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
  283. SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
  284. };
  285. static const struct snd_kcontrol_new right_input_mixer[] = {
  286. SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
  287. SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
  288. SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
  289. };
  290. static const struct snd_kcontrol_new left_boost_mixer[] = {
  291. SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
  292. 4, 7, 0, boost_tlv),
  293. SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
  294. 0, 7, 0, boost_tlv)
  295. };
  296. static const struct snd_kcontrol_new out3_mixer[] = {
  297. SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
  298. 1, 1, 0),
  299. SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
  300. 0, 1, 0),
  301. };
  302. static const struct snd_kcontrol_new out4_mixer[] = {
  303. SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
  304. 4, 1, 0),
  305. SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
  306. 1, 1, 0),
  307. SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
  308. 3, 1, 0),
  309. SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
  310. 0, 1, 0),
  311. };
  312. static const struct snd_kcontrol_new right_boost_mixer[] = {
  313. SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
  314. 4, 7, 0, boost_tlv),
  315. SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
  316. 0, 7, 0, boost_tlv)
  317. };
  318. static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
  319. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
  320. 0, 0),
  321. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
  322. 1, 0),
  323. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
  324. 0, 0),
  325. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
  326. 1, 0),
  327. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
  328. 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
  329. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
  330. 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
  331. SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
  332. 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
  333. SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
  334. 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
  335. SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
  336. 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
  337. SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
  338. 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
  339. SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
  340. 6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
  341. SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
  342. 7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
  343. SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
  344. 6, 1, NULL, 0),
  345. SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
  346. 6, 1, NULL, 0),
  347. SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
  348. 7, 0, NULL, 0),
  349. SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
  350. 8, 0, NULL, 0),
  351. SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
  352. 5, 0, NULL, 0),
  353. SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
  354. 6, 0, NULL, 0),
  355. SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
  356. 7, 0, NULL, 0),
  357. SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
  358. 8, 0, NULL, 0),
  359. SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0,
  360. NULL, 0),
  361. SND_SOC_DAPM_INPUT("LIN"),
  362. SND_SOC_DAPM_INPUT("LIP"),
  363. SND_SOC_DAPM_INPUT("RIN"),
  364. SND_SOC_DAPM_INPUT("RIP"),
  365. SND_SOC_DAPM_INPUT("AUXL"),
  366. SND_SOC_DAPM_INPUT("AUXR"),
  367. SND_SOC_DAPM_INPUT("L2"),
  368. SND_SOC_DAPM_INPUT("R2"),
  369. SND_SOC_DAPM_OUTPUT("HPL"),
  370. SND_SOC_DAPM_OUTPUT("HPR"),
  371. SND_SOC_DAPM_OUTPUT("SPKL"),
  372. SND_SOC_DAPM_OUTPUT("SPKR"),
  373. SND_SOC_DAPM_OUTPUT("OUT3"),
  374. SND_SOC_DAPM_OUTPUT("OUT4")
  375. };
  376. static const struct snd_soc_dapm_route wm8983_audio_map[] = {
  377. { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
  378. { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
  379. { "OUT3 Out", NULL, "OUT3 Mixer" },
  380. { "OUT3", NULL, "OUT3 Out" },
  381. { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
  382. { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
  383. { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
  384. { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
  385. { "OUT4 Out", NULL, "OUT4 Mixer" },
  386. { "OUT4", NULL, "OUT4 Out" },
  387. { "Right Output Mixer", "PCM Switch", "Right DAC" },
  388. { "Right Output Mixer", "Aux Switch", "AUXR" },
  389. { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
  390. { "Left Output Mixer", "PCM Switch", "Left DAC" },
  391. { "Left Output Mixer", "Aux Switch", "AUXL" },
  392. { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
  393. { "Right Headphone Out", NULL, "Right Output Mixer" },
  394. { "HPR", NULL, "Right Headphone Out" },
  395. { "Left Headphone Out", NULL, "Left Output Mixer" },
  396. { "HPL", NULL, "Left Headphone Out" },
  397. { "Right Speaker Out", NULL, "Right Output Mixer" },
  398. { "SPKR", NULL, "Right Speaker Out" },
  399. { "Left Speaker Out", NULL, "Left Output Mixer" },
  400. { "SPKL", NULL, "Left Speaker Out" },
  401. { "Right ADC", NULL, "Right Boost Mixer" },
  402. { "Right Boost Mixer", "AUXR Volume", "AUXR" },
  403. { "Right Boost Mixer", NULL, "Right Capture PGA" },
  404. { "Right Boost Mixer", "R2 Volume", "R2" },
  405. { "Left ADC", NULL, "Left Boost Mixer" },
  406. { "Left Boost Mixer", "AUXL Volume", "AUXL" },
  407. { "Left Boost Mixer", NULL, "Left Capture PGA" },
  408. { "Left Boost Mixer", "L2 Volume", "L2" },
  409. { "Right Capture PGA", NULL, "Right Input Mixer" },
  410. { "Left Capture PGA", NULL, "Left Input Mixer" },
  411. { "Right Input Mixer", "R2 Switch", "R2" },
  412. { "Right Input Mixer", "MicN Switch", "RIN" },
  413. { "Right Input Mixer", "MicP Switch", "RIP" },
  414. { "Left Input Mixer", "L2 Switch", "L2" },
  415. { "Left Input Mixer", "MicN Switch", "LIN" },
  416. { "Left Input Mixer", "MicP Switch", "LIP" },
  417. };
  418. static int eqmode_get(struct snd_kcontrol *kcontrol,
  419. struct snd_ctl_elem_value *ucontrol)
  420. {
  421. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  422. unsigned int reg;
  423. reg = snd_soc_component_read(component, WM8983_EQ1_LOW_SHELF);
  424. if (reg & WM8983_EQ3DMODE)
  425. ucontrol->value.enumerated.item[0] = 1;
  426. else
  427. ucontrol->value.enumerated.item[0] = 0;
  428. return 0;
  429. }
  430. static int eqmode_put(struct snd_kcontrol *kcontrol,
  431. struct snd_ctl_elem_value *ucontrol)
  432. {
  433. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  434. unsigned int regpwr2, regpwr3;
  435. unsigned int reg_eq;
  436. if (ucontrol->value.enumerated.item[0] != 0
  437. && ucontrol->value.enumerated.item[0] != 1)
  438. return -EINVAL;
  439. reg_eq = snd_soc_component_read(component, WM8983_EQ1_LOW_SHELF);
  440. switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
  441. case 0:
  442. if (!ucontrol->value.enumerated.item[0])
  443. return 0;
  444. break;
  445. case 1:
  446. if (ucontrol->value.enumerated.item[0])
  447. return 0;
  448. break;
  449. }
  450. regpwr2 = snd_soc_component_read(component, WM8983_POWER_MANAGEMENT_2);
  451. regpwr3 = snd_soc_component_read(component, WM8983_POWER_MANAGEMENT_3);
  452. /* disable the DACs and ADCs */
  453. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_2,
  454. WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
  455. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_3,
  456. WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
  457. /* set the desired eqmode */
  458. snd_soc_component_update_bits(component, WM8983_EQ1_LOW_SHELF,
  459. WM8983_EQ3DMODE_MASK,
  460. ucontrol->value.enumerated.item[0]
  461. << WM8983_EQ3DMODE_SHIFT);
  462. /* restore DAC/ADC configuration */
  463. snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_2, regpwr2);
  464. snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_3, regpwr3);
  465. return 0;
  466. }
  467. static bool wm8983_writeable(struct device *dev, unsigned int reg)
  468. {
  469. switch (reg) {
  470. case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL:
  471. case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2:
  472. case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4:
  473. case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3:
  474. case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL:
  475. case WM8983_BIAS_CTRL:
  476. return true;
  477. default:
  478. return false;
  479. }
  480. }
  481. static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
  482. {
  483. struct snd_soc_component *component = dai->component;
  484. return snd_soc_component_update_bits(component, WM8983_DAC_CONTROL,
  485. WM8983_SOFTMUTE_MASK,
  486. !!mute << WM8983_SOFTMUTE_SHIFT);
  487. }
  488. static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  489. {
  490. struct snd_soc_component *component = dai->component;
  491. u16 format, master, bcp, lrp;
  492. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  493. case SND_SOC_DAIFMT_I2S:
  494. format = 0x2;
  495. break;
  496. case SND_SOC_DAIFMT_RIGHT_J:
  497. format = 0x0;
  498. break;
  499. case SND_SOC_DAIFMT_LEFT_J:
  500. format = 0x1;
  501. break;
  502. case SND_SOC_DAIFMT_DSP_A:
  503. case SND_SOC_DAIFMT_DSP_B:
  504. format = 0x3;
  505. break;
  506. default:
  507. dev_err(dai->dev, "Unknown dai format\n");
  508. return -EINVAL;
  509. }
  510. snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
  511. WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
  512. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  513. case SND_SOC_DAIFMT_CBM_CFM:
  514. master = 1;
  515. break;
  516. case SND_SOC_DAIFMT_CBS_CFS:
  517. master = 0;
  518. break;
  519. default:
  520. dev_err(dai->dev, "Unknown master/slave configuration\n");
  521. return -EINVAL;
  522. }
  523. snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
  524. WM8983_MS_MASK, master << WM8983_MS_SHIFT);
  525. /* FIXME: We don't currently support DSP A/B modes */
  526. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  527. case SND_SOC_DAIFMT_DSP_A:
  528. case SND_SOC_DAIFMT_DSP_B:
  529. dev_err(dai->dev, "DSP A/B modes are not supported\n");
  530. return -EINVAL;
  531. default:
  532. break;
  533. }
  534. bcp = lrp = 0;
  535. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  536. case SND_SOC_DAIFMT_NB_NF:
  537. break;
  538. case SND_SOC_DAIFMT_IB_IF:
  539. bcp = lrp = 1;
  540. break;
  541. case SND_SOC_DAIFMT_IB_NF:
  542. bcp = 1;
  543. break;
  544. case SND_SOC_DAIFMT_NB_IF:
  545. lrp = 1;
  546. break;
  547. default:
  548. dev_err(dai->dev, "Unknown polarity configuration\n");
  549. return -EINVAL;
  550. }
  551. snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
  552. WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
  553. snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
  554. WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
  555. return 0;
  556. }
  557. static int wm8983_hw_params(struct snd_pcm_substream *substream,
  558. struct snd_pcm_hw_params *params,
  559. struct snd_soc_dai *dai)
  560. {
  561. int i;
  562. struct snd_soc_component *component = dai->component;
  563. struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
  564. u16 blen, srate_idx;
  565. u32 tmp;
  566. int srate_best;
  567. int ret;
  568. ret = snd_soc_params_to_bclk(params);
  569. if (ret < 0) {
  570. dev_err(component->dev, "Failed to convert params to bclk: %d\n", ret);
  571. return ret;
  572. }
  573. wm8983->bclk = ret;
  574. switch (params_width(params)) {
  575. case 16:
  576. blen = 0x0;
  577. break;
  578. case 20:
  579. blen = 0x1;
  580. break;
  581. case 24:
  582. blen = 0x2;
  583. break;
  584. case 32:
  585. blen = 0x3;
  586. break;
  587. default:
  588. dev_err(dai->dev, "Unsupported word length %u\n",
  589. params_width(params));
  590. return -EINVAL;
  591. }
  592. snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
  593. WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
  594. /*
  595. * match to the nearest possible sample rate and rely
  596. * on the array index to configure the SR register
  597. */
  598. srate_idx = 0;
  599. srate_best = abs(srates[0] - params_rate(params));
  600. for (i = 1; i < ARRAY_SIZE(srates); ++i) {
  601. if (abs(srates[i] - params_rate(params)) >= srate_best)
  602. continue;
  603. srate_idx = i;
  604. srate_best = abs(srates[i] - params_rate(params));
  605. }
  606. dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
  607. snd_soc_component_update_bits(component, WM8983_ADDITIONAL_CONTROL,
  608. WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
  609. dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
  610. dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
  611. for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
  612. if (wm8983->sysclk / params_rate(params)
  613. == fs_ratios[i].ratio)
  614. break;
  615. }
  616. if (i == ARRAY_SIZE(fs_ratios)) {
  617. dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
  618. wm8983->sysclk, params_rate(params));
  619. return -EINVAL;
  620. }
  621. dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
  622. snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
  623. WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
  624. /* select the appropriate bclk divider */
  625. tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
  626. for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
  627. if (wm8983->bclk == tmp / bclk_divs[i])
  628. break;
  629. }
  630. if (i == ARRAY_SIZE(bclk_divs)) {
  631. dev_err(dai->dev, "No matching BCLK divider found\n");
  632. return -EINVAL;
  633. }
  634. dev_dbg(dai->dev, "BCLK div = %d\n", i);
  635. snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
  636. WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
  637. return 0;
  638. }
  639. struct pll_div {
  640. u32 div2:1;
  641. u32 n:4;
  642. u32 k:24;
  643. };
  644. #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
  645. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  646. unsigned int source)
  647. {
  648. u64 Kpart;
  649. unsigned long int K, Ndiv, Nmod;
  650. pll_div->div2 = 0;
  651. Ndiv = target / source;
  652. if (Ndiv < 6) {
  653. source >>= 1;
  654. pll_div->div2 = 1;
  655. Ndiv = target / source;
  656. }
  657. if (Ndiv < 6 || Ndiv > 12) {
  658. printk(KERN_ERR "%s: WM8983 N value is not within"
  659. " the recommended range: %lu\n", __func__, Ndiv);
  660. return -EINVAL;
  661. }
  662. pll_div->n = Ndiv;
  663. Nmod = target % source;
  664. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  665. do_div(Kpart, source);
  666. K = Kpart & 0xffffffff;
  667. if ((K % 10) >= 5)
  668. K += 5;
  669. K /= 10;
  670. pll_div->k = K;
  671. return 0;
  672. }
  673. static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
  674. int source, unsigned int freq_in,
  675. unsigned int freq_out)
  676. {
  677. int ret;
  678. struct snd_soc_component *component;
  679. struct pll_div pll_div;
  680. component = dai->component;
  681. if (!freq_in || !freq_out) {
  682. /* disable the PLL */
  683. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  684. WM8983_PLLEN_MASK, 0);
  685. return 0;
  686. } else {
  687. ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
  688. if (ret)
  689. return ret;
  690. /* disable the PLL before re-programming it */
  691. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  692. WM8983_PLLEN_MASK, 0);
  693. /* set PLLN and PRESCALE */
  694. snd_soc_component_write(component, WM8983_PLL_N,
  695. (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
  696. | pll_div.n);
  697. /* set PLLK */
  698. snd_soc_component_write(component, WM8983_PLL_K_3, pll_div.k & 0x1ff);
  699. snd_soc_component_write(component, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
  700. snd_soc_component_write(component, WM8983_PLL_K_1, (pll_div.k >> 18));
  701. /* enable the PLL */
  702. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  703. WM8983_PLLEN_MASK, WM8983_PLLEN);
  704. }
  705. return 0;
  706. }
  707. static int wm8983_set_sysclk(struct snd_soc_dai *dai,
  708. int clk_id, unsigned int freq, int dir)
  709. {
  710. struct snd_soc_component *component = dai->component;
  711. struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
  712. switch (clk_id) {
  713. case WM8983_CLKSRC_MCLK:
  714. snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
  715. WM8983_CLKSEL_MASK, 0);
  716. break;
  717. case WM8983_CLKSRC_PLL:
  718. snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
  719. WM8983_CLKSEL_MASK, WM8983_CLKSEL);
  720. break;
  721. default:
  722. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  723. return -EINVAL;
  724. }
  725. wm8983->sysclk = freq;
  726. return 0;
  727. }
  728. static int wm8983_set_bias_level(struct snd_soc_component *component,
  729. enum snd_soc_bias_level level)
  730. {
  731. struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
  732. int ret;
  733. switch (level) {
  734. case SND_SOC_BIAS_ON:
  735. case SND_SOC_BIAS_PREPARE:
  736. /* VMID at 100k */
  737. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  738. WM8983_VMIDSEL_MASK,
  739. 1 << WM8983_VMIDSEL_SHIFT);
  740. break;
  741. case SND_SOC_BIAS_STANDBY:
  742. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  743. ret = regcache_sync(wm8983->regmap);
  744. if (ret < 0) {
  745. dev_err(component->dev, "Failed to sync cache: %d\n", ret);
  746. return ret;
  747. }
  748. /* enable anti-pop features */
  749. snd_soc_component_update_bits(component, WM8983_OUT4_TO_ADC,
  750. WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
  751. WM8983_POBCTRL | WM8983_DELEN);
  752. /* enable thermal shutdown */
  753. snd_soc_component_update_bits(component, WM8983_OUTPUT_CTRL,
  754. WM8983_TSDEN_MASK, WM8983_TSDEN);
  755. /* enable BIASEN */
  756. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  757. WM8983_BIASEN_MASK, WM8983_BIASEN);
  758. /* VMID at 100k */
  759. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  760. WM8983_VMIDSEL_MASK,
  761. 1 << WM8983_VMIDSEL_SHIFT);
  762. msleep(250);
  763. /* disable anti-pop features */
  764. snd_soc_component_update_bits(component, WM8983_OUT4_TO_ADC,
  765. WM8983_POBCTRL_MASK |
  766. WM8983_DELEN_MASK, 0);
  767. }
  768. /* VMID at 500k */
  769. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  770. WM8983_VMIDSEL_MASK,
  771. 2 << WM8983_VMIDSEL_SHIFT);
  772. break;
  773. case SND_SOC_BIAS_OFF:
  774. /* disable thermal shutdown */
  775. snd_soc_component_update_bits(component, WM8983_OUTPUT_CTRL,
  776. WM8983_TSDEN_MASK, 0);
  777. /* disable VMIDSEL and BIASEN */
  778. snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
  779. WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
  780. 0);
  781. /* wait for VMID to discharge */
  782. msleep(100);
  783. snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_1, 0);
  784. snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_2, 0);
  785. snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_3, 0);
  786. break;
  787. }
  788. return 0;
  789. }
  790. static int wm8983_probe(struct snd_soc_component *component)
  791. {
  792. int ret;
  793. int i;
  794. ret = snd_soc_component_write(component, WM8983_SOFTWARE_RESET, 0);
  795. if (ret < 0) {
  796. dev_err(component->dev, "Failed to issue reset: %d\n", ret);
  797. return ret;
  798. }
  799. /* set the vol/gain update bits */
  800. for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
  801. snd_soc_component_update_bits(component, vol_update_regs[i],
  802. 0x100, 0x100);
  803. /* mute all outputs and set PGAs to minimum gain */
  804. for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
  805. i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
  806. snd_soc_component_update_bits(component, i, 0x40, 0x40);
  807. /* enable soft mute */
  808. snd_soc_component_update_bits(component, WM8983_DAC_CONTROL,
  809. WM8983_SOFTMUTE_MASK,
  810. WM8983_SOFTMUTE);
  811. /* enable BIASCUT */
  812. snd_soc_component_update_bits(component, WM8983_BIAS_CTRL,
  813. WM8983_BIASCUT, WM8983_BIASCUT);
  814. return 0;
  815. }
  816. static const struct snd_soc_dai_ops wm8983_dai_ops = {
  817. .mute_stream = wm8983_dac_mute,
  818. .hw_params = wm8983_hw_params,
  819. .set_fmt = wm8983_set_fmt,
  820. .set_sysclk = wm8983_set_sysclk,
  821. .set_pll = wm8983_set_pll,
  822. .no_capture_mute = 1,
  823. };
  824. #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  825. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  826. static struct snd_soc_dai_driver wm8983_dai = {
  827. .name = "wm8983-hifi",
  828. .playback = {
  829. .stream_name = "Playback",
  830. .channels_min = 2,
  831. .channels_max = 2,
  832. .rates = SNDRV_PCM_RATE_8000_48000,
  833. .formats = WM8983_FORMATS,
  834. },
  835. .capture = {
  836. .stream_name = "Capture",
  837. .channels_min = 2,
  838. .channels_max = 2,
  839. .rates = SNDRV_PCM_RATE_8000_48000,
  840. .formats = WM8983_FORMATS,
  841. },
  842. .ops = &wm8983_dai_ops,
  843. .symmetric_rates = 1
  844. };
  845. static const struct snd_soc_component_driver soc_component_dev_wm8983 = {
  846. .probe = wm8983_probe,
  847. .set_bias_level = wm8983_set_bias_level,
  848. .controls = wm8983_snd_controls,
  849. .num_controls = ARRAY_SIZE(wm8983_snd_controls),
  850. .dapm_widgets = wm8983_dapm_widgets,
  851. .num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets),
  852. .dapm_routes = wm8983_audio_map,
  853. .num_dapm_routes = ARRAY_SIZE(wm8983_audio_map),
  854. .suspend_bias_off = 1,
  855. .idle_bias_on = 1,
  856. .use_pmdown_time = 1,
  857. .endianness = 1,
  858. .non_legacy_dai_naming = 1,
  859. };
  860. static const struct regmap_config wm8983_regmap = {
  861. .reg_bits = 7,
  862. .val_bits = 9,
  863. .reg_defaults = wm8983_defaults,
  864. .num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
  865. .cache_type = REGCACHE_RBTREE,
  866. .max_register = WM8983_MAX_REGISTER,
  867. .writeable_reg = wm8983_writeable,
  868. };
  869. #if defined(CONFIG_SPI_MASTER)
  870. static int wm8983_spi_probe(struct spi_device *spi)
  871. {
  872. struct wm8983_priv *wm8983;
  873. int ret;
  874. wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL);
  875. if (!wm8983)
  876. return -ENOMEM;
  877. wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap);
  878. if (IS_ERR(wm8983->regmap)) {
  879. ret = PTR_ERR(wm8983->regmap);
  880. dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
  881. return ret;
  882. }
  883. spi_set_drvdata(spi, wm8983);
  884. ret = devm_snd_soc_register_component(&spi->dev,
  885. &soc_component_dev_wm8983, &wm8983_dai, 1);
  886. return ret;
  887. }
  888. static struct spi_driver wm8983_spi_driver = {
  889. .driver = {
  890. .name = "wm8983",
  891. },
  892. .probe = wm8983_spi_probe,
  893. };
  894. #endif
  895. #if IS_ENABLED(CONFIG_I2C)
  896. static int wm8983_i2c_probe(struct i2c_client *i2c,
  897. const struct i2c_device_id *id)
  898. {
  899. struct wm8983_priv *wm8983;
  900. int ret;
  901. wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL);
  902. if (!wm8983)
  903. return -ENOMEM;
  904. wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap);
  905. if (IS_ERR(wm8983->regmap)) {
  906. ret = PTR_ERR(wm8983->regmap);
  907. dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
  908. return ret;
  909. }
  910. i2c_set_clientdata(i2c, wm8983);
  911. ret = devm_snd_soc_register_component(&i2c->dev,
  912. &soc_component_dev_wm8983, &wm8983_dai, 1);
  913. return ret;
  914. }
  915. static const struct i2c_device_id wm8983_i2c_id[] = {
  916. { "wm8983", 0 },
  917. { }
  918. };
  919. MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
  920. static struct i2c_driver wm8983_i2c_driver = {
  921. .driver = {
  922. .name = "wm8983",
  923. },
  924. .probe = wm8983_i2c_probe,
  925. .id_table = wm8983_i2c_id
  926. };
  927. #endif
  928. static int __init wm8983_modinit(void)
  929. {
  930. int ret = 0;
  931. #if IS_ENABLED(CONFIG_I2C)
  932. ret = i2c_add_driver(&wm8983_i2c_driver);
  933. if (ret) {
  934. printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
  935. ret);
  936. }
  937. #endif
  938. #if defined(CONFIG_SPI_MASTER)
  939. ret = spi_register_driver(&wm8983_spi_driver);
  940. if (ret != 0) {
  941. printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
  942. ret);
  943. }
  944. #endif
  945. return ret;
  946. }
  947. module_init(wm8983_modinit);
  948. static void __exit wm8983_exit(void)
  949. {
  950. #if IS_ENABLED(CONFIG_I2C)
  951. i2c_del_driver(&wm8983_i2c_driver);
  952. #endif
  953. #if defined(CONFIG_SPI_MASTER)
  954. spi_unregister_driver(&wm8983_spi_driver);
  955. #endif
  956. }
  957. module_exit(wm8983_exit);
  958. MODULE_DESCRIPTION("ASoC WM8983 driver");
  959. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  960. MODULE_LICENSE("GPL");