wm8978.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
  4. *
  5. * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  6. * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
  7. * Copyright 2006-2009 Wolfson Microelectronics PLC.
  8. * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/regmap.h>
  18. #include <linux/slab.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <asm/div64.h>
  26. #include "wm8978.h"
  27. static const struct reg_default wm8978_reg_defaults[] = {
  28. { 1, 0x0000 },
  29. { 2, 0x0000 },
  30. { 3, 0x0000 },
  31. { 4, 0x0050 },
  32. { 5, 0x0000 },
  33. { 6, 0x0140 },
  34. { 7, 0x0000 },
  35. { 8, 0x0000 },
  36. { 9, 0x0000 },
  37. { 10, 0x0000 },
  38. { 11, 0x00ff },
  39. { 12, 0x00ff },
  40. { 13, 0x0000 },
  41. { 14, 0x0100 },
  42. { 15, 0x00ff },
  43. { 16, 0x00ff },
  44. { 17, 0x0000 },
  45. { 18, 0x012c },
  46. { 19, 0x002c },
  47. { 20, 0x002c },
  48. { 21, 0x002c },
  49. { 22, 0x002c },
  50. { 23, 0x0000 },
  51. { 24, 0x0032 },
  52. { 25, 0x0000 },
  53. { 26, 0x0000 },
  54. { 27, 0x0000 },
  55. { 28, 0x0000 },
  56. { 29, 0x0000 },
  57. { 30, 0x0000 },
  58. { 31, 0x0000 },
  59. { 32, 0x0038 },
  60. { 33, 0x000b },
  61. { 34, 0x0032 },
  62. { 35, 0x0000 },
  63. { 36, 0x0008 },
  64. { 37, 0x000c },
  65. { 38, 0x0093 },
  66. { 39, 0x00e9 },
  67. { 40, 0x0000 },
  68. { 41, 0x0000 },
  69. { 42, 0x0000 },
  70. { 43, 0x0000 },
  71. { 44, 0x0033 },
  72. { 45, 0x0010 },
  73. { 46, 0x0010 },
  74. { 47, 0x0100 },
  75. { 48, 0x0100 },
  76. { 49, 0x0002 },
  77. { 50, 0x0001 },
  78. { 51, 0x0001 },
  79. { 52, 0x0039 },
  80. { 53, 0x0039 },
  81. { 54, 0x0039 },
  82. { 55, 0x0039 },
  83. { 56, 0x0001 },
  84. { 57, 0x0001 },
  85. };
  86. static bool wm8978_volatile(struct device *dev, unsigned int reg)
  87. {
  88. return reg == WM8978_RESET;
  89. }
  90. /* codec private data */
  91. struct wm8978_priv {
  92. struct regmap *regmap;
  93. unsigned int f_pllout;
  94. unsigned int f_mclk;
  95. unsigned int f_256fs;
  96. unsigned int f_opclk;
  97. int mclk_idx;
  98. enum wm8978_sysclk_src sysclk;
  99. };
  100. static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
  101. static const char *wm8978_eqmode[] = {"Capture", "Playback"};
  102. static const char *wm8978_bw[] = {"Narrow", "Wide"};
  103. static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
  104. static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
  105. static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
  106. static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
  107. static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
  108. static const char *wm8978_alc3[] = {"ALC", "Limiter"};
  109. static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
  110. static SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
  111. wm8978_companding);
  112. static SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
  113. wm8978_companding);
  114. static SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
  115. static SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
  116. static SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
  117. static SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
  118. static SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
  119. static SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
  120. static SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
  121. static SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
  122. static SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
  123. static SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
  124. static SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
  125. static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
  126. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  127. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
  128. static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
  129. static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
  130. static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
  131. static const struct snd_kcontrol_new wm8978_snd_controls[] = {
  132. SOC_SINGLE("Digital Loopback Switch",
  133. WM8978_COMPANDING_CONTROL, 0, 1, 0),
  134. SOC_ENUM("ADC Companding", adc_compand),
  135. SOC_ENUM("DAC Companding", dac_compand),
  136. SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
  137. SOC_DOUBLE_R_TLV("PCM Volume",
  138. WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
  139. 0, 255, 0, digital_tlv),
  140. SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
  141. SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
  142. SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
  143. SOC_DOUBLE_R_TLV("ADC Volume",
  144. WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
  145. 0, 255, 0, digital_tlv),
  146. SOC_ENUM("Equaliser Function", eqmode),
  147. SOC_ENUM("EQ1 Cut Off", eq1),
  148. SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
  149. SOC_ENUM("Equaliser EQ2 Bandwidth", eq2bw),
  150. SOC_ENUM("EQ2 Cut Off", eq2),
  151. SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
  152. SOC_ENUM("Equaliser EQ3 Bandwidth", eq3bw),
  153. SOC_ENUM("EQ3 Cut Off", eq3),
  154. SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
  155. SOC_ENUM("Equaliser EQ4 Bandwidth", eq4bw),
  156. SOC_ENUM("EQ4 Cut Off", eq4),
  157. SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
  158. SOC_ENUM("EQ5 Cut Off", eq5),
  159. SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
  160. SOC_SINGLE("DAC Playback Limiter Switch",
  161. WM8978_DAC_LIMITER_1, 8, 1, 0),
  162. SOC_SINGLE("DAC Playback Limiter Decay",
  163. WM8978_DAC_LIMITER_1, 4, 15, 0),
  164. SOC_SINGLE("DAC Playback Limiter Attack",
  165. WM8978_DAC_LIMITER_1, 0, 15, 0),
  166. SOC_SINGLE("DAC Playback Limiter Threshold",
  167. WM8978_DAC_LIMITER_2, 4, 7, 0),
  168. SOC_SINGLE_TLV("DAC Playback Limiter Volume",
  169. WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
  170. SOC_ENUM("ALC Enable Switch", alc1),
  171. SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
  172. SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
  173. SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
  174. SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
  175. SOC_ENUM("ALC Capture Mode", alc3),
  176. SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
  177. SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
  178. SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
  179. SOC_SINGLE("ALC Capture Noise Gate Threshold",
  180. WM8978_NOISE_GATE, 0, 7, 0),
  181. SOC_DOUBLE_R("Capture PGA ZC Switch",
  182. WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
  183. 7, 1, 0),
  184. /* OUT1 - Headphones */
  185. SOC_DOUBLE_R("Headphone Playback ZC Switch",
  186. WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
  187. SOC_DOUBLE_R_TLV("Headphone Playback Volume",
  188. WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
  189. 0, 63, 0, spk_tlv),
  190. /* OUT2 - Speakers */
  191. SOC_DOUBLE_R("Speaker Playback ZC Switch",
  192. WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
  193. SOC_DOUBLE_R_TLV("Speaker Playback Volume",
  194. WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
  195. 0, 63, 0, spk_tlv),
  196. /* OUT3/4 - Line Output */
  197. SOC_DOUBLE_R("Line Playback Switch",
  198. WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
  199. /* Mixer #3: Boost (Input) mixer */
  200. SOC_DOUBLE_R("PGA Boost (+20dB)",
  201. WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
  202. 8, 1, 0),
  203. SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
  204. WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
  205. 4, 7, 0, boost_tlv),
  206. SOC_DOUBLE_R_TLV("Aux Boost Volume",
  207. WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
  208. 0, 7, 0, boost_tlv),
  209. /* Input PGA volume */
  210. SOC_DOUBLE_R_TLV("Input PGA Volume",
  211. WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
  212. 0, 63, 0, inpga_tlv),
  213. /* Headphone */
  214. SOC_DOUBLE_R("Headphone Switch",
  215. WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
  216. /* Speaker */
  217. SOC_DOUBLE_R("Speaker Switch",
  218. WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
  219. /* DAC / ADC oversampling */
  220. SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
  221. 5, 1, 0),
  222. SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
  223. 5, 1, 0),
  224. };
  225. /* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
  226. static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
  227. SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
  228. SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
  229. SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
  230. };
  231. static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
  232. SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
  233. SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
  234. SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
  235. };
  236. /* OUT3/OUT4 Mixer not implemented */
  237. /* Mixer #2: Input PGA Mute */
  238. static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
  239. SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
  240. SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
  241. SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
  242. };
  243. static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
  244. SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
  245. SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
  246. SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
  247. };
  248. static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
  249. SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
  250. WM8978_POWER_MANAGEMENT_3, 0, 0),
  251. SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
  252. WM8978_POWER_MANAGEMENT_3, 1, 0),
  253. SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
  254. WM8978_POWER_MANAGEMENT_2, 0, 0),
  255. SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
  256. WM8978_POWER_MANAGEMENT_2, 1, 0),
  257. /* Mixer #1: OUT1,2 */
  258. SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
  259. 2, 0, wm8978_left_out_mixer),
  260. SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
  261. 3, 0, wm8978_right_out_mixer),
  262. SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
  263. 2, 0, wm8978_left_input_mixer),
  264. SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
  265. 3, 0, wm8978_right_input_mixer),
  266. SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
  267. 4, 0, NULL, 0),
  268. SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
  269. 5, 0, NULL, 0),
  270. SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
  271. 6, 1, NULL, 0),
  272. SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
  273. 6, 1, NULL, 0),
  274. SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
  275. 7, 0, NULL, 0),
  276. SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
  277. 8, 0, NULL, 0),
  278. SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
  279. 6, 0, NULL, 0),
  280. SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
  281. 5, 0, NULL, 0),
  282. SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
  283. 8, 0, NULL, 0),
  284. SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
  285. SND_SOC_DAPM_INPUT("LMICN"),
  286. SND_SOC_DAPM_INPUT("LMICP"),
  287. SND_SOC_DAPM_INPUT("RMICN"),
  288. SND_SOC_DAPM_INPUT("RMICP"),
  289. SND_SOC_DAPM_INPUT("LAUX"),
  290. SND_SOC_DAPM_INPUT("RAUX"),
  291. SND_SOC_DAPM_INPUT("L2"),
  292. SND_SOC_DAPM_INPUT("R2"),
  293. SND_SOC_DAPM_OUTPUT("LHP"),
  294. SND_SOC_DAPM_OUTPUT("RHP"),
  295. SND_SOC_DAPM_OUTPUT("LSPK"),
  296. SND_SOC_DAPM_OUTPUT("RSPK"),
  297. };
  298. static const struct snd_soc_dapm_route wm8978_dapm_routes[] = {
  299. /* Output mixer */
  300. {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
  301. {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
  302. {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
  303. {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
  304. {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
  305. {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
  306. /* Outputs */
  307. {"Right Headphone Out", NULL, "Right Output Mixer"},
  308. {"RHP", NULL, "Right Headphone Out"},
  309. {"Left Headphone Out", NULL, "Left Output Mixer"},
  310. {"LHP", NULL, "Left Headphone Out"},
  311. {"Right Speaker Out", NULL, "Right Output Mixer"},
  312. {"RSPK", NULL, "Right Speaker Out"},
  313. {"Left Speaker Out", NULL, "Left Output Mixer"},
  314. {"LSPK", NULL, "Left Speaker Out"},
  315. /* Boost Mixer */
  316. {"Right ADC", NULL, "Right Boost Mixer"},
  317. {"Right Boost Mixer", NULL, "RAUX"},
  318. {"Right Boost Mixer", NULL, "Right Capture PGA"},
  319. {"Right Boost Mixer", NULL, "R2"},
  320. {"Left ADC", NULL, "Left Boost Mixer"},
  321. {"Left Boost Mixer", NULL, "LAUX"},
  322. {"Left Boost Mixer", NULL, "Left Capture PGA"},
  323. {"Left Boost Mixer", NULL, "L2"},
  324. /* Input PGA */
  325. {"Right Capture PGA", NULL, "Right Input Mixer"},
  326. {"Left Capture PGA", NULL, "Left Input Mixer"},
  327. {"Right Input Mixer", "R2 Switch", "R2"},
  328. {"Right Input Mixer", "MicN Switch", "RMICN"},
  329. {"Right Input Mixer", "MicP Switch", "RMICP"},
  330. {"Left Input Mixer", "L2 Switch", "L2"},
  331. {"Left Input Mixer", "MicN Switch", "LMICN"},
  332. {"Left Input Mixer", "MicP Switch", "LMICP"},
  333. };
  334. /* PLL divisors */
  335. struct wm8978_pll_div {
  336. u32 k;
  337. u8 n;
  338. u8 div2;
  339. };
  340. #define FIXED_PLL_SIZE (1 << 24)
  341. static void pll_factors(struct snd_soc_component *component,
  342. struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
  343. {
  344. u64 k_part;
  345. unsigned int k, n_div, n_mod;
  346. n_div = target / source;
  347. if (n_div < 6) {
  348. source >>= 1;
  349. pll_div->div2 = 1;
  350. n_div = target / source;
  351. } else {
  352. pll_div->div2 = 0;
  353. }
  354. if (n_div < 6 || n_div > 12)
  355. dev_warn(component->dev,
  356. "WM8978 N value exceeds recommended range! N = %u\n",
  357. n_div);
  358. pll_div->n = n_div;
  359. n_mod = target - source * n_div;
  360. k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
  361. do_div(k_part, source);
  362. k = k_part & 0xFFFFFFFF;
  363. pll_div->k = k;
  364. }
  365. /* MCLK dividers */
  366. static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
  367. static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
  368. /*
  369. * find index >= idx, such that, for a given f_out,
  370. * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
  371. * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
  372. * generalised for f_opclk with suitable coefficient arrays, but currently
  373. * the OPCLK divisor is calculated directly, not iteratively.
  374. */
  375. static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
  376. unsigned int *f_pllout)
  377. {
  378. int i;
  379. for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
  380. unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
  381. mclk_denominator[i];
  382. if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
  383. *f_pllout = f_pllout_x4 / 4;
  384. return i;
  385. }
  386. }
  387. return -EINVAL;
  388. }
  389. /*
  390. * Calculate internal frequencies and dividers, according to Figure 40
  391. * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
  392. */
  393. static int wm8978_configure_pll(struct snd_soc_component *component)
  394. {
  395. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  396. struct wm8978_pll_div pll_div;
  397. unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
  398. f_256fs = wm8978->f_256fs;
  399. unsigned int f2;
  400. if (!f_mclk)
  401. return -EINVAL;
  402. if (f_opclk) {
  403. unsigned int opclk_div;
  404. /* Cannot set up MCLK divider now, do later */
  405. wm8978->mclk_idx = -1;
  406. /*
  407. * The user needs OPCLK. Choose OPCLKDIV to put
  408. * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
  409. * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
  410. * prescale = 1, or prescale = 2. Prescale is calculated inside
  411. * pll_factors(). We have to select f_PLLOUT, such that
  412. * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
  413. * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
  414. */
  415. if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
  416. return -EINVAL;
  417. if (4 * f_opclk < 3 * f_mclk)
  418. /* Have to use OPCLKDIV */
  419. opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
  420. else
  421. opclk_div = 1;
  422. dev_dbg(component->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
  423. snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 0x30,
  424. (opclk_div - 1) << 4);
  425. wm8978->f_pllout = f_opclk * opclk_div;
  426. } else if (f_256fs) {
  427. /*
  428. * Not using OPCLK, but PLL is used for the codec, choose R:
  429. * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
  430. * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
  431. * prescale = 1, or prescale = 2. Prescale is calculated inside
  432. * pll_factors(). We have to select f_PLLOUT, such that
  433. * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
  434. * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
  435. * must be 3.781MHz <= f_MCLK <= 32.768MHz
  436. */
  437. int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
  438. if (idx < 0)
  439. return idx;
  440. wm8978->mclk_idx = idx;
  441. } else {
  442. return -EINVAL;
  443. }
  444. f2 = wm8978->f_pllout * 4;
  445. dev_dbg(component->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
  446. wm8978->f_mclk, wm8978->f_pllout);
  447. pll_factors(component, &pll_div, f2, wm8978->f_mclk);
  448. dev_dbg(component->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
  449. __func__, pll_div.n, pll_div.k, pll_div.div2);
  450. /* Turn PLL off for configuration... */
  451. snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
  452. snd_soc_component_write(component, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
  453. snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18);
  454. snd_soc_component_write(component, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
  455. snd_soc_component_write(component, WM8978_PLL_K3, pll_div.k & 0x1ff);
  456. /* ...and on again */
  457. snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
  458. if (f_opclk)
  459. /* Output PLL (OPCLK) to GPIO1 */
  460. snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 7, 4);
  461. return 0;
  462. }
  463. /*
  464. * Configure WM8978 clock dividers.
  465. */
  466. static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  467. int div_id, int div)
  468. {
  469. struct snd_soc_component *component = codec_dai->component;
  470. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  471. int ret = 0;
  472. switch (div_id) {
  473. case WM8978_OPCLKRATE:
  474. wm8978->f_opclk = div;
  475. if (wm8978->f_mclk)
  476. /*
  477. * We know the MCLK frequency, the user has requested
  478. * OPCLK, configure the PLL based on that and start it
  479. * and OPCLK immediately. We will configure PLL to match
  480. * user-requested OPCLK frquency as good as possible.
  481. * In fact, it is likely, that matching the sampling
  482. * rate, when it becomes known, is more important, and
  483. * we will not be reconfiguring PLL then, because we
  484. * must not interrupt OPCLK. But it should be fine,
  485. * because typically the user will request OPCLK to run
  486. * at 256fs or 512fs, and for these cases we will also
  487. * find an exact MCLK divider configuration - it will
  488. * be equal to or double the OPCLK divisor.
  489. */
  490. ret = wm8978_configure_pll(component);
  491. break;
  492. case WM8978_BCLKDIV:
  493. if (div & ~0x1c)
  494. return -EINVAL;
  495. snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, div);
  496. break;
  497. default:
  498. return -EINVAL;
  499. }
  500. dev_dbg(component->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
  501. return ret;
  502. }
  503. /*
  504. * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
  505. */
  506. static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  507. unsigned int freq, int dir)
  508. {
  509. struct snd_soc_component *component = codec_dai->component;
  510. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  511. int ret = 0;
  512. dev_dbg(component->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
  513. if (freq) {
  514. wm8978->f_mclk = freq;
  515. /* Even if MCLK is used for system clock, might have to drive OPCLK */
  516. if (wm8978->f_opclk)
  517. ret = wm8978_configure_pll(component);
  518. /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
  519. if (!ret)
  520. wm8978->sysclk = clk_id;
  521. }
  522. if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
  523. /* Clock CODEC directly from MCLK */
  524. snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0);
  525. /* GPIO1 into default mode as input - before configuring PLL */
  526. snd_soc_component_update_bits(component, WM8978_GPIO_CONTROL, 7, 0);
  527. /* Turn off PLL */
  528. snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
  529. wm8978->sysclk = WM8978_MCLK;
  530. wm8978->f_pllout = 0;
  531. wm8978->f_opclk = 0;
  532. }
  533. return ret;
  534. }
  535. /*
  536. * Set ADC and Voice DAC format.
  537. */
  538. static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  539. {
  540. struct snd_soc_component *component = codec_dai->component;
  541. /*
  542. * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
  543. * Data Format mask = 0x18: all will be calculated anew
  544. */
  545. u16 iface = snd_soc_component_read(component, WM8978_AUDIO_INTERFACE) & ~0x198;
  546. u16 clk = snd_soc_component_read(component, WM8978_CLOCKING);
  547. dev_dbg(component->dev, "%s\n", __func__);
  548. /* set master/slave audio interface */
  549. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  550. case SND_SOC_DAIFMT_CBM_CFM:
  551. clk |= 1;
  552. break;
  553. case SND_SOC_DAIFMT_CBS_CFS:
  554. clk &= ~1;
  555. break;
  556. default:
  557. return -EINVAL;
  558. }
  559. /* interface format */
  560. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  561. case SND_SOC_DAIFMT_I2S:
  562. iface |= 0x10;
  563. break;
  564. case SND_SOC_DAIFMT_RIGHT_J:
  565. break;
  566. case SND_SOC_DAIFMT_LEFT_J:
  567. iface |= 0x8;
  568. break;
  569. case SND_SOC_DAIFMT_DSP_A:
  570. iface |= 0x18;
  571. break;
  572. default:
  573. return -EINVAL;
  574. }
  575. /* clock inversion */
  576. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  577. case SND_SOC_DAIFMT_NB_NF:
  578. break;
  579. case SND_SOC_DAIFMT_IB_IF:
  580. iface |= 0x180;
  581. break;
  582. case SND_SOC_DAIFMT_IB_NF:
  583. iface |= 0x100;
  584. break;
  585. case SND_SOC_DAIFMT_NB_IF:
  586. iface |= 0x80;
  587. break;
  588. default:
  589. return -EINVAL;
  590. }
  591. snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface);
  592. snd_soc_component_write(component, WM8978_CLOCKING, clk);
  593. return 0;
  594. }
  595. /*
  596. * Set PCM DAI bit size and sample rate.
  597. */
  598. static int wm8978_hw_params(struct snd_pcm_substream *substream,
  599. struct snd_pcm_hw_params *params,
  600. struct snd_soc_dai *dai)
  601. {
  602. struct snd_soc_component *component = dai->component;
  603. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  604. /* Word length mask = 0x60 */
  605. u16 iface_ctl = snd_soc_component_read(component, WM8978_AUDIO_INTERFACE) & ~0x60;
  606. /* Sampling rate mask = 0xe (for filters) */
  607. u16 add_ctl = snd_soc_component_read(component, WM8978_ADDITIONAL_CONTROL) & ~0xe;
  608. u16 clking = snd_soc_component_read(component, WM8978_CLOCKING);
  609. enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
  610. WM8978_PLL : WM8978_MCLK;
  611. unsigned int f_sel, diff, diff_best = INT_MAX;
  612. int i, best = 0;
  613. if (!wm8978->f_mclk)
  614. return -EINVAL;
  615. /* bit size */
  616. switch (params_width(params)) {
  617. case 16:
  618. break;
  619. case 20:
  620. iface_ctl |= 0x20;
  621. break;
  622. case 24:
  623. iface_ctl |= 0x40;
  624. break;
  625. case 32:
  626. iface_ctl |= 0x60;
  627. break;
  628. }
  629. /* filter coefficient */
  630. switch (params_rate(params)) {
  631. case 8000:
  632. add_ctl |= 0x5 << 1;
  633. break;
  634. case 11025:
  635. add_ctl |= 0x4 << 1;
  636. break;
  637. case 16000:
  638. add_ctl |= 0x3 << 1;
  639. break;
  640. case 22050:
  641. add_ctl |= 0x2 << 1;
  642. break;
  643. case 32000:
  644. add_ctl |= 0x1 << 1;
  645. break;
  646. case 44100:
  647. case 48000:
  648. break;
  649. }
  650. /* Sampling rate is known now, can configure the MCLK divider */
  651. wm8978->f_256fs = params_rate(params) * 256;
  652. if (wm8978->sysclk == WM8978_MCLK) {
  653. wm8978->mclk_idx = -1;
  654. f_sel = wm8978->f_mclk;
  655. } else {
  656. if (!wm8978->f_opclk) {
  657. /* We only enter here, if OPCLK is not used */
  658. int ret = wm8978_configure_pll(component);
  659. if (ret < 0)
  660. return ret;
  661. }
  662. f_sel = wm8978->f_pllout;
  663. }
  664. if (wm8978->mclk_idx < 0) {
  665. /* Either MCLK is used directly, or OPCLK is used */
  666. if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
  667. return -EINVAL;
  668. for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
  669. diff = abs(wm8978->f_256fs * 3 -
  670. f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
  671. if (diff < diff_best) {
  672. diff_best = diff;
  673. best = i;
  674. }
  675. if (!diff)
  676. break;
  677. }
  678. } else {
  679. /* OPCLK not used, codec driven by PLL */
  680. best = wm8978->mclk_idx;
  681. diff = 0;
  682. }
  683. if (diff)
  684. dev_warn(component->dev, "Imprecise sampling rate: %uHz%s\n",
  685. f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
  686. wm8978->sysclk == WM8978_MCLK ?
  687. ", consider using PLL" : "");
  688. dev_dbg(component->dev, "%s: width %d, rate %u, MCLK divisor #%d\n", __func__,
  689. params_width(params), params_rate(params), best);
  690. /* MCLK divisor mask = 0xe0 */
  691. snd_soc_component_update_bits(component, WM8978_CLOCKING, 0xe0, best << 5);
  692. snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface_ctl);
  693. snd_soc_component_write(component, WM8978_ADDITIONAL_CONTROL, add_ctl);
  694. if (wm8978->sysclk != current_clk_id) {
  695. if (wm8978->sysclk == WM8978_PLL)
  696. /* Run CODEC from PLL instead of MCLK */
  697. snd_soc_component_update_bits(component, WM8978_CLOCKING,
  698. 0x100, 0x100);
  699. else
  700. /* Clock CODEC directly from MCLK */
  701. snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0);
  702. }
  703. return 0;
  704. }
  705. static int wm8978_mute(struct snd_soc_dai *dai, int mute, int direction)
  706. {
  707. struct snd_soc_component *component = dai->component;
  708. dev_dbg(component->dev, "%s: %d\n", __func__, mute);
  709. if (mute)
  710. snd_soc_component_update_bits(component, WM8978_DAC_CONTROL, 0x40, 0x40);
  711. else
  712. snd_soc_component_update_bits(component, WM8978_DAC_CONTROL, 0x40, 0);
  713. return 0;
  714. }
  715. static int wm8978_set_bias_level(struct snd_soc_component *component,
  716. enum snd_soc_bias_level level)
  717. {
  718. u16 power1 = snd_soc_component_read(component, WM8978_POWER_MANAGEMENT_1) & ~3;
  719. switch (level) {
  720. case SND_SOC_BIAS_ON:
  721. case SND_SOC_BIAS_PREPARE:
  722. power1 |= 1; /* VMID 75k */
  723. snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, power1);
  724. break;
  725. case SND_SOC_BIAS_STANDBY:
  726. /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
  727. power1 |= 0xc;
  728. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  729. /* Initial cap charge at VMID 5k */
  730. snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1,
  731. power1 | 0x3);
  732. mdelay(100);
  733. }
  734. power1 |= 0x2; /* VMID 500k */
  735. snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, power1);
  736. break;
  737. case SND_SOC_BIAS_OFF:
  738. /* Preserve PLL - OPCLK may be used by someone */
  739. snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
  740. snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_2, 0);
  741. snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_3, 0);
  742. break;
  743. }
  744. dev_dbg(component->dev, "%s: %d, %x\n", __func__, level, power1);
  745. return 0;
  746. }
  747. #define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  748. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  749. static const struct snd_soc_dai_ops wm8978_dai_ops = {
  750. .hw_params = wm8978_hw_params,
  751. .mute_stream = wm8978_mute,
  752. .set_fmt = wm8978_set_dai_fmt,
  753. .set_clkdiv = wm8978_set_dai_clkdiv,
  754. .set_sysclk = wm8978_set_dai_sysclk,
  755. .no_capture_mute = 1,
  756. };
  757. /* Also supports 12kHz */
  758. static struct snd_soc_dai_driver wm8978_dai = {
  759. .name = "wm8978-hifi",
  760. .playback = {
  761. .stream_name = "Playback",
  762. .channels_min = 1,
  763. .channels_max = 2,
  764. .rates = SNDRV_PCM_RATE_8000_48000,
  765. .formats = WM8978_FORMATS,
  766. },
  767. .capture = {
  768. .stream_name = "Capture",
  769. .channels_min = 1,
  770. .channels_max = 2,
  771. .rates = SNDRV_PCM_RATE_8000_48000,
  772. .formats = WM8978_FORMATS,
  773. },
  774. .ops = &wm8978_dai_ops,
  775. .symmetric_rates = 1,
  776. };
  777. static int wm8978_suspend(struct snd_soc_component *component)
  778. {
  779. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  780. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  781. /* Also switch PLL off */
  782. snd_soc_component_write(component, WM8978_POWER_MANAGEMENT_1, 0);
  783. regcache_mark_dirty(wm8978->regmap);
  784. return 0;
  785. }
  786. static int wm8978_resume(struct snd_soc_component *component)
  787. {
  788. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  789. /* Sync reg_cache with the hardware */
  790. regcache_sync(wm8978->regmap);
  791. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  792. if (wm8978->f_pllout)
  793. /* Switch PLL on */
  794. snd_soc_component_update_bits(component, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
  795. return 0;
  796. }
  797. /*
  798. * These registers contain an "update" bit - bit 8. This means, for example,
  799. * that one can write new DAC digital volume for both channels, but only when
  800. * the update bit is set, will also the volume be updated - simultaneously for
  801. * both channels.
  802. */
  803. static const int update_reg[] = {
  804. WM8978_LEFT_DAC_DIGITAL_VOLUME,
  805. WM8978_RIGHT_DAC_DIGITAL_VOLUME,
  806. WM8978_LEFT_ADC_DIGITAL_VOLUME,
  807. WM8978_RIGHT_ADC_DIGITAL_VOLUME,
  808. WM8978_LEFT_INP_PGA_CONTROL,
  809. WM8978_RIGHT_INP_PGA_CONTROL,
  810. WM8978_LOUT1_HP_CONTROL,
  811. WM8978_ROUT1_HP_CONTROL,
  812. WM8978_LOUT2_SPK_CONTROL,
  813. WM8978_ROUT2_SPK_CONTROL,
  814. };
  815. static int wm8978_probe(struct snd_soc_component *component)
  816. {
  817. struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
  818. int i;
  819. /*
  820. * Set default system clock to PLL, it is more precise, this is also the
  821. * default hardware setting
  822. */
  823. wm8978->sysclk = WM8978_PLL;
  824. /*
  825. * Set the update bit in all registers, that have one. This way all
  826. * writes to those registers will also cause the update bit to be
  827. * written.
  828. */
  829. for (i = 0; i < ARRAY_SIZE(update_reg); i++)
  830. snd_soc_component_update_bits(component, update_reg[i], 0x100, 0x100);
  831. return 0;
  832. }
  833. static const struct snd_soc_component_driver soc_component_dev_wm8978 = {
  834. .probe = wm8978_probe,
  835. .suspend = wm8978_suspend,
  836. .resume = wm8978_resume,
  837. .set_bias_level = wm8978_set_bias_level,
  838. .controls = wm8978_snd_controls,
  839. .num_controls = ARRAY_SIZE(wm8978_snd_controls),
  840. .dapm_widgets = wm8978_dapm_widgets,
  841. .num_dapm_widgets = ARRAY_SIZE(wm8978_dapm_widgets),
  842. .dapm_routes = wm8978_dapm_routes,
  843. .num_dapm_routes = ARRAY_SIZE(wm8978_dapm_routes),
  844. .idle_bias_on = 1,
  845. .use_pmdown_time = 1,
  846. .endianness = 1,
  847. .non_legacy_dai_naming = 1,
  848. };
  849. static const struct regmap_config wm8978_regmap_config = {
  850. .reg_bits = 7,
  851. .val_bits = 9,
  852. .max_register = WM8978_MAX_REGISTER,
  853. .volatile_reg = wm8978_volatile,
  854. .cache_type = REGCACHE_RBTREE,
  855. .reg_defaults = wm8978_reg_defaults,
  856. .num_reg_defaults = ARRAY_SIZE(wm8978_reg_defaults),
  857. };
  858. static int wm8978_i2c_probe(struct i2c_client *i2c,
  859. const struct i2c_device_id *id)
  860. {
  861. struct wm8978_priv *wm8978;
  862. int ret;
  863. wm8978 = devm_kzalloc(&i2c->dev, sizeof(struct wm8978_priv),
  864. GFP_KERNEL);
  865. if (wm8978 == NULL)
  866. return -ENOMEM;
  867. wm8978->regmap = devm_regmap_init_i2c(i2c, &wm8978_regmap_config);
  868. if (IS_ERR(wm8978->regmap)) {
  869. ret = PTR_ERR(wm8978->regmap);
  870. dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
  871. return ret;
  872. }
  873. i2c_set_clientdata(i2c, wm8978);
  874. /* Reset the codec */
  875. ret = regmap_write(wm8978->regmap, WM8978_RESET, 0);
  876. if (ret != 0) {
  877. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  878. return ret;
  879. }
  880. ret = devm_snd_soc_register_component(&i2c->dev,
  881. &soc_component_dev_wm8978, &wm8978_dai, 1);
  882. if (ret != 0) {
  883. dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
  884. return ret;
  885. }
  886. return 0;
  887. }
  888. static const struct i2c_device_id wm8978_i2c_id[] = {
  889. { "wm8978", 0 },
  890. { }
  891. };
  892. MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
  893. static const struct of_device_id wm8978_of_match[] = {
  894. { .compatible = "wlf,wm8978", },
  895. { }
  896. };
  897. MODULE_DEVICE_TABLE(of, wm8978_of_match);
  898. static struct i2c_driver wm8978_i2c_driver = {
  899. .driver = {
  900. .name = "wm8978",
  901. .of_match_table = wm8978_of_match,
  902. },
  903. .probe = wm8978_i2c_probe,
  904. .id_table = wm8978_i2c_id,
  905. };
  906. module_i2c_driver(wm8978_i2c_driver);
  907. MODULE_DESCRIPTION("ASoC WM8978 codec driver");
  908. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  909. MODULE_LICENSE("GPL");