wm8961.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8961.c -- WM8961 ALSA SoC Audio driver
  4. *
  5. * Copyright 2009-10 Wolfson Microelectronics, plc
  6. *
  7. * Author: Mark Brown
  8. *
  9. * Currently unimplemented features:
  10. * - ALC
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/initval.h>
  25. #include <sound/tlv.h>
  26. #include "wm8961.h"
  27. #define WM8961_MAX_REGISTER 0xFC
  28. static const struct reg_default wm8961_reg_defaults[] = {
  29. { 0, 0x009F }, /* R0 - Left Input volume */
  30. { 1, 0x009F }, /* R1 - Right Input volume */
  31. { 2, 0x0000 }, /* R2 - LOUT1 volume */
  32. { 3, 0x0000 }, /* R3 - ROUT1 volume */
  33. { 4, 0x0020 }, /* R4 - Clocking1 */
  34. { 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */
  35. { 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */
  36. { 7, 0x000A }, /* R7 - Audio Interface 0 */
  37. { 8, 0x01F4 }, /* R8 - Clocking2 */
  38. { 9, 0x0000 }, /* R9 - Audio Interface 1 */
  39. { 10, 0x00FF }, /* R10 - Left DAC volume */
  40. { 11, 0x00FF }, /* R11 - Right DAC volume */
  41. { 14, 0x0040 }, /* R14 - Audio Interface 2 */
  42. { 17, 0x007B }, /* R17 - ALC1 */
  43. { 18, 0x0000 }, /* R18 - ALC2 */
  44. { 19, 0x0032 }, /* R19 - ALC3 */
  45. { 20, 0x0000 }, /* R20 - Noise Gate */
  46. { 21, 0x00C0 }, /* R21 - Left ADC volume */
  47. { 22, 0x00C0 }, /* R22 - Right ADC volume */
  48. { 23, 0x0120 }, /* R23 - Additional control(1) */
  49. { 24, 0x0000 }, /* R24 - Additional control(2) */
  50. { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
  51. { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
  52. { 27, 0x0000 }, /* R27 - Additional Control (3) */
  53. { 28, 0x0000 }, /* R28 - Anti-pop */
  54. { 30, 0x005F }, /* R30 - Clocking 3 */
  55. { 32, 0x0000 }, /* R32 - ADCL signal path */
  56. { 33, 0x0000 }, /* R33 - ADCR signal path */
  57. { 40, 0x0000 }, /* R40 - LOUT2 volume */
  58. { 41, 0x0000 }, /* R41 - ROUT2 volume */
  59. { 47, 0x0000 }, /* R47 - Pwr Mgmt (3) */
  60. { 48, 0x0023 }, /* R48 - Additional Control (4) */
  61. { 49, 0x0000 }, /* R49 - Class D Control 1 */
  62. { 51, 0x0003 }, /* R51 - Class D Control 2 */
  63. { 56, 0x0106 }, /* R56 - Clocking 4 */
  64. { 57, 0x0000 }, /* R57 - DSP Sidetone 0 */
  65. { 58, 0x0000 }, /* R58 - DSP Sidetone 1 */
  66. { 60, 0x0000 }, /* R60 - DC Servo 0 */
  67. { 61, 0x0000 }, /* R61 - DC Servo 1 */
  68. { 63, 0x015E }, /* R63 - DC Servo 3 */
  69. { 65, 0x0010 }, /* R65 - DC Servo 5 */
  70. { 68, 0x0003 }, /* R68 - Analogue PGA Bias */
  71. { 69, 0x0000 }, /* R69 - Analogue HP 0 */
  72. { 71, 0x01FB }, /* R71 - Analogue HP 2 */
  73. { 72, 0x0000 }, /* R72 - Charge Pump 1 */
  74. { 82, 0x0000 }, /* R82 - Charge Pump B */
  75. { 87, 0x0000 }, /* R87 - Write Sequencer 1 */
  76. { 88, 0x0000 }, /* R88 - Write Sequencer 2 */
  77. { 89, 0x0000 }, /* R89 - Write Sequencer 3 */
  78. { 90, 0x0000 }, /* R90 - Write Sequencer 4 */
  79. { 91, 0x0000 }, /* R91 - Write Sequencer 5 */
  80. { 92, 0x0000 }, /* R92 - Write Sequencer 6 */
  81. { 93, 0x0000 }, /* R93 - Write Sequencer 7 */
  82. { 252, 0x0001 }, /* R252 - General test 1 */
  83. };
  84. struct wm8961_priv {
  85. struct regmap *regmap;
  86. int sysclk;
  87. };
  88. static bool wm8961_volatile(struct device *dev, unsigned int reg)
  89. {
  90. switch (reg) {
  91. case WM8961_SOFTWARE_RESET:
  92. case WM8961_WRITE_SEQUENCER_7:
  93. case WM8961_DC_SERVO_1:
  94. return true;
  95. default:
  96. return false;
  97. }
  98. }
  99. static bool wm8961_readable(struct device *dev, unsigned int reg)
  100. {
  101. switch (reg) {
  102. case WM8961_LEFT_INPUT_VOLUME:
  103. case WM8961_RIGHT_INPUT_VOLUME:
  104. case WM8961_LOUT1_VOLUME:
  105. case WM8961_ROUT1_VOLUME:
  106. case WM8961_CLOCKING1:
  107. case WM8961_ADC_DAC_CONTROL_1:
  108. case WM8961_ADC_DAC_CONTROL_2:
  109. case WM8961_AUDIO_INTERFACE_0:
  110. case WM8961_CLOCKING2:
  111. case WM8961_AUDIO_INTERFACE_1:
  112. case WM8961_LEFT_DAC_VOLUME:
  113. case WM8961_RIGHT_DAC_VOLUME:
  114. case WM8961_AUDIO_INTERFACE_2:
  115. case WM8961_SOFTWARE_RESET:
  116. case WM8961_ALC1:
  117. case WM8961_ALC2:
  118. case WM8961_ALC3:
  119. case WM8961_NOISE_GATE:
  120. case WM8961_LEFT_ADC_VOLUME:
  121. case WM8961_RIGHT_ADC_VOLUME:
  122. case WM8961_ADDITIONAL_CONTROL_1:
  123. case WM8961_ADDITIONAL_CONTROL_2:
  124. case WM8961_PWR_MGMT_1:
  125. case WM8961_PWR_MGMT_2:
  126. case WM8961_ADDITIONAL_CONTROL_3:
  127. case WM8961_ANTI_POP:
  128. case WM8961_CLOCKING_3:
  129. case WM8961_ADCL_SIGNAL_PATH:
  130. case WM8961_ADCR_SIGNAL_PATH:
  131. case WM8961_LOUT2_VOLUME:
  132. case WM8961_ROUT2_VOLUME:
  133. case WM8961_PWR_MGMT_3:
  134. case WM8961_ADDITIONAL_CONTROL_4:
  135. case WM8961_CLASS_D_CONTROL_1:
  136. case WM8961_CLASS_D_CONTROL_2:
  137. case WM8961_CLOCKING_4:
  138. case WM8961_DSP_SIDETONE_0:
  139. case WM8961_DSP_SIDETONE_1:
  140. case WM8961_DC_SERVO_0:
  141. case WM8961_DC_SERVO_1:
  142. case WM8961_DC_SERVO_3:
  143. case WM8961_DC_SERVO_5:
  144. case WM8961_ANALOGUE_PGA_BIAS:
  145. case WM8961_ANALOGUE_HP_0:
  146. case WM8961_ANALOGUE_HP_2:
  147. case WM8961_CHARGE_PUMP_1:
  148. case WM8961_CHARGE_PUMP_B:
  149. case WM8961_WRITE_SEQUENCER_1:
  150. case WM8961_WRITE_SEQUENCER_2:
  151. case WM8961_WRITE_SEQUENCER_3:
  152. case WM8961_WRITE_SEQUENCER_4:
  153. case WM8961_WRITE_SEQUENCER_5:
  154. case WM8961_WRITE_SEQUENCER_6:
  155. case WM8961_WRITE_SEQUENCER_7:
  156. case WM8961_GENERAL_TEST_1:
  157. return true;
  158. default:
  159. return false;
  160. }
  161. }
  162. /*
  163. * The headphone output supports special anti-pop sequences giving
  164. * silent power up and power down.
  165. */
  166. static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
  167. struct snd_kcontrol *kcontrol, int event)
  168. {
  169. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  170. u16 hp_reg = snd_soc_component_read(component, WM8961_ANALOGUE_HP_0);
  171. u16 cp_reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_1);
  172. u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
  173. u16 dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
  174. int timeout = 500;
  175. if (event & SND_SOC_DAPM_POST_PMU) {
  176. /* Make sure the output is shorted */
  177. hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
  178. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  179. /* Enable the charge pump */
  180. cp_reg |= WM8961_CP_ENA;
  181. snd_soc_component_write(component, WM8961_CHARGE_PUMP_1, cp_reg);
  182. mdelay(5);
  183. /* Enable the PGA */
  184. pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
  185. snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
  186. /* Enable the amplifier */
  187. hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
  188. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  189. /* Second stage enable */
  190. hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
  191. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  192. /* Enable the DC servo & trigger startup */
  193. dcs_reg |=
  194. WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
  195. WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
  196. dev_dbg(component->dev, "Enabling DC servo\n");
  197. snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
  198. do {
  199. msleep(1);
  200. dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
  201. } while (--timeout &&
  202. dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
  203. WM8961_DCS_TRIG_STARTUP_HPL));
  204. if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
  205. WM8961_DCS_TRIG_STARTUP_HPL))
  206. dev_err(component->dev, "DC servo timed out\n");
  207. else
  208. dev_dbg(component->dev, "DC servo startup complete\n");
  209. /* Enable the output stage */
  210. hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
  211. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  212. /* Remove the short on the output stage */
  213. hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
  214. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  215. }
  216. if (event & SND_SOC_DAPM_PRE_PMD) {
  217. /* Short the output */
  218. hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
  219. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  220. /* Disable the output stage */
  221. hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
  222. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  223. /* Disable DC offset cancellation */
  224. dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
  225. WM8961_DCS_ENA_CHAN_HPL);
  226. snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
  227. /* Finish up */
  228. hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
  229. WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
  230. snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
  231. /* Disable the PGA */
  232. pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
  233. snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
  234. /* Disable the charge pump */
  235. dev_dbg(component->dev, "Disabling charge pump\n");
  236. snd_soc_component_write(component, WM8961_CHARGE_PUMP_1,
  237. cp_reg & ~WM8961_CP_ENA);
  238. }
  239. return 0;
  240. }
  241. static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
  242. struct snd_kcontrol *kcontrol, int event)
  243. {
  244. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  245. u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
  246. u16 spk_reg = snd_soc_component_read(component, WM8961_CLASS_D_CONTROL_1);
  247. if (event & SND_SOC_DAPM_POST_PMU) {
  248. /* Enable the PGA */
  249. pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
  250. snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
  251. /* Enable the amplifier */
  252. spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
  253. snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);
  254. }
  255. if (event & SND_SOC_DAPM_PRE_PMD) {
  256. /* Disable the amplifier */
  257. spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
  258. snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);
  259. /* Disable the PGA */
  260. pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
  261. snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
  262. }
  263. return 0;
  264. }
  265. static const char *adc_hpf_text[] = {
  266. "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
  267. };
  268. static SOC_ENUM_SINGLE_DECL(adc_hpf,
  269. WM8961_ADC_DAC_CONTROL_2, 7, adc_hpf_text);
  270. static const char *dac_deemph_text[] = {
  271. "None", "32kHz", "44.1kHz", "48kHz",
  272. };
  273. static SOC_ENUM_SINGLE_DECL(dac_deemph,
  274. WM8961_ADC_DAC_CONTROL_1, 1, dac_deemph_text);
  275. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  276. static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
  277. static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
  278. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  279. static const DECLARE_TLV_DB_RANGE(boost_tlv,
  280. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  281. 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
  282. 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
  283. 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0)
  284. );
  285. static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
  286. static const struct snd_kcontrol_new wm8961_snd_controls[] = {
  287. SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
  288. 0, 127, 0, out_tlv),
  289. SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
  290. 6, 3, 7, 0, hp_sec_tlv),
  291. SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
  292. 7, 1, 0),
  293. SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
  294. 0, 127, 0, out_tlv),
  295. SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
  296. 7, 1, 0),
  297. SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
  298. SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
  299. SOC_ENUM("DAC Deemphasis", dac_deemph),
  300. SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
  301. SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
  302. WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
  303. SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
  304. SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
  305. SOC_DOUBLE_R_TLV("Capture Volume",
  306. WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
  307. 1, 119, 0, adc_tlv),
  308. SOC_DOUBLE_R_TLV("Capture Boost Volume",
  309. WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
  310. 4, 3, 0, boost_tlv),
  311. SOC_DOUBLE_R_TLV("Capture PGA Volume",
  312. WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
  313. 0, 62, 0, pga_tlv),
  314. SOC_DOUBLE_R("Capture PGA ZC Switch",
  315. WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
  316. 6, 1, 1),
  317. SOC_DOUBLE_R("Capture PGA Switch",
  318. WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
  319. 7, 1, 1),
  320. };
  321. static const char *sidetone_text[] = {
  322. "None", "Left", "Right"
  323. };
  324. static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
  325. WM8961_DSP_SIDETONE_0, 2, sidetone_text);
  326. static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
  327. WM8961_DSP_SIDETONE_1, 2, sidetone_text);
  328. static const struct snd_kcontrol_new dacl_mux =
  329. SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
  330. static const struct snd_kcontrol_new dacr_mux =
  331. SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
  332. static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
  333. SND_SOC_DAPM_INPUT("LINPUT"),
  334. SND_SOC_DAPM_INPUT("RINPUT"),
  335. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
  336. SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
  337. SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
  338. SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
  339. SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
  340. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
  341. SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
  342. SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
  343. SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
  344. SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
  345. /* Handle as a mono path for DCS */
  346. SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
  347. 4, 0, NULL, 0, wm8961_hp_event,
  348. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  349. SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
  350. 4, 0, NULL, 0, wm8961_spk_event,
  351. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  352. SND_SOC_DAPM_OUTPUT("HP_L"),
  353. SND_SOC_DAPM_OUTPUT("HP_R"),
  354. SND_SOC_DAPM_OUTPUT("SPK_LN"),
  355. SND_SOC_DAPM_OUTPUT("SPK_LP"),
  356. SND_SOC_DAPM_OUTPUT("SPK_RN"),
  357. SND_SOC_DAPM_OUTPUT("SPK_RP"),
  358. };
  359. static const struct snd_soc_dapm_route audio_paths[] = {
  360. { "DACL", NULL, "CLK_DSP" },
  361. { "DACL", NULL, "DACL Sidetone" },
  362. { "DACR", NULL, "CLK_DSP" },
  363. { "DACR", NULL, "DACR Sidetone" },
  364. { "DACL Sidetone", "Left", "ADCL" },
  365. { "DACL Sidetone", "Right", "ADCR" },
  366. { "DACR Sidetone", "Left", "ADCL" },
  367. { "DACR Sidetone", "Right", "ADCR" },
  368. { "HP_L", NULL, "Headphone Output" },
  369. { "HP_R", NULL, "Headphone Output" },
  370. { "Headphone Output", NULL, "DACL" },
  371. { "Headphone Output", NULL, "DACR" },
  372. { "SPK_LN", NULL, "Speaker Output" },
  373. { "SPK_LP", NULL, "Speaker Output" },
  374. { "SPK_RN", NULL, "Speaker Output" },
  375. { "SPK_RP", NULL, "Speaker Output" },
  376. { "Speaker Output", NULL, "DACL" },
  377. { "Speaker Output", NULL, "DACR" },
  378. { "ADCL", NULL, "Left Input" },
  379. { "ADCL", NULL, "CLK_DSP" },
  380. { "ADCR", NULL, "Right Input" },
  381. { "ADCR", NULL, "CLK_DSP" },
  382. { "Left Input", NULL, "LINPUT" },
  383. { "Right Input", NULL, "RINPUT" },
  384. };
  385. /* Values for CLK_SYS_RATE */
  386. static struct {
  387. int ratio;
  388. u16 val;
  389. } wm8961_clk_sys_ratio[] = {
  390. { 64, 0 },
  391. { 128, 1 },
  392. { 192, 2 },
  393. { 256, 3 },
  394. { 384, 4 },
  395. { 512, 5 },
  396. { 768, 6 },
  397. { 1024, 7 },
  398. { 1408, 8 },
  399. { 1536, 9 },
  400. };
  401. /* Values for SAMPLE_RATE */
  402. static struct {
  403. int rate;
  404. u16 val;
  405. } wm8961_srate[] = {
  406. { 48000, 0 },
  407. { 44100, 0 },
  408. { 32000, 1 },
  409. { 22050, 2 },
  410. { 24000, 2 },
  411. { 16000, 3 },
  412. { 11250, 4 },
  413. { 12000, 4 },
  414. { 8000, 5 },
  415. };
  416. static int wm8961_hw_params(struct snd_pcm_substream *substream,
  417. struct snd_pcm_hw_params *params,
  418. struct snd_soc_dai *dai)
  419. {
  420. struct snd_soc_component *component = dai->component;
  421. struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
  422. int i, best, target, fs;
  423. u16 reg;
  424. fs = params_rate(params);
  425. if (!wm8961->sysclk) {
  426. dev_err(component->dev, "MCLK has not been specified\n");
  427. return -EINVAL;
  428. }
  429. /* Find the closest sample rate for the filters */
  430. best = 0;
  431. for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
  432. if (abs(wm8961_srate[i].rate - fs) <
  433. abs(wm8961_srate[best].rate - fs))
  434. best = i;
  435. }
  436. reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_3);
  437. reg &= ~WM8961_SAMPLE_RATE_MASK;
  438. reg |= wm8961_srate[best].val;
  439. snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg);
  440. dev_dbg(component->dev, "Selected SRATE %dHz for %dHz\n",
  441. wm8961_srate[best].rate, fs);
  442. /* Select a CLK_SYS/fs ratio equal to or higher than required */
  443. target = wm8961->sysclk / fs;
  444. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
  445. dev_err(component->dev,
  446. "SYSCLK must be at least 64*fs for DAC\n");
  447. return -EINVAL;
  448. }
  449. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
  450. dev_err(component->dev,
  451. "SYSCLK must be at least 256*fs for ADC\n");
  452. return -EINVAL;
  453. }
  454. for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
  455. if (wm8961_clk_sys_ratio[i].ratio >= target)
  456. break;
  457. }
  458. if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
  459. dev_err(component->dev, "Unable to generate CLK_SYS_RATE\n");
  460. return -EINVAL;
  461. }
  462. dev_dbg(component->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
  463. wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
  464. wm8961->sysclk / fs);
  465. reg = snd_soc_component_read(component, WM8961_CLOCKING_4);
  466. reg &= ~WM8961_CLK_SYS_RATE_MASK;
  467. reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
  468. snd_soc_component_write(component, WM8961_CLOCKING_4, reg);
  469. reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
  470. reg &= ~WM8961_WL_MASK;
  471. switch (params_width(params)) {
  472. case 16:
  473. break;
  474. case 20:
  475. reg |= 1 << WM8961_WL_SHIFT;
  476. break;
  477. case 24:
  478. reg |= 2 << WM8961_WL_SHIFT;
  479. break;
  480. case 32:
  481. reg |= 3 << WM8961_WL_SHIFT;
  482. break;
  483. default:
  484. return -EINVAL;
  485. }
  486. snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg);
  487. /* Sloping stop-band filter is recommended for <= 24kHz */
  488. reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
  489. if (fs <= 24000)
  490. reg |= WM8961_DACSLOPE;
  491. else
  492. reg &= ~WM8961_DACSLOPE;
  493. snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
  494. return 0;
  495. }
  496. static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  497. unsigned int freq,
  498. int dir)
  499. {
  500. struct snd_soc_component *component = dai->component;
  501. struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
  502. u16 reg = snd_soc_component_read(component, WM8961_CLOCKING1);
  503. if (freq > 33000000) {
  504. dev_err(component->dev, "MCLK must be <33MHz\n");
  505. return -EINVAL;
  506. }
  507. if (freq > 16500000) {
  508. dev_dbg(component->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
  509. reg |= WM8961_MCLKDIV;
  510. freq /= 2;
  511. } else {
  512. dev_dbg(component->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
  513. reg &= ~WM8961_MCLKDIV;
  514. }
  515. snd_soc_component_write(component, WM8961_CLOCKING1, reg);
  516. wm8961->sysclk = freq;
  517. return 0;
  518. }
  519. static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  520. {
  521. struct snd_soc_component *component = dai->component;
  522. u16 aif = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
  523. aif &= ~(WM8961_BCLKINV | WM8961_LRP |
  524. WM8961_MS | WM8961_FORMAT_MASK);
  525. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  526. case SND_SOC_DAIFMT_CBM_CFM:
  527. aif |= WM8961_MS;
  528. break;
  529. case SND_SOC_DAIFMT_CBS_CFS:
  530. break;
  531. default:
  532. return -EINVAL;
  533. }
  534. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  535. case SND_SOC_DAIFMT_RIGHT_J:
  536. break;
  537. case SND_SOC_DAIFMT_LEFT_J:
  538. aif |= 1;
  539. break;
  540. case SND_SOC_DAIFMT_I2S:
  541. aif |= 2;
  542. break;
  543. case SND_SOC_DAIFMT_DSP_B:
  544. aif |= WM8961_LRP;
  545. fallthrough;
  546. case SND_SOC_DAIFMT_DSP_A:
  547. aif |= 3;
  548. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  549. case SND_SOC_DAIFMT_NB_NF:
  550. case SND_SOC_DAIFMT_IB_NF:
  551. break;
  552. default:
  553. return -EINVAL;
  554. }
  555. break;
  556. default:
  557. return -EINVAL;
  558. }
  559. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  560. case SND_SOC_DAIFMT_NB_NF:
  561. break;
  562. case SND_SOC_DAIFMT_NB_IF:
  563. aif |= WM8961_LRP;
  564. break;
  565. case SND_SOC_DAIFMT_IB_NF:
  566. aif |= WM8961_BCLKINV;
  567. break;
  568. case SND_SOC_DAIFMT_IB_IF:
  569. aif |= WM8961_BCLKINV | WM8961_LRP;
  570. break;
  571. default:
  572. return -EINVAL;
  573. }
  574. return snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, aif);
  575. }
  576. static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
  577. {
  578. struct snd_soc_component *component = dai->component;
  579. u16 reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_2);
  580. if (tristate)
  581. reg |= WM8961_TRIS;
  582. else
  583. reg &= ~WM8961_TRIS;
  584. return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg);
  585. }
  586. static int wm8961_mute(struct snd_soc_dai *dai, int mute, int direction)
  587. {
  588. struct snd_soc_component *component = dai->component;
  589. u16 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_1);
  590. if (mute)
  591. reg |= WM8961_DACMU;
  592. else
  593. reg &= ~WM8961_DACMU;
  594. msleep(17);
  595. return snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_1, reg);
  596. }
  597. static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
  598. {
  599. struct snd_soc_component *component = dai->component;
  600. u16 reg;
  601. switch (div_id) {
  602. case WM8961_BCLK:
  603. reg = snd_soc_component_read(component, WM8961_CLOCKING2);
  604. reg &= ~WM8961_BCLKDIV_MASK;
  605. reg |= div;
  606. snd_soc_component_write(component, WM8961_CLOCKING2, reg);
  607. break;
  608. case WM8961_LRCLK:
  609. reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_2);
  610. reg &= ~WM8961_LRCLK_RATE_MASK;
  611. reg |= div;
  612. snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg);
  613. break;
  614. default:
  615. return -EINVAL;
  616. }
  617. return 0;
  618. }
  619. static int wm8961_set_bias_level(struct snd_soc_component *component,
  620. enum snd_soc_bias_level level)
  621. {
  622. u16 reg;
  623. /* This is all slightly unusual since we have no bypass paths
  624. * and the output amplifier structure means we can just slam
  625. * the biases straight up rather than having to ramp them
  626. * slowly.
  627. */
  628. switch (level) {
  629. case SND_SOC_BIAS_ON:
  630. break;
  631. case SND_SOC_BIAS_PREPARE:
  632. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
  633. /* Enable bias generation */
  634. reg = snd_soc_component_read(component, WM8961_ANTI_POP);
  635. reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
  636. snd_soc_component_write(component, WM8961_ANTI_POP, reg);
  637. /* VMID=2*50k, VREF */
  638. reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
  639. reg &= ~WM8961_VMIDSEL_MASK;
  640. reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
  641. snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
  642. }
  643. break;
  644. case SND_SOC_BIAS_STANDBY:
  645. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
  646. /* VREF off */
  647. reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
  648. reg &= ~WM8961_VREF;
  649. snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
  650. /* Bias generation off */
  651. reg = snd_soc_component_read(component, WM8961_ANTI_POP);
  652. reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
  653. snd_soc_component_write(component, WM8961_ANTI_POP, reg);
  654. /* VMID off */
  655. reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
  656. reg &= ~WM8961_VMIDSEL_MASK;
  657. snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
  658. }
  659. break;
  660. case SND_SOC_BIAS_OFF:
  661. break;
  662. }
  663. return 0;
  664. }
  665. #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
  666. #define WM8961_FORMATS \
  667. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  668. SNDRV_PCM_FMTBIT_S24_LE)
  669. static const struct snd_soc_dai_ops wm8961_dai_ops = {
  670. .hw_params = wm8961_hw_params,
  671. .set_sysclk = wm8961_set_sysclk,
  672. .set_fmt = wm8961_set_fmt,
  673. .mute_stream = wm8961_mute,
  674. .set_tristate = wm8961_set_tristate,
  675. .set_clkdiv = wm8961_set_clkdiv,
  676. .no_capture_mute = 1,
  677. };
  678. static struct snd_soc_dai_driver wm8961_dai = {
  679. .name = "wm8961-hifi",
  680. .playback = {
  681. .stream_name = "HiFi Playback",
  682. .channels_min = 1,
  683. .channels_max = 2,
  684. .rates = WM8961_RATES,
  685. .formats = WM8961_FORMATS,},
  686. .capture = {
  687. .stream_name = "HiFi Capture",
  688. .channels_min = 1,
  689. .channels_max = 2,
  690. .rates = WM8961_RATES,
  691. .formats = WM8961_FORMATS,},
  692. .ops = &wm8961_dai_ops,
  693. };
  694. static int wm8961_probe(struct snd_soc_component *component)
  695. {
  696. u16 reg;
  697. /* Enable class W */
  698. reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_B);
  699. reg |= WM8961_CP_DYN_PWR_MASK;
  700. snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg);
  701. /* Latch volume update bits (right channel only, we always
  702. * write both out) and default ZC on. */
  703. reg = snd_soc_component_read(component, WM8961_ROUT1_VOLUME);
  704. snd_soc_component_write(component, WM8961_ROUT1_VOLUME,
  705. reg | WM8961_LO1ZC | WM8961_OUT1VU);
  706. snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
  707. reg = snd_soc_component_read(component, WM8961_ROUT2_VOLUME);
  708. snd_soc_component_write(component, WM8961_ROUT2_VOLUME,
  709. reg | WM8961_SPKRZC | WM8961_SPKVU);
  710. snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
  711. reg = snd_soc_component_read(component, WM8961_RIGHT_ADC_VOLUME);
  712. snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
  713. reg = snd_soc_component_read(component, WM8961_RIGHT_INPUT_VOLUME);
  714. snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
  715. /* Use soft mute by default */
  716. reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
  717. reg |= WM8961_DACSMM;
  718. snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
  719. /* Use automatic clocking mode by default; for now this is all
  720. * we support.
  721. */
  722. reg = snd_soc_component_read(component, WM8961_CLOCKING_3);
  723. reg &= ~WM8961_MANUAL_MODE;
  724. snd_soc_component_write(component, WM8961_CLOCKING_3, reg);
  725. return 0;
  726. }
  727. #ifdef CONFIG_PM
  728. static int wm8961_resume(struct snd_soc_component *component)
  729. {
  730. snd_soc_component_cache_sync(component);
  731. return 0;
  732. }
  733. #else
  734. #define wm8961_resume NULL
  735. #endif
  736. static const struct snd_soc_component_driver soc_component_dev_wm8961 = {
  737. .probe = wm8961_probe,
  738. .resume = wm8961_resume,
  739. .set_bias_level = wm8961_set_bias_level,
  740. .controls = wm8961_snd_controls,
  741. .num_controls = ARRAY_SIZE(wm8961_snd_controls),
  742. .dapm_widgets = wm8961_dapm_widgets,
  743. .num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets),
  744. .dapm_routes = audio_paths,
  745. .num_dapm_routes = ARRAY_SIZE(audio_paths),
  746. .suspend_bias_off = 1,
  747. .idle_bias_on = 1,
  748. .use_pmdown_time = 1,
  749. .endianness = 1,
  750. .non_legacy_dai_naming = 1,
  751. };
  752. static const struct regmap_config wm8961_regmap = {
  753. .reg_bits = 8,
  754. .val_bits = 16,
  755. .max_register = WM8961_MAX_REGISTER,
  756. .reg_defaults = wm8961_reg_defaults,
  757. .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
  758. .cache_type = REGCACHE_RBTREE,
  759. .volatile_reg = wm8961_volatile,
  760. .readable_reg = wm8961_readable,
  761. };
  762. static int wm8961_i2c_probe(struct i2c_client *i2c,
  763. const struct i2c_device_id *id)
  764. {
  765. struct wm8961_priv *wm8961;
  766. unsigned int val;
  767. int ret;
  768. wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
  769. GFP_KERNEL);
  770. if (wm8961 == NULL)
  771. return -ENOMEM;
  772. wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
  773. if (IS_ERR(wm8961->regmap))
  774. return PTR_ERR(wm8961->regmap);
  775. ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);
  776. if (ret != 0) {
  777. dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
  778. return ret;
  779. }
  780. if (val != 0x1801) {
  781. dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);
  782. return -EINVAL;
  783. }
  784. /* This isn't volatile - readback doesn't correspond to write */
  785. regcache_cache_bypass(wm8961->regmap, true);
  786. ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);
  787. regcache_cache_bypass(wm8961->regmap, false);
  788. if (ret != 0) {
  789. dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
  790. return ret;
  791. }
  792. dev_info(&i2c->dev, "WM8961 family %d revision %c\n",
  793. (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
  794. ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
  795. + 'A');
  796. ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);
  797. if (ret != 0) {
  798. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  799. return ret;
  800. }
  801. i2c_set_clientdata(i2c, wm8961);
  802. ret = devm_snd_soc_register_component(&i2c->dev,
  803. &soc_component_dev_wm8961, &wm8961_dai, 1);
  804. return ret;
  805. }
  806. static const struct i2c_device_id wm8961_i2c_id[] = {
  807. { "wm8961", 0 },
  808. { }
  809. };
  810. MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
  811. static struct i2c_driver wm8961_i2c_driver = {
  812. .driver = {
  813. .name = "wm8961",
  814. },
  815. .probe = wm8961_i2c_probe,
  816. .id_table = wm8961_i2c_id,
  817. };
  818. module_i2c_driver(wm8961_i2c_driver);
  819. MODULE_DESCRIPTION("ASoC WM8961 driver");
  820. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  821. MODULE_LICENSE("GPL");