wm8904.h 90 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * wm8904.h -- WM8904 ASoC driver
  4. *
  5. * Copyright 2009 Wolfson Microelectronics, plc
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #ifndef _WM8904_H
  10. #define _WM8904_H
  11. #define WM8904_CLK_AUTO 0
  12. #define WM8904_CLK_MCLK 1
  13. #define WM8904_CLK_FLL 2
  14. #define WM8904_FLL_MCLK 1
  15. #define WM8904_FLL_BCLK 2
  16. #define WM8904_FLL_LRCLK 3
  17. #define WM8904_FLL_FREE_RUNNING 4
  18. /*
  19. * Register values.
  20. */
  21. #define WM8904_SW_RESET_AND_ID 0x00
  22. #define WM8904_REVISION 0x01
  23. #define WM8904_BIAS_CONTROL_0 0x04
  24. #define WM8904_VMID_CONTROL_0 0x05
  25. #define WM8904_MIC_BIAS_CONTROL_0 0x06
  26. #define WM8904_MIC_BIAS_CONTROL_1 0x07
  27. #define WM8904_ANALOGUE_DAC_0 0x08
  28. #define WM8904_MIC_FILTER_CONTROL 0x09
  29. #define WM8904_ANALOGUE_ADC_0 0x0A
  30. #define WM8904_POWER_MANAGEMENT_0 0x0C
  31. #define WM8904_POWER_MANAGEMENT_2 0x0E
  32. #define WM8904_POWER_MANAGEMENT_3 0x0F
  33. #define WM8904_POWER_MANAGEMENT_6 0x12
  34. #define WM8904_CLOCK_RATES_0 0x14
  35. #define WM8904_CLOCK_RATES_1 0x15
  36. #define WM8904_CLOCK_RATES_2 0x16
  37. #define WM8904_AUDIO_INTERFACE_0 0x18
  38. #define WM8904_AUDIO_INTERFACE_1 0x19
  39. #define WM8904_AUDIO_INTERFACE_2 0x1A
  40. #define WM8904_AUDIO_INTERFACE_3 0x1B
  41. #define WM8904_DAC_DIGITAL_VOLUME_LEFT 0x1E
  42. #define WM8904_DAC_DIGITAL_VOLUME_RIGHT 0x1F
  43. #define WM8904_DAC_DIGITAL_0 0x20
  44. #define WM8904_DAC_DIGITAL_1 0x21
  45. #define WM8904_ADC_DIGITAL_VOLUME_LEFT 0x24
  46. #define WM8904_ADC_DIGITAL_VOLUME_RIGHT 0x25
  47. #define WM8904_ADC_DIGITAL_0 0x26
  48. #define WM8904_DIGITAL_MICROPHONE_0 0x27
  49. #define WM8904_DRC_0 0x28
  50. #define WM8904_DRC_1 0x29
  51. #define WM8904_DRC_2 0x2A
  52. #define WM8904_DRC_3 0x2B
  53. #define WM8904_ANALOGUE_LEFT_INPUT_0 0x2C
  54. #define WM8904_ANALOGUE_RIGHT_INPUT_0 0x2D
  55. #define WM8904_ANALOGUE_LEFT_INPUT_1 0x2E
  56. #define WM8904_ANALOGUE_RIGHT_INPUT_1 0x2F
  57. #define WM8904_ANALOGUE_OUT1_LEFT 0x39
  58. #define WM8904_ANALOGUE_OUT1_RIGHT 0x3A
  59. #define WM8904_ANALOGUE_OUT2_LEFT 0x3B
  60. #define WM8904_ANALOGUE_OUT2_RIGHT 0x3C
  61. #define WM8904_ANALOGUE_OUT12_ZC 0x3D
  62. #define WM8904_DC_SERVO_0 0x43
  63. #define WM8904_DC_SERVO_1 0x44
  64. #define WM8904_DC_SERVO_2 0x45
  65. #define WM8904_DC_SERVO_4 0x47
  66. #define WM8904_DC_SERVO_5 0x48
  67. #define WM8904_DC_SERVO_6 0x49
  68. #define WM8904_DC_SERVO_7 0x4A
  69. #define WM8904_DC_SERVO_8 0x4B
  70. #define WM8904_DC_SERVO_9 0x4C
  71. #define WM8904_DC_SERVO_READBACK_0 0x4D
  72. #define WM8904_ANALOGUE_HP_0 0x5A
  73. #define WM8904_ANALOGUE_LINEOUT_0 0x5E
  74. #define WM8904_CHARGE_PUMP_0 0x62
  75. #define WM8904_CLASS_W_0 0x68
  76. #define WM8904_WRITE_SEQUENCER_0 0x6C
  77. #define WM8904_WRITE_SEQUENCER_1 0x6D
  78. #define WM8904_WRITE_SEQUENCER_2 0x6E
  79. #define WM8904_WRITE_SEQUENCER_3 0x6F
  80. #define WM8904_WRITE_SEQUENCER_4 0x70
  81. #define WM8904_FLL_CONTROL_1 0x74
  82. #define WM8904_FLL_CONTROL_2 0x75
  83. #define WM8904_FLL_CONTROL_3 0x76
  84. #define WM8904_FLL_CONTROL_4 0x77
  85. #define WM8904_FLL_CONTROL_5 0x78
  86. #define WM8904_GPIO_CONTROL_1 0x79
  87. #define WM8904_GPIO_CONTROL_2 0x7A
  88. #define WM8904_GPIO_CONTROL_3 0x7B
  89. #define WM8904_GPIO_CONTROL_4 0x7C
  90. #define WM8904_DIGITAL_PULLS 0x7E
  91. #define WM8904_INTERRUPT_STATUS 0x7F
  92. #define WM8904_INTERRUPT_STATUS_MASK 0x80
  93. #define WM8904_INTERRUPT_POLARITY 0x81
  94. #define WM8904_INTERRUPT_DEBOUNCE 0x82
  95. #define WM8904_EQ1 0x86
  96. #define WM8904_EQ2 0x87
  97. #define WM8904_EQ3 0x88
  98. #define WM8904_EQ4 0x89
  99. #define WM8904_EQ5 0x8A
  100. #define WM8904_EQ6 0x8B
  101. #define WM8904_EQ7 0x8C
  102. #define WM8904_EQ8 0x8D
  103. #define WM8904_EQ9 0x8E
  104. #define WM8904_EQ10 0x8F
  105. #define WM8904_EQ11 0x90
  106. #define WM8904_EQ12 0x91
  107. #define WM8904_EQ13 0x92
  108. #define WM8904_EQ14 0x93
  109. #define WM8904_EQ15 0x94
  110. #define WM8904_EQ16 0x95
  111. #define WM8904_EQ17 0x96
  112. #define WM8904_EQ18 0x97
  113. #define WM8904_EQ19 0x98
  114. #define WM8904_EQ20 0x99
  115. #define WM8904_EQ21 0x9A
  116. #define WM8904_EQ22 0x9B
  117. #define WM8904_EQ23 0x9C
  118. #define WM8904_EQ24 0x9D
  119. #define WM8904_CONTROL_INTERFACE_TEST_1 0xA1
  120. #define WM8904_ADC_TEST_0 0xC6
  121. #define WM8904_ANALOGUE_OUTPUT_BIAS_0 0xCC
  122. #define WM8904_FLL_NCO_TEST_0 0xF7
  123. #define WM8904_FLL_NCO_TEST_1 0xF8
  124. #define WM8904_REGISTER_COUNT 101
  125. #define WM8904_MAX_REGISTER 0xF8
  126. /*
  127. * Field Definitions.
  128. */
  129. /*
  130. * R0 (0x00) - SW Reset and ID
  131. */
  132. #define WM8904_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
  133. #define WM8904_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
  134. #define WM8904_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
  135. /*
  136. * R1 (0x01) - Revision
  137. */
  138. #define WM8904_REVISION_MASK 0x000F /* REVISION - [3:0] */
  139. #define WM8904_REVISION_SHIFT 0 /* REVISION - [3:0] */
  140. #define WM8904_REVISION_WIDTH 16 /* REVISION - [3:0] */
  141. /*
  142. * R4 (0x04) - Bias Control 0
  143. */
  144. #define WM8904_POBCTRL 0x0010 /* POBCTRL */
  145. #define WM8904_POBCTRL_MASK 0x0010 /* POBCTRL */
  146. #define WM8904_POBCTRL_SHIFT 4 /* POBCTRL */
  147. #define WM8904_POBCTRL_WIDTH 1 /* POBCTRL */
  148. #define WM8904_ISEL_MASK 0x000C /* ISEL - [3:2] */
  149. #define WM8904_ISEL_SHIFT 2 /* ISEL - [3:2] */
  150. #define WM8904_ISEL_WIDTH 2 /* ISEL - [3:2] */
  151. #define WM8904_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */
  152. #define WM8904_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */
  153. #define WM8904_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */
  154. #define WM8904_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
  155. #define WM8904_BIAS_ENA 0x0001 /* BIAS_ENA */
  156. #define WM8904_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
  157. #define WM8904_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
  158. #define WM8904_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
  159. /*
  160. * R5 (0x05) - VMID Control 0
  161. */
  162. #define WM8904_VMID_BUF_ENA 0x0040 /* VMID_BUF_ENA */
  163. #define WM8904_VMID_BUF_ENA_MASK 0x0040 /* VMID_BUF_ENA */
  164. #define WM8904_VMID_BUF_ENA_SHIFT 6 /* VMID_BUF_ENA */
  165. #define WM8904_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
  166. #define WM8904_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */
  167. #define WM8904_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */
  168. #define WM8904_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */
  169. #define WM8904_VMID_ENA 0x0001 /* VMID_ENA */
  170. #define WM8904_VMID_ENA_MASK 0x0001 /* VMID_ENA */
  171. #define WM8904_VMID_ENA_SHIFT 0 /* VMID_ENA */
  172. #define WM8904_VMID_ENA_WIDTH 1 /* VMID_ENA */
  173. /*
  174. * R8 (0x08) - Analogue DAC 0
  175. */
  176. #define WM8904_DAC_BIAS_SEL_MASK 0x0018 /* DAC_BIAS_SEL - [4:3] */
  177. #define WM8904_DAC_BIAS_SEL_SHIFT 3 /* DAC_BIAS_SEL - [4:3] */
  178. #define WM8904_DAC_BIAS_SEL_WIDTH 2 /* DAC_BIAS_SEL - [4:3] */
  179. #define WM8904_DAC_VMID_BIAS_SEL_MASK 0x0006 /* DAC_VMID_BIAS_SEL - [2:1] */
  180. #define WM8904_DAC_VMID_BIAS_SEL_SHIFT 1 /* DAC_VMID_BIAS_SEL - [2:1] */
  181. #define WM8904_DAC_VMID_BIAS_SEL_WIDTH 2 /* DAC_VMID_BIAS_SEL - [2:1] */
  182. /*
  183. * R9 (0x09) - mic Filter Control
  184. */
  185. #define WM8904_MIC_DET_SET_THRESHOLD_MASK 0xF000 /* MIC_DET_SET_THRESHOLD - [15:12] */
  186. #define WM8904_MIC_DET_SET_THRESHOLD_SHIFT 12 /* MIC_DET_SET_THRESHOLD - [15:12] */
  187. #define WM8904_MIC_DET_SET_THRESHOLD_WIDTH 4 /* MIC_DET_SET_THRESHOLD - [15:12] */
  188. #define WM8904_MIC_DET_RESET_THRESHOLD_MASK 0x0F00 /* MIC_DET_RESET_THRESHOLD - [11:8] */
  189. #define WM8904_MIC_DET_RESET_THRESHOLD_SHIFT 8 /* MIC_DET_RESET_THRESHOLD - [11:8] */
  190. #define WM8904_MIC_DET_RESET_THRESHOLD_WIDTH 4 /* MIC_DET_RESET_THRESHOLD - [11:8] */
  191. #define WM8904_MIC_SHORT_SET_THRESHOLD_MASK 0x00F0 /* MIC_SHORT_SET_THRESHOLD - [7:4] */
  192. #define WM8904_MIC_SHORT_SET_THRESHOLD_SHIFT 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */
  193. #define WM8904_MIC_SHORT_SET_THRESHOLD_WIDTH 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */
  194. #define WM8904_MIC_SHORT_RESET_THRESHOLD_MASK 0x000F /* MIC_SHORT_RESET_THRESHOLD - [3:0] */
  195. #define WM8904_MIC_SHORT_RESET_THRESHOLD_SHIFT 0 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */
  196. #define WM8904_MIC_SHORT_RESET_THRESHOLD_WIDTH 4 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */
  197. /*
  198. * R10 (0x0A) - Analogue ADC 0
  199. */
  200. #define WM8904_ADC_OSR128 0x0001 /* ADC_OSR128 */
  201. #define WM8904_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */
  202. #define WM8904_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */
  203. #define WM8904_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
  204. /*
  205. * R12 (0x0C) - Power Management 0
  206. */
  207. #define WM8904_INL_ENA 0x0002 /* INL_ENA */
  208. #define WM8904_INL_ENA_MASK 0x0002 /* INL_ENA */
  209. #define WM8904_INL_ENA_SHIFT 1 /* INL_ENA */
  210. #define WM8904_INL_ENA_WIDTH 1 /* INL_ENA */
  211. #define WM8904_INR_ENA 0x0001 /* INR_ENA */
  212. #define WM8904_INR_ENA_MASK 0x0001 /* INR_ENA */
  213. #define WM8904_INR_ENA_SHIFT 0 /* INR_ENA */
  214. #define WM8904_INR_ENA_WIDTH 1 /* INR_ENA */
  215. /*
  216. * R14 (0x0E) - Power Management 2
  217. */
  218. #define WM8904_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */
  219. #define WM8904_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */
  220. #define WM8904_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */
  221. #define WM8904_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */
  222. #define WM8904_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */
  223. #define WM8904_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */
  224. #define WM8904_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */
  225. #define WM8904_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */
  226. /*
  227. * R15 (0x0F) - Power Management 3
  228. */
  229. #define WM8904_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */
  230. #define WM8904_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */
  231. #define WM8904_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */
  232. #define WM8904_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */
  233. #define WM8904_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */
  234. #define WM8904_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */
  235. #define WM8904_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */
  236. #define WM8904_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */
  237. /*
  238. * R18 (0x12) - Power Management 6
  239. */
  240. #define WM8904_DACL_ENA 0x0008 /* DACL_ENA */
  241. #define WM8904_DACL_ENA_MASK 0x0008 /* DACL_ENA */
  242. #define WM8904_DACL_ENA_SHIFT 3 /* DACL_ENA */
  243. #define WM8904_DACL_ENA_WIDTH 1 /* DACL_ENA */
  244. #define WM8904_DACR_ENA 0x0004 /* DACR_ENA */
  245. #define WM8904_DACR_ENA_MASK 0x0004 /* DACR_ENA */
  246. #define WM8904_DACR_ENA_SHIFT 2 /* DACR_ENA */
  247. #define WM8904_DACR_ENA_WIDTH 1 /* DACR_ENA */
  248. #define WM8904_ADCL_ENA 0x0002 /* ADCL_ENA */
  249. #define WM8904_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
  250. #define WM8904_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
  251. #define WM8904_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
  252. #define WM8904_ADCR_ENA 0x0001 /* ADCR_ENA */
  253. #define WM8904_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
  254. #define WM8904_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
  255. #define WM8904_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
  256. /*
  257. * R20 (0x14) - Clock Rates 0
  258. */
  259. #define WM8904_TOCLK_RATE_DIV16 0x4000 /* TOCLK_RATE_DIV16 */
  260. #define WM8904_TOCLK_RATE_DIV16_MASK 0x4000 /* TOCLK_RATE_DIV16 */
  261. #define WM8904_TOCLK_RATE_DIV16_SHIFT 14 /* TOCLK_RATE_DIV16 */
  262. #define WM8904_TOCLK_RATE_DIV16_WIDTH 1 /* TOCLK_RATE_DIV16 */
  263. #define WM8904_TOCLK_RATE_X4 0x2000 /* TOCLK_RATE_X4 */
  264. #define WM8904_TOCLK_RATE_X4_MASK 0x2000 /* TOCLK_RATE_X4 */
  265. #define WM8904_TOCLK_RATE_X4_SHIFT 13 /* TOCLK_RATE_X4 */
  266. #define WM8904_TOCLK_RATE_X4_WIDTH 1 /* TOCLK_RATE_X4 */
  267. #define WM8904_SR_MODE 0x1000 /* SR_MODE */
  268. #define WM8904_SR_MODE_MASK 0x1000 /* SR_MODE */
  269. #define WM8904_SR_MODE_SHIFT 12 /* SR_MODE */
  270. #define WM8904_SR_MODE_WIDTH 1 /* SR_MODE */
  271. #define WM8904_MCLK_DIV 0x0001 /* MCLK_DIV */
  272. #define WM8904_MCLK_DIV_MASK 0x0001 /* MCLK_DIV */
  273. #define WM8904_MCLK_DIV_SHIFT 0 /* MCLK_DIV */
  274. #define WM8904_MCLK_DIV_WIDTH 1 /* MCLK_DIV */
  275. /*
  276. * R21 (0x15) - Clock Rates 1
  277. */
  278. #define WM8904_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */
  279. #define WM8904_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */
  280. #define WM8904_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */
  281. #define WM8904_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */
  282. #define WM8904_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */
  283. #define WM8904_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */
  284. /*
  285. * R22 (0x16) - Clock Rates 2
  286. */
  287. #define WM8904_MCLK_INV 0x8000 /* MCLK_INV */
  288. #define WM8904_MCLK_INV_MASK 0x8000 /* MCLK_INV */
  289. #define WM8904_MCLK_INV_SHIFT 15 /* MCLK_INV */
  290. #define WM8904_MCLK_INV_WIDTH 1 /* MCLK_INV */
  291. #define WM8904_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
  292. #define WM8904_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */
  293. #define WM8904_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */
  294. #define WM8904_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
  295. #define WM8904_TOCLK_RATE 0x1000 /* TOCLK_RATE */
  296. #define WM8904_TOCLK_RATE_MASK 0x1000 /* TOCLK_RATE */
  297. #define WM8904_TOCLK_RATE_SHIFT 12 /* TOCLK_RATE */
  298. #define WM8904_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
  299. #define WM8904_OPCLK_ENA 0x0008 /* OPCLK_ENA */
  300. #define WM8904_OPCLK_ENA_MASK 0x0008 /* OPCLK_ENA */
  301. #define WM8904_OPCLK_ENA_SHIFT 3 /* OPCLK_ENA */
  302. #define WM8904_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
  303. #define WM8904_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */
  304. #define WM8904_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */
  305. #define WM8904_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */
  306. #define WM8904_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
  307. #define WM8904_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
  308. #define WM8904_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
  309. #define WM8904_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
  310. #define WM8904_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
  311. #define WM8904_TOCLK_ENA 0x0001 /* TOCLK_ENA */
  312. #define WM8904_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */
  313. #define WM8904_TOCLK_ENA_SHIFT 0 /* TOCLK_ENA */
  314. #define WM8904_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
  315. /*
  316. * R24 (0x18) - Audio Interface 0
  317. */
  318. #define WM8904_DACL_DATINV 0x1000 /* DACL_DATINV */
  319. #define WM8904_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */
  320. #define WM8904_DACL_DATINV_SHIFT 12 /* DACL_DATINV */
  321. #define WM8904_DACL_DATINV_WIDTH 1 /* DACL_DATINV */
  322. #define WM8904_DACR_DATINV 0x0800 /* DACR_DATINV */
  323. #define WM8904_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */
  324. #define WM8904_DACR_DATINV_SHIFT 11 /* DACR_DATINV */
  325. #define WM8904_DACR_DATINV_WIDTH 1 /* DACR_DATINV */
  326. #define WM8904_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */
  327. #define WM8904_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */
  328. #define WM8904_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */
  329. #define WM8904_LOOPBACK 0x0100 /* LOOPBACK */
  330. #define WM8904_LOOPBACK_MASK 0x0100 /* LOOPBACK */
  331. #define WM8904_LOOPBACK_SHIFT 8 /* LOOPBACK */
  332. #define WM8904_LOOPBACK_WIDTH 1 /* LOOPBACK */
  333. #define WM8904_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */
  334. #define WM8904_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */
  335. #define WM8904_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */
  336. #define WM8904_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */
  337. #define WM8904_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */
  338. #define WM8904_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */
  339. #define WM8904_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */
  340. #define WM8904_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */
  341. #define WM8904_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */
  342. #define WM8904_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */
  343. #define WM8904_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */
  344. #define WM8904_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */
  345. #define WM8904_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */
  346. #define WM8904_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */
  347. #define WM8904_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */
  348. #define WM8904_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */
  349. #define WM8904_ADC_COMP 0x0008 /* ADC_COMP */
  350. #define WM8904_ADC_COMP_MASK 0x0008 /* ADC_COMP */
  351. #define WM8904_ADC_COMP_SHIFT 3 /* ADC_COMP */
  352. #define WM8904_ADC_COMP_WIDTH 1 /* ADC_COMP */
  353. #define WM8904_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */
  354. #define WM8904_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */
  355. #define WM8904_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */
  356. #define WM8904_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
  357. #define WM8904_DAC_COMP 0x0002 /* DAC_COMP */
  358. #define WM8904_DAC_COMP_MASK 0x0002 /* DAC_COMP */
  359. #define WM8904_DAC_COMP_SHIFT 1 /* DAC_COMP */
  360. #define WM8904_DAC_COMP_WIDTH 1 /* DAC_COMP */
  361. #define WM8904_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
  362. #define WM8904_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
  363. #define WM8904_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
  364. #define WM8904_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
  365. /*
  366. * R25 (0x19) - Audio Interface 1
  367. */
  368. #define WM8904_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
  369. #define WM8904_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */
  370. #define WM8904_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */
  371. #define WM8904_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */
  372. #define WM8904_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
  373. #define WM8904_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */
  374. #define WM8904_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */
  375. #define WM8904_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */
  376. #define WM8904_AIFADC_TDM 0x0800 /* AIFADC_TDM */
  377. #define WM8904_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */
  378. #define WM8904_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */
  379. #define WM8904_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */
  380. #define WM8904_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */
  381. #define WM8904_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */
  382. #define WM8904_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */
  383. #define WM8904_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */
  384. #define WM8904_AIF_TRIS 0x0100 /* AIF_TRIS */
  385. #define WM8904_AIF_TRIS_MASK 0x0100 /* AIF_TRIS */
  386. #define WM8904_AIF_TRIS_SHIFT 8 /* AIF_TRIS */
  387. #define WM8904_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
  388. #define WM8904_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
  389. #define WM8904_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
  390. #define WM8904_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
  391. #define WM8904_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
  392. #define WM8904_BCLK_DIR 0x0040 /* BCLK_DIR */
  393. #define WM8904_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
  394. #define WM8904_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
  395. #define WM8904_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
  396. #define WM8904_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
  397. #define WM8904_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
  398. #define WM8904_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
  399. #define WM8904_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
  400. #define WM8904_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
  401. #define WM8904_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
  402. #define WM8904_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
  403. #define WM8904_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
  404. #define WM8904_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
  405. #define WM8904_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
  406. /*
  407. * R26 (0x1A) - Audio Interface 2
  408. */
  409. #define WM8904_OPCLK_DIV_MASK 0x0F00 /* OPCLK_DIV - [11:8] */
  410. #define WM8904_OPCLK_DIV_SHIFT 8 /* OPCLK_DIV - [11:8] */
  411. #define WM8904_OPCLK_DIV_WIDTH 4 /* OPCLK_DIV - [11:8] */
  412. #define WM8904_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
  413. #define WM8904_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
  414. #define WM8904_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
  415. /*
  416. * R27 (0x1B) - Audio Interface 3
  417. */
  418. #define WM8904_LRCLK_DIR 0x0800 /* LRCLK_DIR */
  419. #define WM8904_LRCLK_DIR_MASK 0x0800 /* LRCLK_DIR */
  420. #define WM8904_LRCLK_DIR_SHIFT 11 /* LRCLK_DIR */
  421. #define WM8904_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
  422. #define WM8904_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
  423. #define WM8904_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
  424. #define WM8904_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
  425. /*
  426. * R30 (0x1E) - DAC Digital Volume Left
  427. */
  428. #define WM8904_DAC_VU 0x0100 /* DAC_VU */
  429. #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */
  430. #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */
  431. #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */
  432. #define WM8904_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
  433. #define WM8904_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
  434. #define WM8904_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
  435. /*
  436. * R31 (0x1F) - DAC Digital Volume Right
  437. */
  438. #define WM8904_DAC_VU 0x0100 /* DAC_VU */
  439. #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */
  440. #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */
  441. #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */
  442. #define WM8904_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
  443. #define WM8904_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
  444. #define WM8904_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
  445. /*
  446. * R32 (0x20) - DAC Digital 0
  447. */
  448. #define WM8904_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */
  449. #define WM8904_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */
  450. #define WM8904_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */
  451. #define WM8904_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */
  452. #define WM8904_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */
  453. #define WM8904_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */
  454. #define WM8904_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
  455. #define WM8904_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
  456. #define WM8904_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
  457. #define WM8904_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */
  458. #define WM8904_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */
  459. #define WM8904_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */
  460. /*
  461. * R33 (0x21) - DAC Digital 1
  462. */
  463. #define WM8904_DAC_MONO 0x1000 /* DAC_MONO */
  464. #define WM8904_DAC_MONO_MASK 0x1000 /* DAC_MONO */
  465. #define WM8904_DAC_MONO_SHIFT 12 /* DAC_MONO */
  466. #define WM8904_DAC_MONO_WIDTH 1 /* DAC_MONO */
  467. #define WM8904_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */
  468. #define WM8904_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */
  469. #define WM8904_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */
  470. #define WM8904_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */
  471. #define WM8904_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
  472. #define WM8904_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
  473. #define WM8904_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
  474. #define WM8904_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
  475. #define WM8904_DAC_UNMUTE_RAMP 0x0200 /* DAC_UNMUTE_RAMP */
  476. #define WM8904_DAC_UNMUTE_RAMP_MASK 0x0200 /* DAC_UNMUTE_RAMP */
  477. #define WM8904_DAC_UNMUTE_RAMP_SHIFT 9 /* DAC_UNMUTE_RAMP */
  478. #define WM8904_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */
  479. #define WM8904_DAC_OSR128 0x0040 /* DAC_OSR128 */
  480. #define WM8904_DAC_OSR128_MASK 0x0040 /* DAC_OSR128 */
  481. #define WM8904_DAC_OSR128_SHIFT 6 /* DAC_OSR128 */
  482. #define WM8904_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
  483. #define WM8904_DAC_MUTE 0x0008 /* DAC_MUTE */
  484. #define WM8904_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
  485. #define WM8904_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
  486. #define WM8904_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
  487. #define WM8904_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
  488. #define WM8904_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
  489. #define WM8904_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
  490. /*
  491. * R36 (0x24) - ADC Digital Volume Left
  492. */
  493. #define WM8904_ADC_VU 0x0100 /* ADC_VU */
  494. #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */
  495. #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */
  496. #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */
  497. #define WM8904_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
  498. #define WM8904_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
  499. #define WM8904_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
  500. /*
  501. * R37 (0x25) - ADC Digital Volume Right
  502. */
  503. #define WM8904_ADC_VU 0x0100 /* ADC_VU */
  504. #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */
  505. #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */
  506. #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */
  507. #define WM8904_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
  508. #define WM8904_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
  509. #define WM8904_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
  510. /*
  511. * R38 (0x26) - ADC Digital 0
  512. */
  513. #define WM8904_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */
  514. #define WM8904_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */
  515. #define WM8904_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */
  516. #define WM8904_ADC_HPF 0x0010 /* ADC_HPF */
  517. #define WM8904_ADC_HPF_MASK 0x0010 /* ADC_HPF */
  518. #define WM8904_ADC_HPF_SHIFT 4 /* ADC_HPF */
  519. #define WM8904_ADC_HPF_WIDTH 1 /* ADC_HPF */
  520. #define WM8904_ADCL_DATINV 0x0002 /* ADCL_DATINV */
  521. #define WM8904_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */
  522. #define WM8904_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */
  523. #define WM8904_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */
  524. #define WM8904_ADCR_DATINV 0x0001 /* ADCR_DATINV */
  525. #define WM8904_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
  526. #define WM8904_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */
  527. #define WM8904_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */
  528. /*
  529. * R39 (0x27) - Digital Microphone 0
  530. */
  531. #define WM8904_DMIC_ENA 0x1000 /* DMIC_ENA */
  532. #define WM8904_DMIC_ENA_MASK 0x1000 /* DMIC_ENA */
  533. #define WM8904_DMIC_ENA_SHIFT 12 /* DMIC_ENA */
  534. #define WM8904_DMIC_ENA_WIDTH 1 /* DMIC_ENA */
  535. #define WM8904_DMIC_SRC 0x0800 /* DMIC_SRC */
  536. #define WM8904_DMIC_SRC_MASK 0x0800 /* DMIC_SRC */
  537. #define WM8904_DMIC_SRC_SHIFT 11 /* DMIC_SRC */
  538. #define WM8904_DMIC_SRC_WIDTH 1 /* DMIC_SRC */
  539. /*
  540. * R40 (0x28) - DRC 0
  541. */
  542. #define WM8904_DRC_ENA 0x8000 /* DRC_ENA */
  543. #define WM8904_DRC_ENA_MASK 0x8000 /* DRC_ENA */
  544. #define WM8904_DRC_ENA_SHIFT 15 /* DRC_ENA */
  545. #define WM8904_DRC_ENA_WIDTH 1 /* DRC_ENA */
  546. #define WM8904_DRC_DAC_PATH 0x4000 /* DRC_DAC_PATH */
  547. #define WM8904_DRC_DAC_PATH_MASK 0x4000 /* DRC_DAC_PATH */
  548. #define WM8904_DRC_DAC_PATH_SHIFT 14 /* DRC_DAC_PATH */
  549. #define WM8904_DRC_DAC_PATH_WIDTH 1 /* DRC_DAC_PATH */
  550. #define WM8904_DRC_GS_HYST_LVL_MASK 0x1800 /* DRC_GS_HYST_LVL - [12:11] */
  551. #define WM8904_DRC_GS_HYST_LVL_SHIFT 11 /* DRC_GS_HYST_LVL - [12:11] */
  552. #define WM8904_DRC_GS_HYST_LVL_WIDTH 2 /* DRC_GS_HYST_LVL - [12:11] */
  553. #define WM8904_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
  554. #define WM8904_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
  555. #define WM8904_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
  556. #define WM8904_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */
  557. #define WM8904_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */
  558. #define WM8904_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */
  559. #define WM8904_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */
  560. #define WM8904_DRC_GS_ENA 0x0008 /* DRC_GS_ENA */
  561. #define WM8904_DRC_GS_ENA_MASK 0x0008 /* DRC_GS_ENA */
  562. #define WM8904_DRC_GS_ENA_SHIFT 3 /* DRC_GS_ENA */
  563. #define WM8904_DRC_GS_ENA_WIDTH 1 /* DRC_GS_ENA */
  564. #define WM8904_DRC_QR 0x0004 /* DRC_QR */
  565. #define WM8904_DRC_QR_MASK 0x0004 /* DRC_QR */
  566. #define WM8904_DRC_QR_SHIFT 2 /* DRC_QR */
  567. #define WM8904_DRC_QR_WIDTH 1 /* DRC_QR */
  568. #define WM8904_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
  569. #define WM8904_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
  570. #define WM8904_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
  571. #define WM8904_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
  572. #define WM8904_DRC_GS_HYST 0x0001 /* DRC_GS_HYST */
  573. #define WM8904_DRC_GS_HYST_MASK 0x0001 /* DRC_GS_HYST */
  574. #define WM8904_DRC_GS_HYST_SHIFT 0 /* DRC_GS_HYST */
  575. #define WM8904_DRC_GS_HYST_WIDTH 1 /* DRC_GS_HYST */
  576. /*
  577. * R41 (0x29) - DRC 1
  578. */
  579. #define WM8904_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
  580. #define WM8904_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
  581. #define WM8904_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
  582. #define WM8904_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
  583. #define WM8904_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
  584. #define WM8904_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
  585. #define WM8904_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
  586. #define WM8904_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
  587. #define WM8904_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
  588. #define WM8904_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
  589. #define WM8904_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
  590. #define WM8904_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
  591. #define WM8904_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
  592. #define WM8904_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
  593. #define WM8904_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
  594. #define WM8904_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
  595. #define WM8904_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
  596. #define WM8904_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
  597. /*
  598. * R42 (0x2A) - DRC 2
  599. */
  600. #define WM8904_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
  601. #define WM8904_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
  602. #define WM8904_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
  603. #define WM8904_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
  604. #define WM8904_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
  605. #define WM8904_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
  606. /*
  607. * R43 (0x2B) - DRC 3
  608. */
  609. #define WM8904_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
  610. #define WM8904_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
  611. #define WM8904_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
  612. #define WM8904_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
  613. #define WM8904_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
  614. #define WM8904_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
  615. /*
  616. * R44 (0x2C) - Analogue Left Input 0
  617. */
  618. #define WM8904_LINMUTE 0x0080 /* LINMUTE */
  619. #define WM8904_LINMUTE_MASK 0x0080 /* LINMUTE */
  620. #define WM8904_LINMUTE_SHIFT 7 /* LINMUTE */
  621. #define WM8904_LINMUTE_WIDTH 1 /* LINMUTE */
  622. #define WM8904_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */
  623. #define WM8904_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */
  624. #define WM8904_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */
  625. /*
  626. * R45 (0x2D) - Analogue Right Input 0
  627. */
  628. #define WM8904_RINMUTE 0x0080 /* RINMUTE */
  629. #define WM8904_RINMUTE_MASK 0x0080 /* RINMUTE */
  630. #define WM8904_RINMUTE_SHIFT 7 /* RINMUTE */
  631. #define WM8904_RINMUTE_WIDTH 1 /* RINMUTE */
  632. #define WM8904_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */
  633. #define WM8904_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */
  634. #define WM8904_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */
  635. /*
  636. * R46 (0x2E) - Analogue Left Input 1
  637. */
  638. #define WM8904_INL_CM_ENA 0x0040 /* INL_CM_ENA */
  639. #define WM8904_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */
  640. #define WM8904_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */
  641. #define WM8904_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */
  642. #define WM8904_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */
  643. #define WM8904_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */
  644. #define WM8904_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */
  645. #define WM8904_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */
  646. #define WM8904_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */
  647. #define WM8904_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */
  648. #define WM8904_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */
  649. #define WM8904_L_MODE_SHIFT 0 /* L_MODE - [1:0] */
  650. #define WM8904_L_MODE_WIDTH 2 /* L_MODE - [1:0] */
  651. /*
  652. * R47 (0x2F) - Analogue Right Input 1
  653. */
  654. #define WM8904_INR_CM_ENA 0x0040 /* INR_CM_ENA */
  655. #define WM8904_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */
  656. #define WM8904_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */
  657. #define WM8904_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */
  658. #define WM8904_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */
  659. #define WM8904_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */
  660. #define WM8904_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */
  661. #define WM8904_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */
  662. #define WM8904_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */
  663. #define WM8904_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */
  664. #define WM8904_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */
  665. #define WM8904_R_MODE_SHIFT 0 /* R_MODE - [1:0] */
  666. #define WM8904_R_MODE_WIDTH 2 /* R_MODE - [1:0] */
  667. /*
  668. * R57 (0x39) - Analogue OUT1 Left
  669. */
  670. #define WM8904_HPOUTL_MUTE 0x0100 /* HPOUTL_MUTE */
  671. #define WM8904_HPOUTL_MUTE_MASK 0x0100 /* HPOUTL_MUTE */
  672. #define WM8904_HPOUTL_MUTE_SHIFT 8 /* HPOUTL_MUTE */
  673. #define WM8904_HPOUTL_MUTE_WIDTH 1 /* HPOUTL_MUTE */
  674. #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */
  675. #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */
  676. #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */
  677. #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */
  678. #define WM8904_HPOUTLZC 0x0040 /* HPOUTLZC */
  679. #define WM8904_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */
  680. #define WM8904_HPOUTLZC_SHIFT 6 /* HPOUTLZC */
  681. #define WM8904_HPOUTLZC_WIDTH 1 /* HPOUTLZC */
  682. #define WM8904_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */
  683. #define WM8904_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */
  684. #define WM8904_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */
  685. /*
  686. * R58 (0x3A) - Analogue OUT1 Right
  687. */
  688. #define WM8904_HPOUTR_MUTE 0x0100 /* HPOUTR_MUTE */
  689. #define WM8904_HPOUTR_MUTE_MASK 0x0100 /* HPOUTR_MUTE */
  690. #define WM8904_HPOUTR_MUTE_SHIFT 8 /* HPOUTR_MUTE */
  691. #define WM8904_HPOUTR_MUTE_WIDTH 1 /* HPOUTR_MUTE */
  692. #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */
  693. #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */
  694. #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */
  695. #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */
  696. #define WM8904_HPOUTRZC 0x0040 /* HPOUTRZC */
  697. #define WM8904_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */
  698. #define WM8904_HPOUTRZC_SHIFT 6 /* HPOUTRZC */
  699. #define WM8904_HPOUTRZC_WIDTH 1 /* HPOUTRZC */
  700. #define WM8904_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */
  701. #define WM8904_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */
  702. #define WM8904_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */
  703. /*
  704. * R59 (0x3B) - Analogue OUT2 Left
  705. */
  706. #define WM8904_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */
  707. #define WM8904_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */
  708. #define WM8904_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */
  709. #define WM8904_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */
  710. #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */
  711. #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */
  712. #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */
  713. #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */
  714. #define WM8904_LINEOUTLZC 0x0040 /* LINEOUTLZC */
  715. #define WM8904_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */
  716. #define WM8904_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */
  717. #define WM8904_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */
  718. #define WM8904_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */
  719. #define WM8904_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */
  720. #define WM8904_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */
  721. /*
  722. * R60 (0x3C) - Analogue OUT2 Right
  723. */
  724. #define WM8904_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */
  725. #define WM8904_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */
  726. #define WM8904_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */
  727. #define WM8904_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */
  728. #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */
  729. #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */
  730. #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */
  731. #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */
  732. #define WM8904_LINEOUTRZC 0x0040 /* LINEOUTRZC */
  733. #define WM8904_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */
  734. #define WM8904_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */
  735. #define WM8904_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */
  736. #define WM8904_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */
  737. #define WM8904_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */
  738. #define WM8904_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */
  739. /*
  740. * R61 (0x3D) - Analogue OUT12 ZC
  741. */
  742. #define WM8904_HPL_BYP_ENA 0x0008 /* HPL_BYP_ENA */
  743. #define WM8904_HPL_BYP_ENA_MASK 0x0008 /* HPL_BYP_ENA */
  744. #define WM8904_HPL_BYP_ENA_SHIFT 3 /* HPL_BYP_ENA */
  745. #define WM8904_HPL_BYP_ENA_WIDTH 1 /* HPL_BYP_ENA */
  746. #define WM8904_HPR_BYP_ENA 0x0004 /* HPR_BYP_ENA */
  747. #define WM8904_HPR_BYP_ENA_MASK 0x0004 /* HPR_BYP_ENA */
  748. #define WM8904_HPR_BYP_ENA_SHIFT 2 /* HPR_BYP_ENA */
  749. #define WM8904_HPR_BYP_ENA_WIDTH 1 /* HPR_BYP_ENA */
  750. #define WM8904_LINEOUTL_BYP_ENA 0x0002 /* LINEOUTL_BYP_ENA */
  751. #define WM8904_LINEOUTL_BYP_ENA_MASK 0x0002 /* LINEOUTL_BYP_ENA */
  752. #define WM8904_LINEOUTL_BYP_ENA_SHIFT 1 /* LINEOUTL_BYP_ENA */
  753. #define WM8904_LINEOUTL_BYP_ENA_WIDTH 1 /* LINEOUTL_BYP_ENA */
  754. #define WM8904_LINEOUTR_BYP_ENA 0x0001 /* LINEOUTR_BYP_ENA */
  755. #define WM8904_LINEOUTR_BYP_ENA_MASK 0x0001 /* LINEOUTR_BYP_ENA */
  756. #define WM8904_LINEOUTR_BYP_ENA_SHIFT 0 /* LINEOUTR_BYP_ENA */
  757. #define WM8904_LINEOUTR_BYP_ENA_WIDTH 1 /* LINEOUTR_BYP_ENA */
  758. /*
  759. * R67 (0x43) - DC Servo 0
  760. */
  761. #define WM8904_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */
  762. #define WM8904_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */
  763. #define WM8904_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */
  764. #define WM8904_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
  765. #define WM8904_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */
  766. #define WM8904_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */
  767. #define WM8904_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */
  768. #define WM8904_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
  769. #define WM8904_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
  770. #define WM8904_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
  771. #define WM8904_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
  772. #define WM8904_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
  773. #define WM8904_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
  774. #define WM8904_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
  775. #define WM8904_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
  776. #define WM8904_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
  777. /*
  778. * R68 (0x44) - DC Servo 1
  779. */
  780. #define WM8904_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */
  781. #define WM8904_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */
  782. #define WM8904_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
  783. #define WM8904_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
  784. #define WM8904_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */
  785. #define WM8904_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */
  786. #define WM8904_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */
  787. #define WM8904_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
  788. #define WM8904_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
  789. #define WM8904_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
  790. #define WM8904_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
  791. #define WM8904_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
  792. #define WM8904_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
  793. #define WM8904_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
  794. #define WM8904_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
  795. #define WM8904_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
  796. #define WM8904_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */
  797. #define WM8904_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */
  798. #define WM8904_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */
  799. #define WM8904_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
  800. #define WM8904_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */
  801. #define WM8904_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */
  802. #define WM8904_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */
  803. #define WM8904_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
  804. #define WM8904_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
  805. #define WM8904_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
  806. #define WM8904_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
  807. #define WM8904_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
  808. #define WM8904_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
  809. #define WM8904_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
  810. #define WM8904_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
  811. #define WM8904_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
  812. #define WM8904_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */
  813. #define WM8904_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */
  814. #define WM8904_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */
  815. #define WM8904_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
  816. #define WM8904_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */
  817. #define WM8904_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */
  818. #define WM8904_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */
  819. #define WM8904_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
  820. #define WM8904_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
  821. #define WM8904_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
  822. #define WM8904_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
  823. #define WM8904_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
  824. #define WM8904_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
  825. #define WM8904_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
  826. #define WM8904_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
  827. #define WM8904_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
  828. #define WM8904_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */
  829. #define WM8904_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */
  830. #define WM8904_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */
  831. #define WM8904_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
  832. #define WM8904_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */
  833. #define WM8904_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */
  834. #define WM8904_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */
  835. #define WM8904_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
  836. #define WM8904_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */
  837. #define WM8904_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */
  838. #define WM8904_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
  839. #define WM8904_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
  840. #define WM8904_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
  841. #define WM8904_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
  842. #define WM8904_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */
  843. #define WM8904_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
  844. /*
  845. * R69 (0x45) - DC Servo 2
  846. */
  847. #define WM8904_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
  848. #define WM8904_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
  849. #define WM8904_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
  850. #define WM8904_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
  851. #define WM8904_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
  852. #define WM8904_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
  853. /*
  854. * R71 (0x47) - DC Servo 4
  855. */
  856. #define WM8904_DCS_SERIES_NO_23_MASK 0x007F /* DCS_SERIES_NO_23 - [6:0] */
  857. #define WM8904_DCS_SERIES_NO_23_SHIFT 0 /* DCS_SERIES_NO_23 - [6:0] */
  858. #define WM8904_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [6:0] */
  859. /*
  860. * R72 (0x48) - DC Servo 5
  861. */
  862. #define WM8904_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
  863. #define WM8904_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
  864. #define WM8904_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
  865. /*
  866. * R73 (0x49) - DC Servo 6
  867. */
  868. #define WM8904_DCS_DAC_WR_VAL_3_MASK 0x00FF /* DCS_DAC_WR_VAL_3 - [7:0] */
  869. #define WM8904_DCS_DAC_WR_VAL_3_SHIFT 0 /* DCS_DAC_WR_VAL_3 - [7:0] */
  870. #define WM8904_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [7:0] */
  871. /*
  872. * R74 (0x4A) - DC Servo 7
  873. */
  874. #define WM8904_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
  875. #define WM8904_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
  876. #define WM8904_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
  877. /*
  878. * R75 (0x4B) - DC Servo 8
  879. */
  880. #define WM8904_DCS_DAC_WR_VAL_1_MASK 0x00FF /* DCS_DAC_WR_VAL_1 - [7:0] */
  881. #define WM8904_DCS_DAC_WR_VAL_1_SHIFT 0 /* DCS_DAC_WR_VAL_1 - [7:0] */
  882. #define WM8904_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [7:0] */
  883. /*
  884. * R76 (0x4C) - DC Servo 9
  885. */
  886. #define WM8904_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
  887. #define WM8904_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
  888. #define WM8904_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
  889. /*
  890. * R77 (0x4D) - DC Servo Readback 0
  891. */
  892. #define WM8904_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
  893. #define WM8904_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
  894. #define WM8904_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
  895. #define WM8904_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
  896. #define WM8904_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
  897. #define WM8904_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
  898. #define WM8904_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
  899. #define WM8904_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
  900. #define WM8904_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
  901. /*
  902. * R90 (0x5A) - Analogue HP 0
  903. */
  904. #define WM8904_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */
  905. #define WM8904_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */
  906. #define WM8904_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */
  907. #define WM8904_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */
  908. #define WM8904_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */
  909. #define WM8904_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */
  910. #define WM8904_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */
  911. #define WM8904_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */
  912. #define WM8904_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */
  913. #define WM8904_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */
  914. #define WM8904_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */
  915. #define WM8904_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */
  916. #define WM8904_HPL_ENA 0x0010 /* HPL_ENA */
  917. #define WM8904_HPL_ENA_MASK 0x0010 /* HPL_ENA */
  918. #define WM8904_HPL_ENA_SHIFT 4 /* HPL_ENA */
  919. #define WM8904_HPL_ENA_WIDTH 1 /* HPL_ENA */
  920. #define WM8904_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */
  921. #define WM8904_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */
  922. #define WM8904_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */
  923. #define WM8904_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */
  924. #define WM8904_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */
  925. #define WM8904_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */
  926. #define WM8904_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */
  927. #define WM8904_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */
  928. #define WM8904_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */
  929. #define WM8904_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */
  930. #define WM8904_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */
  931. #define WM8904_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */
  932. #define WM8904_HPR_ENA 0x0001 /* HPR_ENA */
  933. #define WM8904_HPR_ENA_MASK 0x0001 /* HPR_ENA */
  934. #define WM8904_HPR_ENA_SHIFT 0 /* HPR_ENA */
  935. #define WM8904_HPR_ENA_WIDTH 1 /* HPR_ENA */
  936. /*
  937. * R94 (0x5E) - Analogue Lineout 0
  938. */
  939. #define WM8904_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */
  940. #define WM8904_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */
  941. #define WM8904_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */
  942. #define WM8904_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */
  943. #define WM8904_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */
  944. #define WM8904_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */
  945. #define WM8904_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */
  946. #define WM8904_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */
  947. #define WM8904_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */
  948. #define WM8904_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */
  949. #define WM8904_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */
  950. #define WM8904_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */
  951. #define WM8904_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */
  952. #define WM8904_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */
  953. #define WM8904_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */
  954. #define WM8904_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */
  955. #define WM8904_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */
  956. #define WM8904_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */
  957. #define WM8904_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */
  958. #define WM8904_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */
  959. #define WM8904_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */
  960. #define WM8904_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */
  961. #define WM8904_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */
  962. #define WM8904_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */
  963. #define WM8904_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */
  964. #define WM8904_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */
  965. #define WM8904_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */
  966. #define WM8904_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */
  967. #define WM8904_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */
  968. #define WM8904_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */
  969. #define WM8904_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */
  970. #define WM8904_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */
  971. /*
  972. * R98 (0x62) - Charge Pump 0
  973. */
  974. #define WM8904_CP_ENA 0x0001 /* CP_ENA */
  975. #define WM8904_CP_ENA_MASK 0x0001 /* CP_ENA */
  976. #define WM8904_CP_ENA_SHIFT 0 /* CP_ENA */
  977. #define WM8904_CP_ENA_WIDTH 1 /* CP_ENA */
  978. /*
  979. * R104 (0x68) - Class W 0
  980. */
  981. #define WM8904_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
  982. #define WM8904_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
  983. #define WM8904_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
  984. #define WM8904_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
  985. /*
  986. * R108 (0x6C) - Write Sequencer 0
  987. */
  988. #define WM8904_WSEQ_ENA 0x0100 /* WSEQ_ENA */
  989. #define WM8904_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */
  990. #define WM8904_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */
  991. #define WM8904_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  992. #define WM8904_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */
  993. #define WM8904_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */
  994. #define WM8904_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */
  995. /*
  996. * R109 (0x6D) - Write Sequencer 1
  997. */
  998. #define WM8904_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */
  999. #define WM8904_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */
  1000. #define WM8904_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */
  1001. #define WM8904_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */
  1002. #define WM8904_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */
  1003. #define WM8904_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */
  1004. #define WM8904_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
  1005. #define WM8904_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
  1006. #define WM8904_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
  1007. /*
  1008. * R110 (0x6E) - Write Sequencer 2
  1009. */
  1010. #define WM8904_WSEQ_EOS 0x4000 /* WSEQ_EOS */
  1011. #define WM8904_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */
  1012. #define WM8904_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */
  1013. #define WM8904_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */
  1014. #define WM8904_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */
  1015. #define WM8904_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */
  1016. #define WM8904_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */
  1017. #define WM8904_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
  1018. #define WM8904_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
  1019. #define WM8904_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
  1020. /*
  1021. * R111 (0x6F) - Write Sequencer 3
  1022. */
  1023. #define WM8904_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
  1024. #define WM8904_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
  1025. #define WM8904_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
  1026. #define WM8904_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  1027. #define WM8904_WSEQ_START 0x0100 /* WSEQ_START */
  1028. #define WM8904_WSEQ_START_MASK 0x0100 /* WSEQ_START */
  1029. #define WM8904_WSEQ_START_SHIFT 8 /* WSEQ_START */
  1030. #define WM8904_WSEQ_START_WIDTH 1 /* WSEQ_START */
  1031. #define WM8904_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
  1032. #define WM8904_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
  1033. #define WM8904_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
  1034. /*
  1035. * R112 (0x70) - Write Sequencer 4
  1036. */
  1037. #define WM8904_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */
  1038. #define WM8904_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */
  1039. #define WM8904_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */
  1040. #define WM8904_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
  1041. #define WM8904_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
  1042. #define WM8904_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
  1043. #define WM8904_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  1044. /*
  1045. * R116 (0x74) - FLL Control 1
  1046. */
  1047. #define WM8904_FLL_FRACN_ENA 0x0004 /* FLL_FRACN_ENA */
  1048. #define WM8904_FLL_FRACN_ENA_MASK 0x0004 /* FLL_FRACN_ENA */
  1049. #define WM8904_FLL_FRACN_ENA_SHIFT 2 /* FLL_FRACN_ENA */
  1050. #define WM8904_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */
  1051. #define WM8904_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
  1052. #define WM8904_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
  1053. #define WM8904_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
  1054. #define WM8904_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
  1055. #define WM8904_FLL_ENA 0x0001 /* FLL_ENA */
  1056. #define WM8904_FLL_ENA_MASK 0x0001 /* FLL_ENA */
  1057. #define WM8904_FLL_ENA_SHIFT 0 /* FLL_ENA */
  1058. #define WM8904_FLL_ENA_WIDTH 1 /* FLL_ENA */
  1059. /*
  1060. * R117 (0x75) - FLL Control 2
  1061. */
  1062. #define WM8904_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
  1063. #define WM8904_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
  1064. #define WM8904_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
  1065. #define WM8904_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
  1066. #define WM8904_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
  1067. #define WM8904_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
  1068. #define WM8904_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
  1069. #define WM8904_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
  1070. #define WM8904_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
  1071. /*
  1072. * R118 (0x76) - FLL Control 3
  1073. */
  1074. #define WM8904_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
  1075. #define WM8904_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
  1076. #define WM8904_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
  1077. /*
  1078. * R119 (0x77) - FLL Control 4
  1079. */
  1080. #define WM8904_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
  1081. #define WM8904_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
  1082. #define WM8904_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
  1083. #define WM8904_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
  1084. #define WM8904_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
  1085. #define WM8904_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
  1086. /*
  1087. * R120 (0x78) - FLL Control 5
  1088. */
  1089. #define WM8904_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
  1090. #define WM8904_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
  1091. #define WM8904_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
  1092. #define WM8904_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */
  1093. #define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
  1094. #define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
  1095. /*
  1096. * R126 (0x7E) - Digital Pulls
  1097. */
  1098. #define WM8904_MCLK_PU 0x0080 /* MCLK_PU */
  1099. #define WM8904_MCLK_PU_MASK 0x0080 /* MCLK_PU */
  1100. #define WM8904_MCLK_PU_SHIFT 7 /* MCLK_PU */
  1101. #define WM8904_MCLK_PU_WIDTH 1 /* MCLK_PU */
  1102. #define WM8904_MCLK_PD 0x0040 /* MCLK_PD */
  1103. #define WM8904_MCLK_PD_MASK 0x0040 /* MCLK_PD */
  1104. #define WM8904_MCLK_PD_SHIFT 6 /* MCLK_PD */
  1105. #define WM8904_MCLK_PD_WIDTH 1 /* MCLK_PD */
  1106. #define WM8904_DACDAT_PU 0x0020 /* DACDAT_PU */
  1107. #define WM8904_DACDAT_PU_MASK 0x0020 /* DACDAT_PU */
  1108. #define WM8904_DACDAT_PU_SHIFT 5 /* DACDAT_PU */
  1109. #define WM8904_DACDAT_PU_WIDTH 1 /* DACDAT_PU */
  1110. #define WM8904_DACDAT_PD 0x0010 /* DACDAT_PD */
  1111. #define WM8904_DACDAT_PD_MASK 0x0010 /* DACDAT_PD */
  1112. #define WM8904_DACDAT_PD_SHIFT 4 /* DACDAT_PD */
  1113. #define WM8904_DACDAT_PD_WIDTH 1 /* DACDAT_PD */
  1114. #define WM8904_LRCLK_PU 0x0008 /* LRCLK_PU */
  1115. #define WM8904_LRCLK_PU_MASK 0x0008 /* LRCLK_PU */
  1116. #define WM8904_LRCLK_PU_SHIFT 3 /* LRCLK_PU */
  1117. #define WM8904_LRCLK_PU_WIDTH 1 /* LRCLK_PU */
  1118. #define WM8904_LRCLK_PD 0x0004 /* LRCLK_PD */
  1119. #define WM8904_LRCLK_PD_MASK 0x0004 /* LRCLK_PD */
  1120. #define WM8904_LRCLK_PD_SHIFT 2 /* LRCLK_PD */
  1121. #define WM8904_LRCLK_PD_WIDTH 1 /* LRCLK_PD */
  1122. #define WM8904_BCLK_PU 0x0002 /* BCLK_PU */
  1123. #define WM8904_BCLK_PU_MASK 0x0002 /* BCLK_PU */
  1124. #define WM8904_BCLK_PU_SHIFT 1 /* BCLK_PU */
  1125. #define WM8904_BCLK_PU_WIDTH 1 /* BCLK_PU */
  1126. #define WM8904_BCLK_PD 0x0001 /* BCLK_PD */
  1127. #define WM8904_BCLK_PD_MASK 0x0001 /* BCLK_PD */
  1128. #define WM8904_BCLK_PD_SHIFT 0 /* BCLK_PD */
  1129. #define WM8904_BCLK_PD_WIDTH 1 /* BCLK_PD */
  1130. /*
  1131. * R127 (0x7F) - Interrupt Status
  1132. */
  1133. #define WM8904_IRQ 0x0400 /* IRQ */
  1134. #define WM8904_IRQ_MASK 0x0400 /* IRQ */
  1135. #define WM8904_IRQ_SHIFT 10 /* IRQ */
  1136. #define WM8904_IRQ_WIDTH 1 /* IRQ */
  1137. #define WM8904_GPIO_BCLK_EINT 0x0200 /* GPIO_BCLK_EINT */
  1138. #define WM8904_GPIO_BCLK_EINT_MASK 0x0200 /* GPIO_BCLK_EINT */
  1139. #define WM8904_GPIO_BCLK_EINT_SHIFT 9 /* GPIO_BCLK_EINT */
  1140. #define WM8904_GPIO_BCLK_EINT_WIDTH 1 /* GPIO_BCLK_EINT */
  1141. #define WM8904_WSEQ_EINT 0x0100 /* WSEQ_EINT */
  1142. #define WM8904_WSEQ_EINT_MASK 0x0100 /* WSEQ_EINT */
  1143. #define WM8904_WSEQ_EINT_SHIFT 8 /* WSEQ_EINT */
  1144. #define WM8904_WSEQ_EINT_WIDTH 1 /* WSEQ_EINT */
  1145. #define WM8904_GPIO3_EINT 0x0080 /* GPIO3_EINT */
  1146. #define WM8904_GPIO3_EINT_MASK 0x0080 /* GPIO3_EINT */
  1147. #define WM8904_GPIO3_EINT_SHIFT 7 /* GPIO3_EINT */
  1148. #define WM8904_GPIO3_EINT_WIDTH 1 /* GPIO3_EINT */
  1149. #define WM8904_GPIO2_EINT 0x0040 /* GPIO2_EINT */
  1150. #define WM8904_GPIO2_EINT_MASK 0x0040 /* GPIO2_EINT */
  1151. #define WM8904_GPIO2_EINT_SHIFT 6 /* GPIO2_EINT */
  1152. #define WM8904_GPIO2_EINT_WIDTH 1 /* GPIO2_EINT */
  1153. #define WM8904_GPIO1_EINT 0x0020 /* GPIO1_EINT */
  1154. #define WM8904_GPIO1_EINT_MASK 0x0020 /* GPIO1_EINT */
  1155. #define WM8904_GPIO1_EINT_SHIFT 5 /* GPIO1_EINT */
  1156. #define WM8904_GPIO1_EINT_WIDTH 1 /* GPIO1_EINT */
  1157. #define WM8904_GPI8_EINT 0x0010 /* GPI8_EINT */
  1158. #define WM8904_GPI8_EINT_MASK 0x0010 /* GPI8_EINT */
  1159. #define WM8904_GPI8_EINT_SHIFT 4 /* GPI8_EINT */
  1160. #define WM8904_GPI8_EINT_WIDTH 1 /* GPI8_EINT */
  1161. #define WM8904_GPI7_EINT 0x0008 /* GPI7_EINT */
  1162. #define WM8904_GPI7_EINT_MASK 0x0008 /* GPI7_EINT */
  1163. #define WM8904_GPI7_EINT_SHIFT 3 /* GPI7_EINT */
  1164. #define WM8904_GPI7_EINT_WIDTH 1 /* GPI7_EINT */
  1165. #define WM8904_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */
  1166. #define WM8904_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */
  1167. #define WM8904_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */
  1168. #define WM8904_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */
  1169. #define WM8904_MIC_SHRT_EINT 0x0002 /* MIC_SHRT_EINT */
  1170. #define WM8904_MIC_SHRT_EINT_MASK 0x0002 /* MIC_SHRT_EINT */
  1171. #define WM8904_MIC_SHRT_EINT_SHIFT 1 /* MIC_SHRT_EINT */
  1172. #define WM8904_MIC_SHRT_EINT_WIDTH 1 /* MIC_SHRT_EINT */
  1173. #define WM8904_MIC_DET_EINT 0x0001 /* MIC_DET_EINT */
  1174. #define WM8904_MIC_DET_EINT_MASK 0x0001 /* MIC_DET_EINT */
  1175. #define WM8904_MIC_DET_EINT_SHIFT 0 /* MIC_DET_EINT */
  1176. #define WM8904_MIC_DET_EINT_WIDTH 1 /* MIC_DET_EINT */
  1177. /*
  1178. * R128 (0x80) - Interrupt Status Mask
  1179. */
  1180. #define WM8904_IM_GPIO_BCLK_EINT 0x0200 /* IM_GPIO_BCLK_EINT */
  1181. #define WM8904_IM_GPIO_BCLK_EINT_MASK 0x0200 /* IM_GPIO_BCLK_EINT */
  1182. #define WM8904_IM_GPIO_BCLK_EINT_SHIFT 9 /* IM_GPIO_BCLK_EINT */
  1183. #define WM8904_IM_GPIO_BCLK_EINT_WIDTH 1 /* IM_GPIO_BCLK_EINT */
  1184. #define WM8904_IM_WSEQ_EINT 0x0100 /* IM_WSEQ_EINT */
  1185. #define WM8904_IM_WSEQ_EINT_MASK 0x0100 /* IM_WSEQ_EINT */
  1186. #define WM8904_IM_WSEQ_EINT_SHIFT 8 /* IM_WSEQ_EINT */
  1187. #define WM8904_IM_WSEQ_EINT_WIDTH 1 /* IM_WSEQ_EINT */
  1188. #define WM8904_IM_GPIO3_EINT 0x0080 /* IM_GPIO3_EINT */
  1189. #define WM8904_IM_GPIO3_EINT_MASK 0x0080 /* IM_GPIO3_EINT */
  1190. #define WM8904_IM_GPIO3_EINT_SHIFT 7 /* IM_GPIO3_EINT */
  1191. #define WM8904_IM_GPIO3_EINT_WIDTH 1 /* IM_GPIO3_EINT */
  1192. #define WM8904_IM_GPIO2_EINT 0x0040 /* IM_GPIO2_EINT */
  1193. #define WM8904_IM_GPIO2_EINT_MASK 0x0040 /* IM_GPIO2_EINT */
  1194. #define WM8904_IM_GPIO2_EINT_SHIFT 6 /* IM_GPIO2_EINT */
  1195. #define WM8904_IM_GPIO2_EINT_WIDTH 1 /* IM_GPIO2_EINT */
  1196. #define WM8904_IM_GPIO1_EINT 0x0020 /* IM_GPIO1_EINT */
  1197. #define WM8904_IM_GPIO1_EINT_MASK 0x0020 /* IM_GPIO1_EINT */
  1198. #define WM8904_IM_GPIO1_EINT_SHIFT 5 /* IM_GPIO1_EINT */
  1199. #define WM8904_IM_GPIO1_EINT_WIDTH 1 /* IM_GPIO1_EINT */
  1200. #define WM8904_IM_GPI8_EINT 0x0010 /* IM_GPI8_EINT */
  1201. #define WM8904_IM_GPI8_EINT_MASK 0x0010 /* IM_GPI8_EINT */
  1202. #define WM8904_IM_GPI8_EINT_SHIFT 4 /* IM_GPI8_EINT */
  1203. #define WM8904_IM_GPI8_EINT_WIDTH 1 /* IM_GPI8_EINT */
  1204. #define WM8904_IM_GPI7_EINT 0x0008 /* IM_GPI7_EINT */
  1205. #define WM8904_IM_GPI7_EINT_MASK 0x0008 /* IM_GPI7_EINT */
  1206. #define WM8904_IM_GPI7_EINT_SHIFT 3 /* IM_GPI7_EINT */
  1207. #define WM8904_IM_GPI7_EINT_WIDTH 1 /* IM_GPI7_EINT */
  1208. #define WM8904_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */
  1209. #define WM8904_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */
  1210. #define WM8904_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */
  1211. #define WM8904_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */
  1212. #define WM8904_IM_MIC_SHRT_EINT 0x0002 /* IM_MIC_SHRT_EINT */
  1213. #define WM8904_IM_MIC_SHRT_EINT_MASK 0x0002 /* IM_MIC_SHRT_EINT */
  1214. #define WM8904_IM_MIC_SHRT_EINT_SHIFT 1 /* IM_MIC_SHRT_EINT */
  1215. #define WM8904_IM_MIC_SHRT_EINT_WIDTH 1 /* IM_MIC_SHRT_EINT */
  1216. #define WM8904_IM_MIC_DET_EINT 0x0001 /* IM_MIC_DET_EINT */
  1217. #define WM8904_IM_MIC_DET_EINT_MASK 0x0001 /* IM_MIC_DET_EINT */
  1218. #define WM8904_IM_MIC_DET_EINT_SHIFT 0 /* IM_MIC_DET_EINT */
  1219. #define WM8904_IM_MIC_DET_EINT_WIDTH 1 /* IM_MIC_DET_EINT */
  1220. /*
  1221. * R129 (0x81) - Interrupt Polarity
  1222. */
  1223. #define WM8904_GPIO_BCLK_EINT_POL 0x0200 /* GPIO_BCLK_EINT_POL */
  1224. #define WM8904_GPIO_BCLK_EINT_POL_MASK 0x0200 /* GPIO_BCLK_EINT_POL */
  1225. #define WM8904_GPIO_BCLK_EINT_POL_SHIFT 9 /* GPIO_BCLK_EINT_POL */
  1226. #define WM8904_GPIO_BCLK_EINT_POL_WIDTH 1 /* GPIO_BCLK_EINT_POL */
  1227. #define WM8904_WSEQ_EINT_POL 0x0100 /* WSEQ_EINT_POL */
  1228. #define WM8904_WSEQ_EINT_POL_MASK 0x0100 /* WSEQ_EINT_POL */
  1229. #define WM8904_WSEQ_EINT_POL_SHIFT 8 /* WSEQ_EINT_POL */
  1230. #define WM8904_WSEQ_EINT_POL_WIDTH 1 /* WSEQ_EINT_POL */
  1231. #define WM8904_GPIO3_EINT_POL 0x0080 /* GPIO3_EINT_POL */
  1232. #define WM8904_GPIO3_EINT_POL_MASK 0x0080 /* GPIO3_EINT_POL */
  1233. #define WM8904_GPIO3_EINT_POL_SHIFT 7 /* GPIO3_EINT_POL */
  1234. #define WM8904_GPIO3_EINT_POL_WIDTH 1 /* GPIO3_EINT_POL */
  1235. #define WM8904_GPIO2_EINT_POL 0x0040 /* GPIO2_EINT_POL */
  1236. #define WM8904_GPIO2_EINT_POL_MASK 0x0040 /* GPIO2_EINT_POL */
  1237. #define WM8904_GPIO2_EINT_POL_SHIFT 6 /* GPIO2_EINT_POL */
  1238. #define WM8904_GPIO2_EINT_POL_WIDTH 1 /* GPIO2_EINT_POL */
  1239. #define WM8904_GPIO1_EINT_POL 0x0020 /* GPIO1_EINT_POL */
  1240. #define WM8904_GPIO1_EINT_POL_MASK 0x0020 /* GPIO1_EINT_POL */
  1241. #define WM8904_GPIO1_EINT_POL_SHIFT 5 /* GPIO1_EINT_POL */
  1242. #define WM8904_GPIO1_EINT_POL_WIDTH 1 /* GPIO1_EINT_POL */
  1243. #define WM8904_GPI8_EINT_POL 0x0010 /* GPI8_EINT_POL */
  1244. #define WM8904_GPI8_EINT_POL_MASK 0x0010 /* GPI8_EINT_POL */
  1245. #define WM8904_GPI8_EINT_POL_SHIFT 4 /* GPI8_EINT_POL */
  1246. #define WM8904_GPI8_EINT_POL_WIDTH 1 /* GPI8_EINT_POL */
  1247. #define WM8904_GPI7_EINT_POL 0x0008 /* GPI7_EINT_POL */
  1248. #define WM8904_GPI7_EINT_POL_MASK 0x0008 /* GPI7_EINT_POL */
  1249. #define WM8904_GPI7_EINT_POL_SHIFT 3 /* GPI7_EINT_POL */
  1250. #define WM8904_GPI7_EINT_POL_WIDTH 1 /* GPI7_EINT_POL */
  1251. #define WM8904_FLL_LOCK_EINT_POL 0x0004 /* FLL_LOCK_EINT_POL */
  1252. #define WM8904_FLL_LOCK_EINT_POL_MASK 0x0004 /* FLL_LOCK_EINT_POL */
  1253. #define WM8904_FLL_LOCK_EINT_POL_SHIFT 2 /* FLL_LOCK_EINT_POL */
  1254. #define WM8904_FLL_LOCK_EINT_POL_WIDTH 1 /* FLL_LOCK_EINT_POL */
  1255. #define WM8904_MIC_SHRT_EINT_POL 0x0002 /* MIC_SHRT_EINT_POL */
  1256. #define WM8904_MIC_SHRT_EINT_POL_MASK 0x0002 /* MIC_SHRT_EINT_POL */
  1257. #define WM8904_MIC_SHRT_EINT_POL_SHIFT 1 /* MIC_SHRT_EINT_POL */
  1258. #define WM8904_MIC_SHRT_EINT_POL_WIDTH 1 /* MIC_SHRT_EINT_POL */
  1259. #define WM8904_MIC_DET_EINT_POL 0x0001 /* MIC_DET_EINT_POL */
  1260. #define WM8904_MIC_DET_EINT_POL_MASK 0x0001 /* MIC_DET_EINT_POL */
  1261. #define WM8904_MIC_DET_EINT_POL_SHIFT 0 /* MIC_DET_EINT_POL */
  1262. #define WM8904_MIC_DET_EINT_POL_WIDTH 1 /* MIC_DET_EINT_POL */
  1263. /*
  1264. * R130 (0x82) - Interrupt Debounce
  1265. */
  1266. #define WM8904_GPIO_BCLK_EINT_DB 0x0200 /* GPIO_BCLK_EINT_DB */
  1267. #define WM8904_GPIO_BCLK_EINT_DB_MASK 0x0200 /* GPIO_BCLK_EINT_DB */
  1268. #define WM8904_GPIO_BCLK_EINT_DB_SHIFT 9 /* GPIO_BCLK_EINT_DB */
  1269. #define WM8904_GPIO_BCLK_EINT_DB_WIDTH 1 /* GPIO_BCLK_EINT_DB */
  1270. #define WM8904_WSEQ_EINT_DB 0x0100 /* WSEQ_EINT_DB */
  1271. #define WM8904_WSEQ_EINT_DB_MASK 0x0100 /* WSEQ_EINT_DB */
  1272. #define WM8904_WSEQ_EINT_DB_SHIFT 8 /* WSEQ_EINT_DB */
  1273. #define WM8904_WSEQ_EINT_DB_WIDTH 1 /* WSEQ_EINT_DB */
  1274. #define WM8904_GPIO3_EINT_DB 0x0080 /* GPIO3_EINT_DB */
  1275. #define WM8904_GPIO3_EINT_DB_MASK 0x0080 /* GPIO3_EINT_DB */
  1276. #define WM8904_GPIO3_EINT_DB_SHIFT 7 /* GPIO3_EINT_DB */
  1277. #define WM8904_GPIO3_EINT_DB_WIDTH 1 /* GPIO3_EINT_DB */
  1278. #define WM8904_GPIO2_EINT_DB 0x0040 /* GPIO2_EINT_DB */
  1279. #define WM8904_GPIO2_EINT_DB_MASK 0x0040 /* GPIO2_EINT_DB */
  1280. #define WM8904_GPIO2_EINT_DB_SHIFT 6 /* GPIO2_EINT_DB */
  1281. #define WM8904_GPIO2_EINT_DB_WIDTH 1 /* GPIO2_EINT_DB */
  1282. #define WM8904_GPIO1_EINT_DB 0x0020 /* GPIO1_EINT_DB */
  1283. #define WM8904_GPIO1_EINT_DB_MASK 0x0020 /* GPIO1_EINT_DB */
  1284. #define WM8904_GPIO1_EINT_DB_SHIFT 5 /* GPIO1_EINT_DB */
  1285. #define WM8904_GPIO1_EINT_DB_WIDTH 1 /* GPIO1_EINT_DB */
  1286. #define WM8904_GPI8_EINT_DB 0x0010 /* GPI8_EINT_DB */
  1287. #define WM8904_GPI8_EINT_DB_MASK 0x0010 /* GPI8_EINT_DB */
  1288. #define WM8904_GPI8_EINT_DB_SHIFT 4 /* GPI8_EINT_DB */
  1289. #define WM8904_GPI8_EINT_DB_WIDTH 1 /* GPI8_EINT_DB */
  1290. #define WM8904_GPI7_EINT_DB 0x0008 /* GPI7_EINT_DB */
  1291. #define WM8904_GPI7_EINT_DB_MASK 0x0008 /* GPI7_EINT_DB */
  1292. #define WM8904_GPI7_EINT_DB_SHIFT 3 /* GPI7_EINT_DB */
  1293. #define WM8904_GPI7_EINT_DB_WIDTH 1 /* GPI7_EINT_DB */
  1294. #define WM8904_FLL_LOCK_EINT_DB 0x0004 /* FLL_LOCK_EINT_DB */
  1295. #define WM8904_FLL_LOCK_EINT_DB_MASK 0x0004 /* FLL_LOCK_EINT_DB */
  1296. #define WM8904_FLL_LOCK_EINT_DB_SHIFT 2 /* FLL_LOCK_EINT_DB */
  1297. #define WM8904_FLL_LOCK_EINT_DB_WIDTH 1 /* FLL_LOCK_EINT_DB */
  1298. #define WM8904_MIC_SHRT_EINT_DB 0x0002 /* MIC_SHRT_EINT_DB */
  1299. #define WM8904_MIC_SHRT_EINT_DB_MASK 0x0002 /* MIC_SHRT_EINT_DB */
  1300. #define WM8904_MIC_SHRT_EINT_DB_SHIFT 1 /* MIC_SHRT_EINT_DB */
  1301. #define WM8904_MIC_SHRT_EINT_DB_WIDTH 1 /* MIC_SHRT_EINT_DB */
  1302. #define WM8904_MIC_DET_EINT_DB 0x0001 /* MIC_DET_EINT_DB */
  1303. #define WM8904_MIC_DET_EINT_DB_MASK 0x0001 /* MIC_DET_EINT_DB */
  1304. #define WM8904_MIC_DET_EINT_DB_SHIFT 0 /* MIC_DET_EINT_DB */
  1305. #define WM8904_MIC_DET_EINT_DB_WIDTH 1 /* MIC_DET_EINT_DB */
  1306. /*
  1307. * R134 (0x86) - EQ1
  1308. */
  1309. #define WM8904_EQ_ENA 0x0001 /* EQ_ENA */
  1310. #define WM8904_EQ_ENA_MASK 0x0001 /* EQ_ENA */
  1311. #define WM8904_EQ_ENA_SHIFT 0 /* EQ_ENA */
  1312. #define WM8904_EQ_ENA_WIDTH 1 /* EQ_ENA */
  1313. /*
  1314. * R135 (0x87) - EQ2
  1315. */
  1316. #define WM8904_EQ_B1_GAIN_MASK 0x001F /* EQ_B1_GAIN - [4:0] */
  1317. #define WM8904_EQ_B1_GAIN_SHIFT 0 /* EQ_B1_GAIN - [4:0] */
  1318. #define WM8904_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [4:0] */
  1319. /*
  1320. * R136 (0x88) - EQ3
  1321. */
  1322. #define WM8904_EQ_B2_GAIN_MASK 0x001F /* EQ_B2_GAIN - [4:0] */
  1323. #define WM8904_EQ_B2_GAIN_SHIFT 0 /* EQ_B2_GAIN - [4:0] */
  1324. #define WM8904_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [4:0] */
  1325. /*
  1326. * R137 (0x89) - EQ4
  1327. */
  1328. #define WM8904_EQ_B3_GAIN_MASK 0x001F /* EQ_B3_GAIN - [4:0] */
  1329. #define WM8904_EQ_B3_GAIN_SHIFT 0 /* EQ_B3_GAIN - [4:0] */
  1330. #define WM8904_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [4:0] */
  1331. /*
  1332. * R138 (0x8A) - EQ5
  1333. */
  1334. #define WM8904_EQ_B4_GAIN_MASK 0x001F /* EQ_B4_GAIN - [4:0] */
  1335. #define WM8904_EQ_B4_GAIN_SHIFT 0 /* EQ_B4_GAIN - [4:0] */
  1336. #define WM8904_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [4:0] */
  1337. /*
  1338. * R139 (0x8B) - EQ6
  1339. */
  1340. #define WM8904_EQ_B5_GAIN_MASK 0x001F /* EQ_B5_GAIN - [4:0] */
  1341. #define WM8904_EQ_B5_GAIN_SHIFT 0 /* EQ_B5_GAIN - [4:0] */
  1342. #define WM8904_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [4:0] */
  1343. /*
  1344. * R140 (0x8C) - EQ7
  1345. */
  1346. #define WM8904_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
  1347. #define WM8904_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
  1348. #define WM8904_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
  1349. /*
  1350. * R141 (0x8D) - EQ8
  1351. */
  1352. #define WM8904_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
  1353. #define WM8904_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
  1354. #define WM8904_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
  1355. /*
  1356. * R142 (0x8E) - EQ9
  1357. */
  1358. #define WM8904_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
  1359. #define WM8904_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
  1360. #define WM8904_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
  1361. /*
  1362. * R143 (0x8F) - EQ10
  1363. */
  1364. #define WM8904_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
  1365. #define WM8904_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
  1366. #define WM8904_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
  1367. /*
  1368. * R144 (0x90) - EQ11
  1369. */
  1370. #define WM8904_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
  1371. #define WM8904_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
  1372. #define WM8904_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
  1373. /*
  1374. * R145 (0x91) - EQ12
  1375. */
  1376. #define WM8904_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
  1377. #define WM8904_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
  1378. #define WM8904_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
  1379. /*
  1380. * R146 (0x92) - EQ13
  1381. */
  1382. #define WM8904_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
  1383. #define WM8904_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
  1384. #define WM8904_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
  1385. /*
  1386. * R147 (0x93) - EQ14
  1387. */
  1388. #define WM8904_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
  1389. #define WM8904_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
  1390. #define WM8904_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
  1391. /*
  1392. * R148 (0x94) - EQ15
  1393. */
  1394. #define WM8904_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
  1395. #define WM8904_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
  1396. #define WM8904_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
  1397. /*
  1398. * R149 (0x95) - EQ16
  1399. */
  1400. #define WM8904_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
  1401. #define WM8904_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
  1402. #define WM8904_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
  1403. /*
  1404. * R150 (0x96) - EQ17
  1405. */
  1406. #define WM8904_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
  1407. #define WM8904_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
  1408. #define WM8904_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
  1409. /*
  1410. * R151 (0x97) - EQ18
  1411. */
  1412. #define WM8904_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
  1413. #define WM8904_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
  1414. #define WM8904_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
  1415. /*
  1416. * R152 (0x98) - EQ19
  1417. */
  1418. #define WM8904_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
  1419. #define WM8904_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
  1420. #define WM8904_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
  1421. /*
  1422. * R153 (0x99) - EQ20
  1423. */
  1424. #define WM8904_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
  1425. #define WM8904_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
  1426. #define WM8904_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
  1427. /*
  1428. * R154 (0x9A) - EQ21
  1429. */
  1430. #define WM8904_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
  1431. #define WM8904_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
  1432. #define WM8904_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
  1433. /*
  1434. * R155 (0x9B) - EQ22
  1435. */
  1436. #define WM8904_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
  1437. #define WM8904_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
  1438. #define WM8904_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
  1439. /*
  1440. * R156 (0x9C) - EQ23
  1441. */
  1442. #define WM8904_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
  1443. #define WM8904_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
  1444. #define WM8904_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
  1445. /*
  1446. * R157 (0x9D) - EQ24
  1447. */
  1448. #define WM8904_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
  1449. #define WM8904_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
  1450. #define WM8904_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
  1451. /*
  1452. * R161 (0xA1) - Control Interface Test 1
  1453. */
  1454. #define WM8904_USER_KEY 0x0002 /* USER_KEY */
  1455. #define WM8904_USER_KEY_MASK 0x0002 /* USER_KEY */
  1456. #define WM8904_USER_KEY_SHIFT 1 /* USER_KEY */
  1457. #define WM8904_USER_KEY_WIDTH 1 /* USER_KEY */
  1458. /*
  1459. * R198 (0xC6) - ADC Test 0
  1460. */
  1461. #define WM8904_ADC_128_OSR_TST_MODE 0x0004 /* ADC_128_OSR_TST_MODE */
  1462. #define WM8904_ADC_128_OSR_TST_MODE_SHIFT 2 /* ADC_128_OSR_TST_MODE */
  1463. #define WM8904_ADC_128_OSR_TST_MODE_WIDTH 1 /* ADC_128_OSR_TST_MODE */
  1464. #define WM8904_ADC_BIASX1P5 0x0001 /* ADC_BIASX1P5 */
  1465. #define WM8904_ADC_BIASX1P5_SHIFT 0 /* ADC_BIASX1P5 */
  1466. #define WM8904_ADC_BIASX1P5_WIDTH 1 /* ADC_BIASX1P5 */
  1467. /*
  1468. * R204 (0xCC) - Analogue Output Bias 0
  1469. */
  1470. #define WM8904_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */
  1471. #define WM8904_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */
  1472. #define WM8904_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */
  1473. /*
  1474. * R247 (0xF7) - FLL NCO Test 0
  1475. */
  1476. #define WM8904_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */
  1477. #define WM8904_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */
  1478. #define WM8904_FLL_FRC_NCO_SHIFT 0 /* FLL_FRC_NCO */
  1479. #define WM8904_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */
  1480. /*
  1481. * R248 (0xF8) - FLL NCO Test 1
  1482. */
  1483. #define WM8904_FLL_FRC_NCO_VAL_MASK 0x003F /* FLL_FRC_NCO_VAL - [5:0] */
  1484. #define WM8904_FLL_FRC_NCO_VAL_SHIFT 0 /* FLL_FRC_NCO_VAL - [5:0] */
  1485. #define WM8904_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [5:0] */
  1486. #endif