wm8903.h 70 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * wm8903.h - WM8903 audio codec interface
  4. *
  5. * Copyright 2008 Wolfson Microelectronics PLC.
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. */
  8. #ifndef _WM8903_H
  9. #define _WM8903_H
  10. #include <linux/i2c.h>
  11. extern int wm8903_mic_detect(struct snd_soc_component *component,
  12. struct snd_soc_jack *jack,
  13. int det, int shrt);
  14. /*
  15. * Register values.
  16. */
  17. #define WM8903_SW_RESET_AND_ID 0x00
  18. #define WM8903_REVISION_NUMBER 0x01
  19. #define WM8903_BIAS_CONTROL_0 0x04
  20. #define WM8903_VMID_CONTROL_0 0x05
  21. #define WM8903_MIC_BIAS_CONTROL_0 0x06
  22. #define WM8903_ANALOGUE_DAC_0 0x08
  23. #define WM8903_ANALOGUE_ADC_0 0x0A
  24. #define WM8903_POWER_MANAGEMENT_0 0x0C
  25. #define WM8903_POWER_MANAGEMENT_1 0x0D
  26. #define WM8903_POWER_MANAGEMENT_2 0x0E
  27. #define WM8903_POWER_MANAGEMENT_3 0x0F
  28. #define WM8903_POWER_MANAGEMENT_4 0x10
  29. #define WM8903_POWER_MANAGEMENT_5 0x11
  30. #define WM8903_POWER_MANAGEMENT_6 0x12
  31. #define WM8903_CLOCK_RATES_0 0x14
  32. #define WM8903_CLOCK_RATES_1 0x15
  33. #define WM8903_CLOCK_RATES_2 0x16
  34. #define WM8903_AUDIO_INTERFACE_0 0x18
  35. #define WM8903_AUDIO_INTERFACE_1 0x19
  36. #define WM8903_AUDIO_INTERFACE_2 0x1A
  37. #define WM8903_AUDIO_INTERFACE_3 0x1B
  38. #define WM8903_DAC_DIGITAL_VOLUME_LEFT 0x1E
  39. #define WM8903_DAC_DIGITAL_VOLUME_RIGHT 0x1F
  40. #define WM8903_DAC_DIGITAL_0 0x20
  41. #define WM8903_DAC_DIGITAL_1 0x21
  42. #define WM8903_ADC_DIGITAL_VOLUME_LEFT 0x24
  43. #define WM8903_ADC_DIGITAL_VOLUME_RIGHT 0x25
  44. #define WM8903_ADC_DIGITAL_0 0x26
  45. #define WM8903_DIGITAL_MICROPHONE_0 0x27
  46. #define WM8903_DRC_0 0x28
  47. #define WM8903_DRC_1 0x29
  48. #define WM8903_DRC_2 0x2A
  49. #define WM8903_DRC_3 0x2B
  50. #define WM8903_ANALOGUE_LEFT_INPUT_0 0x2C
  51. #define WM8903_ANALOGUE_RIGHT_INPUT_0 0x2D
  52. #define WM8903_ANALOGUE_LEFT_INPUT_1 0x2E
  53. #define WM8903_ANALOGUE_RIGHT_INPUT_1 0x2F
  54. #define WM8903_ANALOGUE_LEFT_MIX_0 0x32
  55. #define WM8903_ANALOGUE_RIGHT_MIX_0 0x33
  56. #define WM8903_ANALOGUE_SPK_MIX_LEFT_0 0x34
  57. #define WM8903_ANALOGUE_SPK_MIX_LEFT_1 0x35
  58. #define WM8903_ANALOGUE_SPK_MIX_RIGHT_0 0x36
  59. #define WM8903_ANALOGUE_SPK_MIX_RIGHT_1 0x37
  60. #define WM8903_ANALOGUE_OUT1_LEFT 0x39
  61. #define WM8903_ANALOGUE_OUT1_RIGHT 0x3A
  62. #define WM8903_ANALOGUE_OUT2_LEFT 0x3B
  63. #define WM8903_ANALOGUE_OUT2_RIGHT 0x3C
  64. #define WM8903_ANALOGUE_OUT3_LEFT 0x3E
  65. #define WM8903_ANALOGUE_OUT3_RIGHT 0x3F
  66. #define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0 0x41
  67. #define WM8903_DC_SERVO_0 0x43
  68. #define WM8903_DC_SERVO_2 0x45
  69. #define WM8903_DC_SERVO_4 0x47
  70. #define WM8903_DC_SERVO_5 0x48
  71. #define WM8903_DC_SERVO_6 0x49
  72. #define WM8903_DC_SERVO_7 0x4A
  73. #define WM8903_DC_SERVO_READBACK_1 0x51
  74. #define WM8903_DC_SERVO_READBACK_2 0x52
  75. #define WM8903_DC_SERVO_READBACK_3 0x53
  76. #define WM8903_DC_SERVO_READBACK_4 0x54
  77. #define WM8903_ANALOGUE_HP_0 0x5A
  78. #define WM8903_ANALOGUE_LINEOUT_0 0x5E
  79. #define WM8903_CHARGE_PUMP_0 0x62
  80. #define WM8903_CLASS_W_0 0x68
  81. #define WM8903_WRITE_SEQUENCER_0 0x6C
  82. #define WM8903_WRITE_SEQUENCER_1 0x6D
  83. #define WM8903_WRITE_SEQUENCER_2 0x6E
  84. #define WM8903_WRITE_SEQUENCER_3 0x6F
  85. #define WM8903_WRITE_SEQUENCER_4 0x70
  86. #define WM8903_CONTROL_INTERFACE 0x72
  87. #define WM8903_GPIO_CONTROL_1 0x74
  88. #define WM8903_GPIO_CONTROL_2 0x75
  89. #define WM8903_GPIO_CONTROL_3 0x76
  90. #define WM8903_GPIO_CONTROL_4 0x77
  91. #define WM8903_GPIO_CONTROL_5 0x78
  92. #define WM8903_INTERRUPT_STATUS_1 0x79
  93. #define WM8903_INTERRUPT_STATUS_1_MASK 0x7A
  94. #define WM8903_INTERRUPT_POLARITY_1 0x7B
  95. #define WM8903_INTERRUPT_CONTROL 0x7E
  96. #define WM8903_CLOCK_RATE_TEST_4 0xA4
  97. #define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC
  98. #define WM8903_REGISTER_COUNT 75
  99. #define WM8903_MAX_REGISTER 0xAC
  100. /*
  101. * Field Definitions.
  102. */
  103. /*
  104. * R0 (0x00) - SW Reset and ID
  105. */
  106. #define WM8903_SW_RESET_DEV_ID1_MASK 0xFFFF /* SW_RESET_DEV_ID1 - [15:0] */
  107. #define WM8903_SW_RESET_DEV_ID1_SHIFT 0 /* SW_RESET_DEV_ID1 - [15:0] */
  108. #define WM8903_SW_RESET_DEV_ID1_WIDTH 16 /* SW_RESET_DEV_ID1 - [15:0] */
  109. /*
  110. * R1 (0x01) - Revision Number
  111. */
  112. #define WM8903_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
  113. #define WM8903_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
  114. #define WM8903_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
  115. /*
  116. * R4 (0x04) - Bias Control 0
  117. */
  118. #define WM8903_POBCTRL 0x0010 /* POBCTRL */
  119. #define WM8903_POBCTRL_MASK 0x0010 /* POBCTRL */
  120. #define WM8903_POBCTRL_SHIFT 4 /* POBCTRL */
  121. #define WM8903_POBCTRL_WIDTH 1 /* POBCTRL */
  122. #define WM8903_ISEL_MASK 0x000C /* ISEL - [3:2] */
  123. #define WM8903_ISEL_SHIFT 2 /* ISEL - [3:2] */
  124. #define WM8903_ISEL_WIDTH 2 /* ISEL - [3:2] */
  125. #define WM8903_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */
  126. #define WM8903_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */
  127. #define WM8903_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */
  128. #define WM8903_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
  129. #define WM8903_BIAS_ENA 0x0001 /* BIAS_ENA */
  130. #define WM8903_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
  131. #define WM8903_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
  132. #define WM8903_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
  133. /*
  134. * R5 (0x05) - VMID Control 0
  135. */
  136. #define WM8903_VMID_TIE_ENA 0x0080 /* VMID_TIE_ENA */
  137. #define WM8903_VMID_TIE_ENA_MASK 0x0080 /* VMID_TIE_ENA */
  138. #define WM8903_VMID_TIE_ENA_SHIFT 7 /* VMID_TIE_ENA */
  139. #define WM8903_VMID_TIE_ENA_WIDTH 1 /* VMID_TIE_ENA */
  140. #define WM8903_BUFIO_ENA 0x0040 /* BUFIO_ENA */
  141. #define WM8903_BUFIO_ENA_MASK 0x0040 /* BUFIO_ENA */
  142. #define WM8903_BUFIO_ENA_SHIFT 6 /* BUFIO_ENA */
  143. #define WM8903_BUFIO_ENA_WIDTH 1 /* BUFIO_ENA */
  144. #define WM8903_VMID_IO_ENA 0x0020 /* VMID_IO_ENA */
  145. #define WM8903_VMID_IO_ENA_MASK 0x0020 /* VMID_IO_ENA */
  146. #define WM8903_VMID_IO_ENA_SHIFT 5 /* VMID_IO_ENA */
  147. #define WM8903_VMID_IO_ENA_WIDTH 1 /* VMID_IO_ENA */
  148. #define WM8903_VMID_SOFT_MASK 0x0018 /* VMID_SOFT - [4:3] */
  149. #define WM8903_VMID_SOFT_SHIFT 3 /* VMID_SOFT - [4:3] */
  150. #define WM8903_VMID_SOFT_WIDTH 2 /* VMID_SOFT - [4:3] */
  151. #define WM8903_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */
  152. #define WM8903_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */
  153. #define WM8903_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */
  154. #define WM8903_VMID_BUF_ENA 0x0001 /* VMID_BUF_ENA */
  155. #define WM8903_VMID_BUF_ENA_MASK 0x0001 /* VMID_BUF_ENA */
  156. #define WM8903_VMID_BUF_ENA_SHIFT 0 /* VMID_BUF_ENA */
  157. #define WM8903_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
  158. #define WM8903_VMID_RES_50K 2
  159. #define WM8903_VMID_RES_250K 4
  160. #define WM8903_VMID_RES_5K 6
  161. /*
  162. * R8 (0x08) - Analogue DAC 0
  163. */
  164. #define WM8903_DACBIAS_SEL_MASK 0x0018 /* DACBIAS_SEL - [4:3] */
  165. #define WM8903_DACBIAS_SEL_SHIFT 3 /* DACBIAS_SEL - [4:3] */
  166. #define WM8903_DACBIAS_SEL_WIDTH 2 /* DACBIAS_SEL - [4:3] */
  167. #define WM8903_DACVMID_BIAS_SEL_MASK 0x0006 /* DACVMID_BIAS_SEL - [2:1] */
  168. #define WM8903_DACVMID_BIAS_SEL_SHIFT 1 /* DACVMID_BIAS_SEL - [2:1] */
  169. #define WM8903_DACVMID_BIAS_SEL_WIDTH 2 /* DACVMID_BIAS_SEL - [2:1] */
  170. /*
  171. * R10 (0x0A) - Analogue ADC 0
  172. */
  173. #define WM8903_ADC_OSR128 0x0001 /* ADC_OSR128 */
  174. #define WM8903_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */
  175. #define WM8903_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */
  176. #define WM8903_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
  177. /*
  178. * R12 (0x0C) - Power Management 0
  179. */
  180. #define WM8903_INL_ENA 0x0002 /* INL_ENA */
  181. #define WM8903_INL_ENA_MASK 0x0002 /* INL_ENA */
  182. #define WM8903_INL_ENA_SHIFT 1 /* INL_ENA */
  183. #define WM8903_INL_ENA_WIDTH 1 /* INL_ENA */
  184. #define WM8903_INR_ENA 0x0001 /* INR_ENA */
  185. #define WM8903_INR_ENA_MASK 0x0001 /* INR_ENA */
  186. #define WM8903_INR_ENA_SHIFT 0 /* INR_ENA */
  187. #define WM8903_INR_ENA_WIDTH 1 /* INR_ENA */
  188. /*
  189. * R13 (0x0D) - Power Management 1
  190. */
  191. #define WM8903_MIXOUTL_ENA 0x0002 /* MIXOUTL_ENA */
  192. #define WM8903_MIXOUTL_ENA_MASK 0x0002 /* MIXOUTL_ENA */
  193. #define WM8903_MIXOUTL_ENA_SHIFT 1 /* MIXOUTL_ENA */
  194. #define WM8903_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */
  195. #define WM8903_MIXOUTR_ENA 0x0001 /* MIXOUTR_ENA */
  196. #define WM8903_MIXOUTR_ENA_MASK 0x0001 /* MIXOUTR_ENA */
  197. #define WM8903_MIXOUTR_ENA_SHIFT 0 /* MIXOUTR_ENA */
  198. #define WM8903_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */
  199. /*
  200. * R14 (0x0E) - Power Management 2
  201. */
  202. #define WM8903_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */
  203. #define WM8903_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */
  204. #define WM8903_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */
  205. #define WM8903_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */
  206. #define WM8903_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */
  207. #define WM8903_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */
  208. #define WM8903_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */
  209. #define WM8903_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */
  210. /*
  211. * R15 (0x0F) - Power Management 3
  212. */
  213. #define WM8903_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */
  214. #define WM8903_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */
  215. #define WM8903_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */
  216. #define WM8903_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */
  217. #define WM8903_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */
  218. #define WM8903_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */
  219. #define WM8903_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */
  220. #define WM8903_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */
  221. /*
  222. * R16 (0x10) - Power Management 4
  223. */
  224. #define WM8903_MIXSPKL_ENA 0x0002 /* MIXSPKL_ENA */
  225. #define WM8903_MIXSPKL_ENA_MASK 0x0002 /* MIXSPKL_ENA */
  226. #define WM8903_MIXSPKL_ENA_SHIFT 1 /* MIXSPKL_ENA */
  227. #define WM8903_MIXSPKL_ENA_WIDTH 1 /* MIXSPKL_ENA */
  228. #define WM8903_MIXSPKR_ENA 0x0001 /* MIXSPKR_ENA */
  229. #define WM8903_MIXSPKR_ENA_MASK 0x0001 /* MIXSPKR_ENA */
  230. #define WM8903_MIXSPKR_ENA_SHIFT 0 /* MIXSPKR_ENA */
  231. #define WM8903_MIXSPKR_ENA_WIDTH 1 /* MIXSPKR_ENA */
  232. /*
  233. * R17 (0x11) - Power Management 5
  234. */
  235. #define WM8903_SPKL_ENA 0x0002 /* SPKL_ENA */
  236. #define WM8903_SPKL_ENA_MASK 0x0002 /* SPKL_ENA */
  237. #define WM8903_SPKL_ENA_SHIFT 1 /* SPKL_ENA */
  238. #define WM8903_SPKL_ENA_WIDTH 1 /* SPKL_ENA */
  239. #define WM8903_SPKR_ENA 0x0001 /* SPKR_ENA */
  240. #define WM8903_SPKR_ENA_MASK 0x0001 /* SPKR_ENA */
  241. #define WM8903_SPKR_ENA_SHIFT 0 /* SPKR_ENA */
  242. #define WM8903_SPKR_ENA_WIDTH 1 /* SPKR_ENA */
  243. /*
  244. * R18 (0x12) - Power Management 6
  245. */
  246. #define WM8903_DACL_ENA 0x0008 /* DACL_ENA */
  247. #define WM8903_DACL_ENA_MASK 0x0008 /* DACL_ENA */
  248. #define WM8903_DACL_ENA_SHIFT 3 /* DACL_ENA */
  249. #define WM8903_DACL_ENA_WIDTH 1 /* DACL_ENA */
  250. #define WM8903_DACR_ENA 0x0004 /* DACR_ENA */
  251. #define WM8903_DACR_ENA_MASK 0x0004 /* DACR_ENA */
  252. #define WM8903_DACR_ENA_SHIFT 2 /* DACR_ENA */
  253. #define WM8903_DACR_ENA_WIDTH 1 /* DACR_ENA */
  254. #define WM8903_ADCL_ENA 0x0002 /* ADCL_ENA */
  255. #define WM8903_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
  256. #define WM8903_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
  257. #define WM8903_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
  258. #define WM8903_ADCR_ENA 0x0001 /* ADCR_ENA */
  259. #define WM8903_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
  260. #define WM8903_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
  261. #define WM8903_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
  262. /*
  263. * R20 (0x14) - Clock Rates 0
  264. */
  265. #define WM8903_MCLKDIV2 0x0001 /* MCLKDIV2 */
  266. #define WM8903_MCLKDIV2_MASK 0x0001 /* MCLKDIV2 */
  267. #define WM8903_MCLKDIV2_SHIFT 0 /* MCLKDIV2 */
  268. #define WM8903_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
  269. /*
  270. * R21 (0x15) - Clock Rates 1
  271. */
  272. #define WM8903_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */
  273. #define WM8903_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */
  274. #define WM8903_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */
  275. #define WM8903_CLK_SYS_MODE_MASK 0x0300 /* CLK_SYS_MODE - [9:8] */
  276. #define WM8903_CLK_SYS_MODE_SHIFT 8 /* CLK_SYS_MODE - [9:8] */
  277. #define WM8903_CLK_SYS_MODE_WIDTH 2 /* CLK_SYS_MODE - [9:8] */
  278. #define WM8903_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
  279. #define WM8903_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
  280. #define WM8903_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
  281. /*
  282. * R22 (0x16) - Clock Rates 2
  283. */
  284. #define WM8903_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */
  285. #define WM8903_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */
  286. #define WM8903_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */
  287. #define WM8903_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
  288. #define WM8903_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
  289. #define WM8903_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
  290. #define WM8903_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
  291. #define WM8903_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
  292. #define WM8903_TO_ENA 0x0001 /* TO_ENA */
  293. #define WM8903_TO_ENA_MASK 0x0001 /* TO_ENA */
  294. #define WM8903_TO_ENA_SHIFT 0 /* TO_ENA */
  295. #define WM8903_TO_ENA_WIDTH 1 /* TO_ENA */
  296. /*
  297. * R24 (0x18) - Audio Interface 0
  298. */
  299. #define WM8903_DACL_DATINV 0x1000 /* DACL_DATINV */
  300. #define WM8903_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */
  301. #define WM8903_DACL_DATINV_SHIFT 12 /* DACL_DATINV */
  302. #define WM8903_DACL_DATINV_WIDTH 1 /* DACL_DATINV */
  303. #define WM8903_DACR_DATINV 0x0800 /* DACR_DATINV */
  304. #define WM8903_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */
  305. #define WM8903_DACR_DATINV_SHIFT 11 /* DACR_DATINV */
  306. #define WM8903_DACR_DATINV_WIDTH 1 /* DACR_DATINV */
  307. #define WM8903_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */
  308. #define WM8903_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */
  309. #define WM8903_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */
  310. #define WM8903_LOOPBACK 0x0100 /* LOOPBACK */
  311. #define WM8903_LOOPBACK_MASK 0x0100 /* LOOPBACK */
  312. #define WM8903_LOOPBACK_SHIFT 8 /* LOOPBACK */
  313. #define WM8903_LOOPBACK_WIDTH 1 /* LOOPBACK */
  314. #define WM8903_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */
  315. #define WM8903_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */
  316. #define WM8903_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */
  317. #define WM8903_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */
  318. #define WM8903_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */
  319. #define WM8903_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */
  320. #define WM8903_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */
  321. #define WM8903_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */
  322. #define WM8903_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */
  323. #define WM8903_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */
  324. #define WM8903_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */
  325. #define WM8903_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */
  326. #define WM8903_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */
  327. #define WM8903_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */
  328. #define WM8903_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */
  329. #define WM8903_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */
  330. #define WM8903_ADC_COMP 0x0008 /* ADC_COMP */
  331. #define WM8903_ADC_COMP_MASK 0x0008 /* ADC_COMP */
  332. #define WM8903_ADC_COMP_SHIFT 3 /* ADC_COMP */
  333. #define WM8903_ADC_COMP_WIDTH 1 /* ADC_COMP */
  334. #define WM8903_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */
  335. #define WM8903_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */
  336. #define WM8903_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */
  337. #define WM8903_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
  338. #define WM8903_DAC_COMP 0x0002 /* DAC_COMP */
  339. #define WM8903_DAC_COMP_MASK 0x0002 /* DAC_COMP */
  340. #define WM8903_DAC_COMP_SHIFT 1 /* DAC_COMP */
  341. #define WM8903_DAC_COMP_WIDTH 1 /* DAC_COMP */
  342. #define WM8903_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
  343. #define WM8903_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
  344. #define WM8903_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
  345. #define WM8903_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
  346. /*
  347. * R25 (0x19) - Audio Interface 1
  348. */
  349. #define WM8903_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
  350. #define WM8903_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */
  351. #define WM8903_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */
  352. #define WM8903_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */
  353. #define WM8903_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
  354. #define WM8903_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */
  355. #define WM8903_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */
  356. #define WM8903_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */
  357. #define WM8903_AIFADC_TDM 0x0800 /* AIFADC_TDM */
  358. #define WM8903_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */
  359. #define WM8903_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */
  360. #define WM8903_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */
  361. #define WM8903_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */
  362. #define WM8903_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */
  363. #define WM8903_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */
  364. #define WM8903_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */
  365. #define WM8903_LRCLK_DIR 0x0200 /* LRCLK_DIR */
  366. #define WM8903_LRCLK_DIR_MASK 0x0200 /* LRCLK_DIR */
  367. #define WM8903_LRCLK_DIR_SHIFT 9 /* LRCLK_DIR */
  368. #define WM8903_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
  369. #define WM8903_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
  370. #define WM8903_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
  371. #define WM8903_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
  372. #define WM8903_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
  373. #define WM8903_BCLK_DIR 0x0040 /* BCLK_DIR */
  374. #define WM8903_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
  375. #define WM8903_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
  376. #define WM8903_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
  377. #define WM8903_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
  378. #define WM8903_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
  379. #define WM8903_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
  380. #define WM8903_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
  381. #define WM8903_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
  382. #define WM8903_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
  383. #define WM8903_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
  384. #define WM8903_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
  385. #define WM8903_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
  386. #define WM8903_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
  387. /*
  388. * R26 (0x1A) - Audio Interface 2
  389. */
  390. #define WM8903_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
  391. #define WM8903_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
  392. #define WM8903_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
  393. /*
  394. * R27 (0x1B) - Audio Interface 3
  395. */
  396. #define WM8903_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
  397. #define WM8903_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
  398. #define WM8903_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
  399. /*
  400. * R30 (0x1E) - DAC Digital Volume Left
  401. */
  402. #define WM8903_DACVU 0x0100 /* DACVU */
  403. #define WM8903_DACVU_MASK 0x0100 /* DACVU */
  404. #define WM8903_DACVU_SHIFT 8 /* DACVU */
  405. #define WM8903_DACVU_WIDTH 1 /* DACVU */
  406. #define WM8903_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
  407. #define WM8903_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
  408. #define WM8903_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
  409. /*
  410. * R31 (0x1F) - DAC Digital Volume Right
  411. */
  412. #define WM8903_DACVU 0x0100 /* DACVU */
  413. #define WM8903_DACVU_MASK 0x0100 /* DACVU */
  414. #define WM8903_DACVU_SHIFT 8 /* DACVU */
  415. #define WM8903_DACVU_WIDTH 1 /* DACVU */
  416. #define WM8903_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
  417. #define WM8903_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
  418. #define WM8903_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
  419. /*
  420. * R32 (0x20) - DAC Digital 0
  421. */
  422. #define WM8903_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */
  423. #define WM8903_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */
  424. #define WM8903_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */
  425. #define WM8903_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */
  426. #define WM8903_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */
  427. #define WM8903_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */
  428. #define WM8903_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
  429. #define WM8903_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
  430. #define WM8903_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
  431. #define WM8903_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */
  432. #define WM8903_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */
  433. #define WM8903_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */
  434. /*
  435. * R33 (0x21) - DAC Digital 1
  436. */
  437. #define WM8903_DAC_MONO 0x1000 /* DAC_MONO */
  438. #define WM8903_DAC_MONO_MASK 0x1000 /* DAC_MONO */
  439. #define WM8903_DAC_MONO_SHIFT 12 /* DAC_MONO */
  440. #define WM8903_DAC_MONO_WIDTH 1 /* DAC_MONO */
  441. #define WM8903_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */
  442. #define WM8903_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */
  443. #define WM8903_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */
  444. #define WM8903_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */
  445. #define WM8903_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
  446. #define WM8903_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
  447. #define WM8903_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
  448. #define WM8903_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
  449. #define WM8903_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
  450. #define WM8903_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
  451. #define WM8903_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
  452. #define WM8903_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
  453. #define WM8903_DAC_MUTE 0x0008 /* DAC_MUTE */
  454. #define WM8903_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
  455. #define WM8903_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
  456. #define WM8903_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
  457. #define WM8903_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
  458. #define WM8903_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
  459. #define WM8903_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
  460. /*
  461. * R36 (0x24) - ADC Digital Volume Left
  462. */
  463. #define WM8903_ADCVU 0x0100 /* ADCVU */
  464. #define WM8903_ADCVU_MASK 0x0100 /* ADCVU */
  465. #define WM8903_ADCVU_SHIFT 8 /* ADCVU */
  466. #define WM8903_ADCVU_WIDTH 1 /* ADCVU */
  467. #define WM8903_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
  468. #define WM8903_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
  469. #define WM8903_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
  470. /*
  471. * R37 (0x25) - ADC Digital Volume Right
  472. */
  473. #define WM8903_ADCVU 0x0100 /* ADCVU */
  474. #define WM8903_ADCVU_MASK 0x0100 /* ADCVU */
  475. #define WM8903_ADCVU_SHIFT 8 /* ADCVU */
  476. #define WM8903_ADCVU_WIDTH 1 /* ADCVU */
  477. #define WM8903_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
  478. #define WM8903_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
  479. #define WM8903_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
  480. /*
  481. * R38 (0x26) - ADC Digital 0
  482. */
  483. #define WM8903_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */
  484. #define WM8903_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */
  485. #define WM8903_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */
  486. #define WM8903_ADC_HPF_ENA 0x0010 /* ADC_HPF_ENA */
  487. #define WM8903_ADC_HPF_ENA_MASK 0x0010 /* ADC_HPF_ENA */
  488. #define WM8903_ADC_HPF_ENA_SHIFT 4 /* ADC_HPF_ENA */
  489. #define WM8903_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */
  490. #define WM8903_ADCL_DATINV 0x0002 /* ADCL_DATINV */
  491. #define WM8903_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */
  492. #define WM8903_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */
  493. #define WM8903_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */
  494. #define WM8903_ADCR_DATINV 0x0001 /* ADCR_DATINV */
  495. #define WM8903_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
  496. #define WM8903_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */
  497. #define WM8903_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */
  498. /*
  499. * R39 (0x27) - Digital Microphone 0
  500. */
  501. #define WM8903_DIGMIC_MODE_SEL 0x0100 /* DIGMIC_MODE_SEL */
  502. #define WM8903_DIGMIC_MODE_SEL_MASK 0x0100 /* DIGMIC_MODE_SEL */
  503. #define WM8903_DIGMIC_MODE_SEL_SHIFT 8 /* DIGMIC_MODE_SEL */
  504. #define WM8903_DIGMIC_MODE_SEL_WIDTH 1 /* DIGMIC_MODE_SEL */
  505. #define WM8903_DIGMIC_CLK_SEL_L_MASK 0x00C0 /* DIGMIC_CLK_SEL_L - [7:6] */
  506. #define WM8903_DIGMIC_CLK_SEL_L_SHIFT 6 /* DIGMIC_CLK_SEL_L - [7:6] */
  507. #define WM8903_DIGMIC_CLK_SEL_L_WIDTH 2 /* DIGMIC_CLK_SEL_L - [7:6] */
  508. #define WM8903_DIGMIC_CLK_SEL_R_MASK 0x0030 /* DIGMIC_CLK_SEL_R - [5:4] */
  509. #define WM8903_DIGMIC_CLK_SEL_R_SHIFT 4 /* DIGMIC_CLK_SEL_R - [5:4] */
  510. #define WM8903_DIGMIC_CLK_SEL_R_WIDTH 2 /* DIGMIC_CLK_SEL_R - [5:4] */
  511. #define WM8903_DIGMIC_CLK_SEL_RT_MASK 0x000C /* DIGMIC_CLK_SEL_RT - [3:2] */
  512. #define WM8903_DIGMIC_CLK_SEL_RT_SHIFT 2 /* DIGMIC_CLK_SEL_RT - [3:2] */
  513. #define WM8903_DIGMIC_CLK_SEL_RT_WIDTH 2 /* DIGMIC_CLK_SEL_RT - [3:2] */
  514. #define WM8903_DIGMIC_CLK_SEL_MASK 0x0003 /* DIGMIC_CLK_SEL - [1:0] */
  515. #define WM8903_DIGMIC_CLK_SEL_SHIFT 0 /* DIGMIC_CLK_SEL - [1:0] */
  516. #define WM8903_DIGMIC_CLK_SEL_WIDTH 2 /* DIGMIC_CLK_SEL - [1:0] */
  517. /*
  518. * R40 (0x28) - DRC 0
  519. */
  520. #define WM8903_DRC_ENA 0x8000 /* DRC_ENA */
  521. #define WM8903_DRC_ENA_MASK 0x8000 /* DRC_ENA */
  522. #define WM8903_DRC_ENA_SHIFT 15 /* DRC_ENA */
  523. #define WM8903_DRC_ENA_WIDTH 1 /* DRC_ENA */
  524. #define WM8903_DRC_THRESH_HYST_MASK 0x1800 /* DRC_THRESH_HYST - [12:11] */
  525. #define WM8903_DRC_THRESH_HYST_SHIFT 11 /* DRC_THRESH_HYST - [12:11] */
  526. #define WM8903_DRC_THRESH_HYST_WIDTH 2 /* DRC_THRESH_HYST - [12:11] */
  527. #define WM8903_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
  528. #define WM8903_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
  529. #define WM8903_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
  530. #define WM8903_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */
  531. #define WM8903_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */
  532. #define WM8903_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */
  533. #define WM8903_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */
  534. #define WM8903_DRC_SMOOTH_ENA 0x0008 /* DRC_SMOOTH_ENA */
  535. #define WM8903_DRC_SMOOTH_ENA_MASK 0x0008 /* DRC_SMOOTH_ENA */
  536. #define WM8903_DRC_SMOOTH_ENA_SHIFT 3 /* DRC_SMOOTH_ENA */
  537. #define WM8903_DRC_SMOOTH_ENA_WIDTH 1 /* DRC_SMOOTH_ENA */
  538. #define WM8903_DRC_QR_ENA 0x0004 /* DRC_QR_ENA */
  539. #define WM8903_DRC_QR_ENA_MASK 0x0004 /* DRC_QR_ENA */
  540. #define WM8903_DRC_QR_ENA_SHIFT 2 /* DRC_QR_ENA */
  541. #define WM8903_DRC_QR_ENA_WIDTH 1 /* DRC_QR_ENA */
  542. #define WM8903_DRC_ANTICLIP_ENA 0x0002 /* DRC_ANTICLIP_ENA */
  543. #define WM8903_DRC_ANTICLIP_ENA_MASK 0x0002 /* DRC_ANTICLIP_ENA */
  544. #define WM8903_DRC_ANTICLIP_ENA_SHIFT 1 /* DRC_ANTICLIP_ENA */
  545. #define WM8903_DRC_ANTICLIP_ENA_WIDTH 1 /* DRC_ANTICLIP_ENA */
  546. #define WM8903_DRC_HYST_ENA 0x0001 /* DRC_HYST_ENA */
  547. #define WM8903_DRC_HYST_ENA_MASK 0x0001 /* DRC_HYST_ENA */
  548. #define WM8903_DRC_HYST_ENA_SHIFT 0 /* DRC_HYST_ENA */
  549. #define WM8903_DRC_HYST_ENA_WIDTH 1 /* DRC_HYST_ENA */
  550. /*
  551. * R41 (0x29) - DRC 1
  552. */
  553. #define WM8903_DRC_ATTACK_RATE_MASK 0xF000 /* DRC_ATTACK_RATE - [15:12] */
  554. #define WM8903_DRC_ATTACK_RATE_SHIFT 12 /* DRC_ATTACK_RATE - [15:12] */
  555. #define WM8903_DRC_ATTACK_RATE_WIDTH 4 /* DRC_ATTACK_RATE - [15:12] */
  556. #define WM8903_DRC_DECAY_RATE_MASK 0x0F00 /* DRC_DECAY_RATE - [11:8] */
  557. #define WM8903_DRC_DECAY_RATE_SHIFT 8 /* DRC_DECAY_RATE - [11:8] */
  558. #define WM8903_DRC_DECAY_RATE_WIDTH 4 /* DRC_DECAY_RATE - [11:8] */
  559. #define WM8903_DRC_THRESH_QR_MASK 0x00C0 /* DRC_THRESH_QR - [7:6] */
  560. #define WM8903_DRC_THRESH_QR_SHIFT 6 /* DRC_THRESH_QR - [7:6] */
  561. #define WM8903_DRC_THRESH_QR_WIDTH 2 /* DRC_THRESH_QR - [7:6] */
  562. #define WM8903_DRC_RATE_QR_MASK 0x0030 /* DRC_RATE_QR - [5:4] */
  563. #define WM8903_DRC_RATE_QR_SHIFT 4 /* DRC_RATE_QR - [5:4] */
  564. #define WM8903_DRC_RATE_QR_WIDTH 2 /* DRC_RATE_QR - [5:4] */
  565. #define WM8903_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
  566. #define WM8903_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
  567. #define WM8903_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
  568. #define WM8903_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
  569. #define WM8903_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
  570. #define WM8903_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
  571. /*
  572. * R42 (0x2A) - DRC 2
  573. */
  574. #define WM8903_DRC_R0_SLOPE_COMP_MASK 0x0038 /* DRC_R0_SLOPE_COMP - [5:3] */
  575. #define WM8903_DRC_R0_SLOPE_COMP_SHIFT 3 /* DRC_R0_SLOPE_COMP - [5:3] */
  576. #define WM8903_DRC_R0_SLOPE_COMP_WIDTH 3 /* DRC_R0_SLOPE_COMP - [5:3] */
  577. #define WM8903_DRC_R1_SLOPE_COMP_MASK 0x0007 /* DRC_R1_SLOPE_COMP - [2:0] */
  578. #define WM8903_DRC_R1_SLOPE_COMP_SHIFT 0 /* DRC_R1_SLOPE_COMP - [2:0] */
  579. #define WM8903_DRC_R1_SLOPE_COMP_WIDTH 3 /* DRC_R1_SLOPE_COMP - [2:0] */
  580. /*
  581. * R43 (0x2B) - DRC 3
  582. */
  583. #define WM8903_DRC_THRESH_COMP_MASK 0x07E0 /* DRC_THRESH_COMP - [10:5] */
  584. #define WM8903_DRC_THRESH_COMP_SHIFT 5 /* DRC_THRESH_COMP - [10:5] */
  585. #define WM8903_DRC_THRESH_COMP_WIDTH 6 /* DRC_THRESH_COMP - [10:5] */
  586. #define WM8903_DRC_AMP_COMP_MASK 0x001F /* DRC_AMP_COMP - [4:0] */
  587. #define WM8903_DRC_AMP_COMP_SHIFT 0 /* DRC_AMP_COMP - [4:0] */
  588. #define WM8903_DRC_AMP_COMP_WIDTH 5 /* DRC_AMP_COMP - [4:0] */
  589. /*
  590. * R44 (0x2C) - Analogue Left Input 0
  591. */
  592. #define WM8903_LINMUTE 0x0080 /* LINMUTE */
  593. #define WM8903_LINMUTE_MASK 0x0080 /* LINMUTE */
  594. #define WM8903_LINMUTE_SHIFT 7 /* LINMUTE */
  595. #define WM8903_LINMUTE_WIDTH 1 /* LINMUTE */
  596. #define WM8903_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */
  597. #define WM8903_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */
  598. #define WM8903_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */
  599. /*
  600. * R45 (0x2D) - Analogue Right Input 0
  601. */
  602. #define WM8903_RINMUTE 0x0080 /* RINMUTE */
  603. #define WM8903_RINMUTE_MASK 0x0080 /* RINMUTE */
  604. #define WM8903_RINMUTE_SHIFT 7 /* RINMUTE */
  605. #define WM8903_RINMUTE_WIDTH 1 /* RINMUTE */
  606. #define WM8903_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */
  607. #define WM8903_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */
  608. #define WM8903_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */
  609. /*
  610. * R46 (0x2E) - Analogue Left Input 1
  611. */
  612. #define WM8903_INL_CM_ENA 0x0040 /* INL_CM_ENA */
  613. #define WM8903_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */
  614. #define WM8903_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */
  615. #define WM8903_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */
  616. #define WM8903_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */
  617. #define WM8903_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */
  618. #define WM8903_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */
  619. #define WM8903_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */
  620. #define WM8903_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */
  621. #define WM8903_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */
  622. #define WM8903_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */
  623. #define WM8903_L_MODE_SHIFT 0 /* L_MODE - [1:0] */
  624. #define WM8903_L_MODE_WIDTH 2 /* L_MODE - [1:0] */
  625. /*
  626. * R47 (0x2F) - Analogue Right Input 1
  627. */
  628. #define WM8903_INR_CM_ENA 0x0040 /* INR_CM_ENA */
  629. #define WM8903_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */
  630. #define WM8903_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */
  631. #define WM8903_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */
  632. #define WM8903_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */
  633. #define WM8903_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */
  634. #define WM8903_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */
  635. #define WM8903_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */
  636. #define WM8903_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */
  637. #define WM8903_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */
  638. #define WM8903_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */
  639. #define WM8903_R_MODE_SHIFT 0 /* R_MODE - [1:0] */
  640. #define WM8903_R_MODE_WIDTH 2 /* R_MODE - [1:0] */
  641. /*
  642. * R50 (0x32) - Analogue Left Mix 0
  643. */
  644. #define WM8903_DACL_TO_MIXOUTL 0x0008 /* DACL_TO_MIXOUTL */
  645. #define WM8903_DACL_TO_MIXOUTL_MASK 0x0008 /* DACL_TO_MIXOUTL */
  646. #define WM8903_DACL_TO_MIXOUTL_SHIFT 3 /* DACL_TO_MIXOUTL */
  647. #define WM8903_DACL_TO_MIXOUTL_WIDTH 1 /* DACL_TO_MIXOUTL */
  648. #define WM8903_DACR_TO_MIXOUTL 0x0004 /* DACR_TO_MIXOUTL */
  649. #define WM8903_DACR_TO_MIXOUTL_MASK 0x0004 /* DACR_TO_MIXOUTL */
  650. #define WM8903_DACR_TO_MIXOUTL_SHIFT 2 /* DACR_TO_MIXOUTL */
  651. #define WM8903_DACR_TO_MIXOUTL_WIDTH 1 /* DACR_TO_MIXOUTL */
  652. #define WM8903_BYPASSL_TO_MIXOUTL 0x0002 /* BYPASSL_TO_MIXOUTL */
  653. #define WM8903_BYPASSL_TO_MIXOUTL_MASK 0x0002 /* BYPASSL_TO_MIXOUTL */
  654. #define WM8903_BYPASSL_TO_MIXOUTL_SHIFT 1 /* BYPASSL_TO_MIXOUTL */
  655. #define WM8903_BYPASSL_TO_MIXOUTL_WIDTH 1 /* BYPASSL_TO_MIXOUTL */
  656. #define WM8903_BYPASSR_TO_MIXOUTL 0x0001 /* BYPASSR_TO_MIXOUTL */
  657. #define WM8903_BYPASSR_TO_MIXOUTL_MASK 0x0001 /* BYPASSR_TO_MIXOUTL */
  658. #define WM8903_BYPASSR_TO_MIXOUTL_SHIFT 0 /* BYPASSR_TO_MIXOUTL */
  659. #define WM8903_BYPASSR_TO_MIXOUTL_WIDTH 1 /* BYPASSR_TO_MIXOUTL */
  660. /*
  661. * R51 (0x33) - Analogue Right Mix 0
  662. */
  663. #define WM8903_DACL_TO_MIXOUTR 0x0008 /* DACL_TO_MIXOUTR */
  664. #define WM8903_DACL_TO_MIXOUTR_MASK 0x0008 /* DACL_TO_MIXOUTR */
  665. #define WM8903_DACL_TO_MIXOUTR_SHIFT 3 /* DACL_TO_MIXOUTR */
  666. #define WM8903_DACL_TO_MIXOUTR_WIDTH 1 /* DACL_TO_MIXOUTR */
  667. #define WM8903_DACR_TO_MIXOUTR 0x0004 /* DACR_TO_MIXOUTR */
  668. #define WM8903_DACR_TO_MIXOUTR_MASK 0x0004 /* DACR_TO_MIXOUTR */
  669. #define WM8903_DACR_TO_MIXOUTR_SHIFT 2 /* DACR_TO_MIXOUTR */
  670. #define WM8903_DACR_TO_MIXOUTR_WIDTH 1 /* DACR_TO_MIXOUTR */
  671. #define WM8903_BYPASSL_TO_MIXOUTR 0x0002 /* BYPASSL_TO_MIXOUTR */
  672. #define WM8903_BYPASSL_TO_MIXOUTR_MASK 0x0002 /* BYPASSL_TO_MIXOUTR */
  673. #define WM8903_BYPASSL_TO_MIXOUTR_SHIFT 1 /* BYPASSL_TO_MIXOUTR */
  674. #define WM8903_BYPASSL_TO_MIXOUTR_WIDTH 1 /* BYPASSL_TO_MIXOUTR */
  675. #define WM8903_BYPASSR_TO_MIXOUTR 0x0001 /* BYPASSR_TO_MIXOUTR */
  676. #define WM8903_BYPASSR_TO_MIXOUTR_MASK 0x0001 /* BYPASSR_TO_MIXOUTR */
  677. #define WM8903_BYPASSR_TO_MIXOUTR_SHIFT 0 /* BYPASSR_TO_MIXOUTR */
  678. #define WM8903_BYPASSR_TO_MIXOUTR_WIDTH 1 /* BYPASSR_TO_MIXOUTR */
  679. /*
  680. * R52 (0x34) - Analogue Spk Mix Left 0
  681. */
  682. #define WM8903_DACL_TO_MIXSPKL 0x0008 /* DACL_TO_MIXSPKL */
  683. #define WM8903_DACL_TO_MIXSPKL_MASK 0x0008 /* DACL_TO_MIXSPKL */
  684. #define WM8903_DACL_TO_MIXSPKL_SHIFT 3 /* DACL_TO_MIXSPKL */
  685. #define WM8903_DACL_TO_MIXSPKL_WIDTH 1 /* DACL_TO_MIXSPKL */
  686. #define WM8903_DACR_TO_MIXSPKL 0x0004 /* DACR_TO_MIXSPKL */
  687. #define WM8903_DACR_TO_MIXSPKL_MASK 0x0004 /* DACR_TO_MIXSPKL */
  688. #define WM8903_DACR_TO_MIXSPKL_SHIFT 2 /* DACR_TO_MIXSPKL */
  689. #define WM8903_DACR_TO_MIXSPKL_WIDTH 1 /* DACR_TO_MIXSPKL */
  690. #define WM8903_BYPASSL_TO_MIXSPKL 0x0002 /* BYPASSL_TO_MIXSPKL */
  691. #define WM8903_BYPASSL_TO_MIXSPKL_MASK 0x0002 /* BYPASSL_TO_MIXSPKL */
  692. #define WM8903_BYPASSL_TO_MIXSPKL_SHIFT 1 /* BYPASSL_TO_MIXSPKL */
  693. #define WM8903_BYPASSL_TO_MIXSPKL_WIDTH 1 /* BYPASSL_TO_MIXSPKL */
  694. #define WM8903_BYPASSR_TO_MIXSPKL 0x0001 /* BYPASSR_TO_MIXSPKL */
  695. #define WM8903_BYPASSR_TO_MIXSPKL_MASK 0x0001 /* BYPASSR_TO_MIXSPKL */
  696. #define WM8903_BYPASSR_TO_MIXSPKL_SHIFT 0 /* BYPASSR_TO_MIXSPKL */
  697. #define WM8903_BYPASSR_TO_MIXSPKL_WIDTH 1 /* BYPASSR_TO_MIXSPKL */
  698. /*
  699. * R53 (0x35) - Analogue Spk Mix Left 1
  700. */
  701. #define WM8903_DACL_MIXSPKL_VOL 0x0008 /* DACL_MIXSPKL_VOL */
  702. #define WM8903_DACL_MIXSPKL_VOL_MASK 0x0008 /* DACL_MIXSPKL_VOL */
  703. #define WM8903_DACL_MIXSPKL_VOL_SHIFT 3 /* DACL_MIXSPKL_VOL */
  704. #define WM8903_DACL_MIXSPKL_VOL_WIDTH 1 /* DACL_MIXSPKL_VOL */
  705. #define WM8903_DACR_MIXSPKL_VOL 0x0004 /* DACR_MIXSPKL_VOL */
  706. #define WM8903_DACR_MIXSPKL_VOL_MASK 0x0004 /* DACR_MIXSPKL_VOL */
  707. #define WM8903_DACR_MIXSPKL_VOL_SHIFT 2 /* DACR_MIXSPKL_VOL */
  708. #define WM8903_DACR_MIXSPKL_VOL_WIDTH 1 /* DACR_MIXSPKL_VOL */
  709. #define WM8903_BYPASSL_MIXSPKL_VOL 0x0002 /* BYPASSL_MIXSPKL_VOL */
  710. #define WM8903_BYPASSL_MIXSPKL_VOL_MASK 0x0002 /* BYPASSL_MIXSPKL_VOL */
  711. #define WM8903_BYPASSL_MIXSPKL_VOL_SHIFT 1 /* BYPASSL_MIXSPKL_VOL */
  712. #define WM8903_BYPASSL_MIXSPKL_VOL_WIDTH 1 /* BYPASSL_MIXSPKL_VOL */
  713. #define WM8903_BYPASSR_MIXSPKL_VOL 0x0001 /* BYPASSR_MIXSPKL_VOL */
  714. #define WM8903_BYPASSR_MIXSPKL_VOL_MASK 0x0001 /* BYPASSR_MIXSPKL_VOL */
  715. #define WM8903_BYPASSR_MIXSPKL_VOL_SHIFT 0 /* BYPASSR_MIXSPKL_VOL */
  716. #define WM8903_BYPASSR_MIXSPKL_VOL_WIDTH 1 /* BYPASSR_MIXSPKL_VOL */
  717. /*
  718. * R54 (0x36) - Analogue Spk Mix Right 0
  719. */
  720. #define WM8903_DACL_TO_MIXSPKR 0x0008 /* DACL_TO_MIXSPKR */
  721. #define WM8903_DACL_TO_MIXSPKR_MASK 0x0008 /* DACL_TO_MIXSPKR */
  722. #define WM8903_DACL_TO_MIXSPKR_SHIFT 3 /* DACL_TO_MIXSPKR */
  723. #define WM8903_DACL_TO_MIXSPKR_WIDTH 1 /* DACL_TO_MIXSPKR */
  724. #define WM8903_DACR_TO_MIXSPKR 0x0004 /* DACR_TO_MIXSPKR */
  725. #define WM8903_DACR_TO_MIXSPKR_MASK 0x0004 /* DACR_TO_MIXSPKR */
  726. #define WM8903_DACR_TO_MIXSPKR_SHIFT 2 /* DACR_TO_MIXSPKR */
  727. #define WM8903_DACR_TO_MIXSPKR_WIDTH 1 /* DACR_TO_MIXSPKR */
  728. #define WM8903_BYPASSL_TO_MIXSPKR 0x0002 /* BYPASSL_TO_MIXSPKR */
  729. #define WM8903_BYPASSL_TO_MIXSPKR_MASK 0x0002 /* BYPASSL_TO_MIXSPKR */
  730. #define WM8903_BYPASSL_TO_MIXSPKR_SHIFT 1 /* BYPASSL_TO_MIXSPKR */
  731. #define WM8903_BYPASSL_TO_MIXSPKR_WIDTH 1 /* BYPASSL_TO_MIXSPKR */
  732. #define WM8903_BYPASSR_TO_MIXSPKR 0x0001 /* BYPASSR_TO_MIXSPKR */
  733. #define WM8903_BYPASSR_TO_MIXSPKR_MASK 0x0001 /* BYPASSR_TO_MIXSPKR */
  734. #define WM8903_BYPASSR_TO_MIXSPKR_SHIFT 0 /* BYPASSR_TO_MIXSPKR */
  735. #define WM8903_BYPASSR_TO_MIXSPKR_WIDTH 1 /* BYPASSR_TO_MIXSPKR */
  736. /*
  737. * R55 (0x37) - Analogue Spk Mix Right 1
  738. */
  739. #define WM8903_DACL_MIXSPKR_VOL 0x0008 /* DACL_MIXSPKR_VOL */
  740. #define WM8903_DACL_MIXSPKR_VOL_MASK 0x0008 /* DACL_MIXSPKR_VOL */
  741. #define WM8903_DACL_MIXSPKR_VOL_SHIFT 3 /* DACL_MIXSPKR_VOL */
  742. #define WM8903_DACL_MIXSPKR_VOL_WIDTH 1 /* DACL_MIXSPKR_VOL */
  743. #define WM8903_DACR_MIXSPKR_VOL 0x0004 /* DACR_MIXSPKR_VOL */
  744. #define WM8903_DACR_MIXSPKR_VOL_MASK 0x0004 /* DACR_MIXSPKR_VOL */
  745. #define WM8903_DACR_MIXSPKR_VOL_SHIFT 2 /* DACR_MIXSPKR_VOL */
  746. #define WM8903_DACR_MIXSPKR_VOL_WIDTH 1 /* DACR_MIXSPKR_VOL */
  747. #define WM8903_BYPASSL_MIXSPKR_VOL 0x0002 /* BYPASSL_MIXSPKR_VOL */
  748. #define WM8903_BYPASSL_MIXSPKR_VOL_MASK 0x0002 /* BYPASSL_MIXSPKR_VOL */
  749. #define WM8903_BYPASSL_MIXSPKR_VOL_SHIFT 1 /* BYPASSL_MIXSPKR_VOL */
  750. #define WM8903_BYPASSL_MIXSPKR_VOL_WIDTH 1 /* BYPASSL_MIXSPKR_VOL */
  751. #define WM8903_BYPASSR_MIXSPKR_VOL 0x0001 /* BYPASSR_MIXSPKR_VOL */
  752. #define WM8903_BYPASSR_MIXSPKR_VOL_MASK 0x0001 /* BYPASSR_MIXSPKR_VOL */
  753. #define WM8903_BYPASSR_MIXSPKR_VOL_SHIFT 0 /* BYPASSR_MIXSPKR_VOL */
  754. #define WM8903_BYPASSR_MIXSPKR_VOL_WIDTH 1 /* BYPASSR_MIXSPKR_VOL */
  755. /*
  756. * R57 (0x39) - Analogue OUT1 Left
  757. */
  758. #define WM8903_HPL_MUTE 0x0100 /* HPL_MUTE */
  759. #define WM8903_HPL_MUTE_MASK 0x0100 /* HPL_MUTE */
  760. #define WM8903_HPL_MUTE_SHIFT 8 /* HPL_MUTE */
  761. #define WM8903_HPL_MUTE_WIDTH 1 /* HPL_MUTE */
  762. #define WM8903_HPOUTVU 0x0080 /* HPOUTVU */
  763. #define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */
  764. #define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */
  765. #define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */
  766. #define WM8903_HPOUTLZC 0x0040 /* HPOUTLZC */
  767. #define WM8903_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */
  768. #define WM8903_HPOUTLZC_SHIFT 6 /* HPOUTLZC */
  769. #define WM8903_HPOUTLZC_WIDTH 1 /* HPOUTLZC */
  770. #define WM8903_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */
  771. #define WM8903_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */
  772. #define WM8903_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */
  773. /*
  774. * R58 (0x3A) - Analogue OUT1 Right
  775. */
  776. #define WM8903_HPR_MUTE 0x0100 /* HPR_MUTE */
  777. #define WM8903_HPR_MUTE_MASK 0x0100 /* HPR_MUTE */
  778. #define WM8903_HPR_MUTE_SHIFT 8 /* HPR_MUTE */
  779. #define WM8903_HPR_MUTE_WIDTH 1 /* HPR_MUTE */
  780. #define WM8903_HPOUTVU 0x0080 /* HPOUTVU */
  781. #define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */
  782. #define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */
  783. #define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */
  784. #define WM8903_HPOUTRZC 0x0040 /* HPOUTRZC */
  785. #define WM8903_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */
  786. #define WM8903_HPOUTRZC_SHIFT 6 /* HPOUTRZC */
  787. #define WM8903_HPOUTRZC_WIDTH 1 /* HPOUTRZC */
  788. #define WM8903_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */
  789. #define WM8903_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */
  790. #define WM8903_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */
  791. /*
  792. * R59 (0x3B) - Analogue OUT2 Left
  793. */
  794. #define WM8903_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */
  795. #define WM8903_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */
  796. #define WM8903_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */
  797. #define WM8903_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */
  798. #define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */
  799. #define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */
  800. #define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */
  801. #define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */
  802. #define WM8903_LINEOUTLZC 0x0040 /* LINEOUTLZC */
  803. #define WM8903_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */
  804. #define WM8903_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */
  805. #define WM8903_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */
  806. #define WM8903_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */
  807. #define WM8903_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */
  808. #define WM8903_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */
  809. /*
  810. * R60 (0x3C) - Analogue OUT2 Right
  811. */
  812. #define WM8903_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */
  813. #define WM8903_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */
  814. #define WM8903_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */
  815. #define WM8903_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */
  816. #define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */
  817. #define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */
  818. #define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */
  819. #define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */
  820. #define WM8903_LINEOUTRZC 0x0040 /* LINEOUTRZC */
  821. #define WM8903_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */
  822. #define WM8903_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */
  823. #define WM8903_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */
  824. #define WM8903_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */
  825. #define WM8903_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */
  826. #define WM8903_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */
  827. /*
  828. * R62 (0x3E) - Analogue OUT3 Left
  829. */
  830. #define WM8903_SPKL_MUTE 0x0100 /* SPKL_MUTE */
  831. #define WM8903_SPKL_MUTE_MASK 0x0100 /* SPKL_MUTE */
  832. #define WM8903_SPKL_MUTE_SHIFT 8 /* SPKL_MUTE */
  833. #define WM8903_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */
  834. #define WM8903_SPKVU 0x0080 /* SPKVU */
  835. #define WM8903_SPKVU_MASK 0x0080 /* SPKVU */
  836. #define WM8903_SPKVU_SHIFT 7 /* SPKVU */
  837. #define WM8903_SPKVU_WIDTH 1 /* SPKVU */
  838. #define WM8903_SPKLZC 0x0040 /* SPKLZC */
  839. #define WM8903_SPKLZC_MASK 0x0040 /* SPKLZC */
  840. #define WM8903_SPKLZC_SHIFT 6 /* SPKLZC */
  841. #define WM8903_SPKLZC_WIDTH 1 /* SPKLZC */
  842. #define WM8903_SPKL_VOL_MASK 0x003F /* SPKL_VOL - [5:0] */
  843. #define WM8903_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [5:0] */
  844. #define WM8903_SPKL_VOL_WIDTH 6 /* SPKL_VOL - [5:0] */
  845. /*
  846. * R63 (0x3F) - Analogue OUT3 Right
  847. */
  848. #define WM8903_SPKR_MUTE 0x0100 /* SPKR_MUTE */
  849. #define WM8903_SPKR_MUTE_MASK 0x0100 /* SPKR_MUTE */
  850. #define WM8903_SPKR_MUTE_SHIFT 8 /* SPKR_MUTE */
  851. #define WM8903_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */
  852. #define WM8903_SPKVU 0x0080 /* SPKVU */
  853. #define WM8903_SPKVU_MASK 0x0080 /* SPKVU */
  854. #define WM8903_SPKVU_SHIFT 7 /* SPKVU */
  855. #define WM8903_SPKVU_WIDTH 1 /* SPKVU */
  856. #define WM8903_SPKRZC 0x0040 /* SPKRZC */
  857. #define WM8903_SPKRZC_MASK 0x0040 /* SPKRZC */
  858. #define WM8903_SPKRZC_SHIFT 6 /* SPKRZC */
  859. #define WM8903_SPKRZC_WIDTH 1 /* SPKRZC */
  860. #define WM8903_SPKR_VOL_MASK 0x003F /* SPKR_VOL - [5:0] */
  861. #define WM8903_SPKR_VOL_SHIFT 0 /* SPKR_VOL - [5:0] */
  862. #define WM8903_SPKR_VOL_WIDTH 6 /* SPKR_VOL - [5:0] */
  863. /*
  864. * R65 (0x41) - Analogue SPK Output Control 0
  865. */
  866. #define WM8903_SPK_DISCHARGE 0x0002 /* SPK_DISCHARGE */
  867. #define WM8903_SPK_DISCHARGE_MASK 0x0002 /* SPK_DISCHARGE */
  868. #define WM8903_SPK_DISCHARGE_SHIFT 1 /* SPK_DISCHARGE */
  869. #define WM8903_SPK_DISCHARGE_WIDTH 1 /* SPK_DISCHARGE */
  870. #define WM8903_VROI 0x0001 /* VROI */
  871. #define WM8903_VROI_MASK 0x0001 /* VROI */
  872. #define WM8903_VROI_SHIFT 0 /* VROI */
  873. #define WM8903_VROI_WIDTH 1 /* VROI */
  874. /*
  875. * R67 (0x43) - DC Servo 0
  876. */
  877. #define WM8903_DCS_MASTER_ENA 0x0010 /* DCS_MASTER_ENA */
  878. #define WM8903_DCS_MASTER_ENA_MASK 0x0010 /* DCS_MASTER_ENA */
  879. #define WM8903_DCS_MASTER_ENA_SHIFT 4 /* DCS_MASTER_ENA */
  880. #define WM8903_DCS_MASTER_ENA_WIDTH 1 /* DCS_MASTER_ENA */
  881. #define WM8903_DCS_ENA_MASK 0x000F /* DCS_ENA - [3:0] */
  882. #define WM8903_DCS_ENA_SHIFT 0 /* DCS_ENA - [3:0] */
  883. #define WM8903_DCS_ENA_WIDTH 4 /* DCS_ENA - [3:0] */
  884. /*
  885. * R69 (0x45) - DC Servo 2
  886. */
  887. #define WM8903_DCS_MODE_MASK 0x0003 /* DCS_MODE - [1:0] */
  888. #define WM8903_DCS_MODE_SHIFT 0 /* DCS_MODE - [1:0] */
  889. #define WM8903_DCS_MODE_WIDTH 2 /* DCS_MODE - [1:0] */
  890. /*
  891. * R90 (0x5A) - Analogue HP 0
  892. */
  893. #define WM8903_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */
  894. #define WM8903_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */
  895. #define WM8903_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */
  896. #define WM8903_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */
  897. #define WM8903_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */
  898. #define WM8903_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */
  899. #define WM8903_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */
  900. #define WM8903_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */
  901. #define WM8903_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */
  902. #define WM8903_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */
  903. #define WM8903_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */
  904. #define WM8903_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */
  905. #define WM8903_HPL_ENA 0x0010 /* HPL_ENA */
  906. #define WM8903_HPL_ENA_MASK 0x0010 /* HPL_ENA */
  907. #define WM8903_HPL_ENA_SHIFT 4 /* HPL_ENA */
  908. #define WM8903_HPL_ENA_WIDTH 1 /* HPL_ENA */
  909. #define WM8903_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */
  910. #define WM8903_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */
  911. #define WM8903_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */
  912. #define WM8903_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */
  913. #define WM8903_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */
  914. #define WM8903_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */
  915. #define WM8903_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */
  916. #define WM8903_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */
  917. #define WM8903_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */
  918. #define WM8903_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */
  919. #define WM8903_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */
  920. #define WM8903_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */
  921. #define WM8903_HPR_ENA 0x0001 /* HPR_ENA */
  922. #define WM8903_HPR_ENA_MASK 0x0001 /* HPR_ENA */
  923. #define WM8903_HPR_ENA_SHIFT 0 /* HPR_ENA */
  924. #define WM8903_HPR_ENA_WIDTH 1 /* HPR_ENA */
  925. /*
  926. * R94 (0x5E) - Analogue Lineout 0
  927. */
  928. #define WM8903_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */
  929. #define WM8903_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */
  930. #define WM8903_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */
  931. #define WM8903_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */
  932. #define WM8903_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */
  933. #define WM8903_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */
  934. #define WM8903_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */
  935. #define WM8903_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */
  936. #define WM8903_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */
  937. #define WM8903_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */
  938. #define WM8903_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */
  939. #define WM8903_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */
  940. #define WM8903_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */
  941. #define WM8903_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */
  942. #define WM8903_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */
  943. #define WM8903_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */
  944. #define WM8903_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */
  945. #define WM8903_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */
  946. #define WM8903_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */
  947. #define WM8903_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */
  948. #define WM8903_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */
  949. #define WM8903_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */
  950. #define WM8903_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */
  951. #define WM8903_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */
  952. #define WM8903_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */
  953. #define WM8903_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */
  954. #define WM8903_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */
  955. #define WM8903_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */
  956. #define WM8903_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */
  957. #define WM8903_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */
  958. #define WM8903_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */
  959. #define WM8903_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */
  960. /*
  961. * R98 (0x62) - Charge Pump 0
  962. */
  963. #define WM8903_CP_ENA 0x0001 /* CP_ENA */
  964. #define WM8903_CP_ENA_MASK 0x0001 /* CP_ENA */
  965. #define WM8903_CP_ENA_SHIFT 0 /* CP_ENA */
  966. #define WM8903_CP_ENA_WIDTH 1 /* CP_ENA */
  967. /*
  968. * R104 (0x68) - Class W 0
  969. */
  970. #define WM8903_CP_DYN_FREQ 0x0002 /* CP_DYN_FREQ */
  971. #define WM8903_CP_DYN_FREQ_MASK 0x0002 /* CP_DYN_FREQ */
  972. #define WM8903_CP_DYN_FREQ_SHIFT 1 /* CP_DYN_FREQ */
  973. #define WM8903_CP_DYN_FREQ_WIDTH 1 /* CP_DYN_FREQ */
  974. #define WM8903_CP_DYN_V 0x0001 /* CP_DYN_V */
  975. #define WM8903_CP_DYN_V_MASK 0x0001 /* CP_DYN_V */
  976. #define WM8903_CP_DYN_V_SHIFT 0 /* CP_DYN_V */
  977. #define WM8903_CP_DYN_V_WIDTH 1 /* CP_DYN_V */
  978. /*
  979. * R108 (0x6C) - Write Sequencer 0
  980. */
  981. #define WM8903_WSEQ_ENA 0x0100 /* WSEQ_ENA */
  982. #define WM8903_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */
  983. #define WM8903_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */
  984. #define WM8903_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  985. #define WM8903_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */
  986. #define WM8903_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */
  987. #define WM8903_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */
  988. /*
  989. * R109 (0x6D) - Write Sequencer 1
  990. */
  991. #define WM8903_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */
  992. #define WM8903_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */
  993. #define WM8903_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */
  994. #define WM8903_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */
  995. #define WM8903_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */
  996. #define WM8903_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */
  997. #define WM8903_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
  998. #define WM8903_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
  999. #define WM8903_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
  1000. /*
  1001. * R110 (0x6E) - Write Sequencer 2
  1002. */
  1003. #define WM8903_WSEQ_EOS 0x4000 /* WSEQ_EOS */
  1004. #define WM8903_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */
  1005. #define WM8903_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */
  1006. #define WM8903_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */
  1007. #define WM8903_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */
  1008. #define WM8903_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */
  1009. #define WM8903_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */
  1010. #define WM8903_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
  1011. #define WM8903_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
  1012. #define WM8903_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
  1013. /*
  1014. * R111 (0x6F) - Write Sequencer 3
  1015. */
  1016. #define WM8903_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
  1017. #define WM8903_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
  1018. #define WM8903_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
  1019. #define WM8903_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  1020. #define WM8903_WSEQ_START 0x0100 /* WSEQ_START */
  1021. #define WM8903_WSEQ_START_MASK 0x0100 /* WSEQ_START */
  1022. #define WM8903_WSEQ_START_SHIFT 8 /* WSEQ_START */
  1023. #define WM8903_WSEQ_START_WIDTH 1 /* WSEQ_START */
  1024. #define WM8903_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
  1025. #define WM8903_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
  1026. #define WM8903_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
  1027. /*
  1028. * R112 (0x70) - Write Sequencer 4
  1029. */
  1030. #define WM8903_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */
  1031. #define WM8903_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */
  1032. #define WM8903_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */
  1033. #define WM8903_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
  1034. #define WM8903_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
  1035. #define WM8903_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
  1036. #define WM8903_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  1037. /*
  1038. * R114 (0x72) - Control Interface
  1039. */
  1040. #define WM8903_MASK_WRITE_ENA 0x0001 /* MASK_WRITE_ENA */
  1041. #define WM8903_MASK_WRITE_ENA_MASK 0x0001 /* MASK_WRITE_ENA */
  1042. #define WM8903_MASK_WRITE_ENA_SHIFT 0 /* MASK_WRITE_ENA */
  1043. #define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */
  1044. /*
  1045. * R121 (0x79) - Interrupt Status 1
  1046. */
  1047. #define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */
  1048. #define WM8903_MICSHRT_EINT_MASK 0x8000 /* MICSHRT_EINT */
  1049. #define WM8903_MICSHRT_EINT_SHIFT 15 /* MICSHRT_EINT */
  1050. #define WM8903_MICSHRT_EINT_WIDTH 1 /* MICSHRT_EINT */
  1051. #define WM8903_MICDET_EINT 0x4000 /* MICDET_EINT */
  1052. #define WM8903_MICDET_EINT_MASK 0x4000 /* MICDET_EINT */
  1053. #define WM8903_MICDET_EINT_SHIFT 14 /* MICDET_EINT */
  1054. #define WM8903_MICDET_EINT_WIDTH 1 /* MICDET_EINT */
  1055. #define WM8903_WSEQ_BUSY_EINT 0x2000 /* WSEQ_BUSY_EINT */
  1056. #define WM8903_WSEQ_BUSY_EINT_MASK 0x2000 /* WSEQ_BUSY_EINT */
  1057. #define WM8903_WSEQ_BUSY_EINT_SHIFT 13 /* WSEQ_BUSY_EINT */
  1058. #define WM8903_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
  1059. #define WM8903_GP5_EINT 0x0010 /* GP5_EINT */
  1060. #define WM8903_GP5_EINT_MASK 0x0010 /* GP5_EINT */
  1061. #define WM8903_GP5_EINT_SHIFT 4 /* GP5_EINT */
  1062. #define WM8903_GP5_EINT_WIDTH 1 /* GP5_EINT */
  1063. #define WM8903_GP4_EINT 0x0008 /* GP4_EINT */
  1064. #define WM8903_GP4_EINT_MASK 0x0008 /* GP4_EINT */
  1065. #define WM8903_GP4_EINT_SHIFT 3 /* GP4_EINT */
  1066. #define WM8903_GP4_EINT_WIDTH 1 /* GP4_EINT */
  1067. #define WM8903_GP3_EINT 0x0004 /* GP3_EINT */
  1068. #define WM8903_GP3_EINT_MASK 0x0004 /* GP3_EINT */
  1069. #define WM8903_GP3_EINT_SHIFT 2 /* GP3_EINT */
  1070. #define WM8903_GP3_EINT_WIDTH 1 /* GP3_EINT */
  1071. #define WM8903_GP2_EINT 0x0002 /* GP2_EINT */
  1072. #define WM8903_GP2_EINT_MASK 0x0002 /* GP2_EINT */
  1073. #define WM8903_GP2_EINT_SHIFT 1 /* GP2_EINT */
  1074. #define WM8903_GP2_EINT_WIDTH 1 /* GP2_EINT */
  1075. #define WM8903_GP1_EINT 0x0001 /* GP1_EINT */
  1076. #define WM8903_GP1_EINT_MASK 0x0001 /* GP1_EINT */
  1077. #define WM8903_GP1_EINT_SHIFT 0 /* GP1_EINT */
  1078. #define WM8903_GP1_EINT_WIDTH 1 /* GP1_EINT */
  1079. /*
  1080. * R122 (0x7A) - Interrupt Status 1 Mask
  1081. */
  1082. #define WM8903_IM_MICSHRT_EINT 0x8000 /* IM_MICSHRT_EINT */
  1083. #define WM8903_IM_MICSHRT_EINT_MASK 0x8000 /* IM_MICSHRT_EINT */
  1084. #define WM8903_IM_MICSHRT_EINT_SHIFT 15 /* IM_MICSHRT_EINT */
  1085. #define WM8903_IM_MICSHRT_EINT_WIDTH 1 /* IM_MICSHRT_EINT */
  1086. #define WM8903_IM_MICDET_EINT 0x4000 /* IM_MICDET_EINT */
  1087. #define WM8903_IM_MICDET_EINT_MASK 0x4000 /* IM_MICDET_EINT */
  1088. #define WM8903_IM_MICDET_EINT_SHIFT 14 /* IM_MICDET_EINT */
  1089. #define WM8903_IM_MICDET_EINT_WIDTH 1 /* IM_MICDET_EINT */
  1090. #define WM8903_IM_WSEQ_BUSY_EINT 0x2000 /* IM_WSEQ_BUSY_EINT */
  1091. #define WM8903_IM_WSEQ_BUSY_EINT_MASK 0x2000 /* IM_WSEQ_BUSY_EINT */
  1092. #define WM8903_IM_WSEQ_BUSY_EINT_SHIFT 13 /* IM_WSEQ_BUSY_EINT */
  1093. #define WM8903_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
  1094. #define WM8903_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
  1095. #define WM8903_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
  1096. #define WM8903_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
  1097. #define WM8903_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
  1098. #define WM8903_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
  1099. #define WM8903_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
  1100. #define WM8903_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
  1101. #define WM8903_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
  1102. #define WM8903_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
  1103. #define WM8903_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
  1104. #define WM8903_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
  1105. #define WM8903_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
  1106. #define WM8903_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
  1107. #define WM8903_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
  1108. #define WM8903_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
  1109. #define WM8903_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
  1110. #define WM8903_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
  1111. #define WM8903_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
  1112. #define WM8903_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
  1113. #define WM8903_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
  1114. /*
  1115. * R123 (0x7B) - Interrupt Polarity 1
  1116. */
  1117. #define WM8903_MICSHRT_INV 0x8000 /* MICSHRT_INV */
  1118. #define WM8903_MICSHRT_INV_MASK 0x8000 /* MICSHRT_INV */
  1119. #define WM8903_MICSHRT_INV_SHIFT 15 /* MICSHRT_INV */
  1120. #define WM8903_MICSHRT_INV_WIDTH 1 /* MICSHRT_INV */
  1121. #define WM8903_MICDET_INV 0x4000 /* MICDET_INV */
  1122. #define WM8903_MICDET_INV_MASK 0x4000 /* MICDET_INV */
  1123. #define WM8903_MICDET_INV_SHIFT 14 /* MICDET_INV */
  1124. #define WM8903_MICDET_INV_WIDTH 1 /* MICDET_INV */
  1125. /*
  1126. * R126 (0x7E) - Interrupt Control
  1127. */
  1128. #define WM8903_IRQ_POL 0x0001 /* IRQ_POL */
  1129. #define WM8903_IRQ_POL_MASK 0x0001 /* IRQ_POL */
  1130. #define WM8903_IRQ_POL_SHIFT 0 /* IRQ_POL */
  1131. #define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */
  1132. /*
  1133. * R164 (0xA4) - Clock Rate Test 4
  1134. */
  1135. #define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */
  1136. #define WM8903_ADC_DIG_MIC_MASK 0x0200 /* ADC_DIG_MIC */
  1137. #define WM8903_ADC_DIG_MIC_SHIFT 9 /* ADC_DIG_MIC */
  1138. #define WM8903_ADC_DIG_MIC_WIDTH 1 /* ADC_DIG_MIC */
  1139. /*
  1140. * R172 (0xAC) - Analogue Output Bias 0
  1141. */
  1142. #define WM8903_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */
  1143. #define WM8903_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */
  1144. #define WM8903_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */
  1145. #endif