wm8900.c 39 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8900.c -- WM8900 ALSA Soc Audio driver
  4. *
  5. * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. *
  9. * TODO:
  10. * - Tristating.
  11. * - TDM.
  12. * - Jack detect.
  13. * - FLL source configuration, currently only MCLK is supported.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include <linux/pm.h>
  21. #include <linux/i2c.h>
  22. #include <linux/regmap.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/slab.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/soc.h>
  29. #include <sound/initval.h>
  30. #include <sound/tlv.h>
  31. #include "wm8900.h"
  32. /* WM8900 register space */
  33. #define WM8900_REG_RESET 0x0
  34. #define WM8900_REG_ID 0x0
  35. #define WM8900_REG_POWER1 0x1
  36. #define WM8900_REG_POWER2 0x2
  37. #define WM8900_REG_POWER3 0x3
  38. #define WM8900_REG_AUDIO1 0x4
  39. #define WM8900_REG_AUDIO2 0x5
  40. #define WM8900_REG_CLOCKING1 0x6
  41. #define WM8900_REG_CLOCKING2 0x7
  42. #define WM8900_REG_AUDIO3 0x8
  43. #define WM8900_REG_AUDIO4 0x9
  44. #define WM8900_REG_DACCTRL 0xa
  45. #define WM8900_REG_LDAC_DV 0xb
  46. #define WM8900_REG_RDAC_DV 0xc
  47. #define WM8900_REG_SIDETONE 0xd
  48. #define WM8900_REG_ADCCTRL 0xe
  49. #define WM8900_REG_LADC_DV 0xf
  50. #define WM8900_REG_RADC_DV 0x10
  51. #define WM8900_REG_GPIO 0x12
  52. #define WM8900_REG_INCTL 0x15
  53. #define WM8900_REG_LINVOL 0x16
  54. #define WM8900_REG_RINVOL 0x17
  55. #define WM8900_REG_INBOOSTMIX1 0x18
  56. #define WM8900_REG_INBOOSTMIX2 0x19
  57. #define WM8900_REG_ADCPATH 0x1a
  58. #define WM8900_REG_AUXBOOST 0x1b
  59. #define WM8900_REG_ADDCTL 0x1e
  60. #define WM8900_REG_FLLCTL1 0x24
  61. #define WM8900_REG_FLLCTL2 0x25
  62. #define WM8900_REG_FLLCTL3 0x26
  63. #define WM8900_REG_FLLCTL4 0x27
  64. #define WM8900_REG_FLLCTL5 0x28
  65. #define WM8900_REG_FLLCTL6 0x29
  66. #define WM8900_REG_LOUTMIXCTL1 0x2c
  67. #define WM8900_REG_ROUTMIXCTL1 0x2d
  68. #define WM8900_REG_BYPASS1 0x2e
  69. #define WM8900_REG_BYPASS2 0x2f
  70. #define WM8900_REG_AUXOUT_CTL 0x30
  71. #define WM8900_REG_LOUT1CTL 0x33
  72. #define WM8900_REG_ROUT1CTL 0x34
  73. #define WM8900_REG_LOUT2CTL 0x35
  74. #define WM8900_REG_ROUT2CTL 0x36
  75. #define WM8900_REG_HPCTL1 0x3a
  76. #define WM8900_REG_OUTBIASCTL 0x73
  77. #define WM8900_MAXREG 0x80
  78. #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
  79. #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
  80. #define WM8900_REG_ADDCTL_VMID_DIS 0x20
  81. #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
  82. #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
  83. #define WM8900_REG_ADDCTL_TEMP_SD 0x02
  84. #define WM8900_REG_GPIO_TEMP_ENA 0x2
  85. #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
  86. #define WM8900_REG_POWER1_BIAS_ENA 0x0008
  87. #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
  88. #define WM8900_REG_POWER1_FLL_ENA 0x0040
  89. #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
  90. #define WM8900_REG_POWER2_ADCL_ENA 0x0002
  91. #define WM8900_REG_POWER2_ADCR_ENA 0x0001
  92. #define WM8900_REG_POWER3_DACL_ENA 0x0002
  93. #define WM8900_REG_POWER3_DACR_ENA 0x0001
  94. #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
  95. #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
  96. #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
  97. #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
  98. #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
  99. #define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
  100. #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
  101. #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
  102. #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
  103. #define WM8900_REG_DACCTRL_MUTE 0x004
  104. #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
  105. #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
  106. #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
  107. #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
  108. #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
  109. #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
  110. #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
  111. #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
  112. #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
  113. #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
  114. #define WM8900_REG_HPCTL1_HP_SHORT 0x08
  115. #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
  116. #define WM8900_LRC_MASK 0x03ff
  117. struct wm8900_priv {
  118. struct regmap *regmap;
  119. u32 fll_in; /* FLL input frequency */
  120. u32 fll_out; /* FLL output frequency */
  121. };
  122. /*
  123. * wm8900 register cache. We can't read the entire register space and we
  124. * have slow control buses so we cache the registers.
  125. */
  126. static const struct reg_default wm8900_reg_defaults[] = {
  127. { 1, 0x0000 },
  128. { 2, 0xc000 },
  129. { 3, 0x0000 },
  130. { 4, 0x4050 },
  131. { 5, 0x4000 },
  132. { 6, 0x0008 },
  133. { 7, 0x0000 },
  134. { 8, 0x0040 },
  135. { 9, 0x0040 },
  136. { 10, 0x1004 },
  137. { 11, 0x00c0 },
  138. { 12, 0x00c0 },
  139. { 13, 0x0000 },
  140. { 14, 0x0100 },
  141. { 15, 0x00c0 },
  142. { 16, 0x00c0 },
  143. { 17, 0x0000 },
  144. { 18, 0xb001 },
  145. { 19, 0x0000 },
  146. { 20, 0x0000 },
  147. { 21, 0x0044 },
  148. { 22, 0x004c },
  149. { 23, 0x004c },
  150. { 24, 0x0044 },
  151. { 25, 0x0044 },
  152. { 26, 0x0000 },
  153. { 27, 0x0044 },
  154. { 28, 0x0000 },
  155. { 29, 0x0000 },
  156. { 30, 0x0002 },
  157. { 31, 0x0000 },
  158. { 32, 0x0000 },
  159. { 33, 0x0000 },
  160. { 34, 0x0000 },
  161. { 35, 0x0000 },
  162. { 36, 0x0008 },
  163. { 37, 0x0000 },
  164. { 38, 0x0000 },
  165. { 39, 0x0008 },
  166. { 40, 0x0097 },
  167. { 41, 0x0100 },
  168. { 42, 0x0000 },
  169. { 43, 0x0000 },
  170. { 44, 0x0050 },
  171. { 45, 0x0050 },
  172. { 46, 0x0055 },
  173. { 47, 0x0055 },
  174. { 48, 0x0055 },
  175. { 49, 0x0000 },
  176. { 50, 0x0000 },
  177. { 51, 0x0079 },
  178. { 52, 0x0079 },
  179. { 53, 0x0079 },
  180. { 54, 0x0079 },
  181. { 55, 0x0000 },
  182. };
  183. static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
  184. {
  185. switch (reg) {
  186. case WM8900_REG_ID:
  187. return true;
  188. default:
  189. return false;
  190. }
  191. }
  192. static void wm8900_reset(struct snd_soc_component *component)
  193. {
  194. snd_soc_component_write(component, WM8900_REG_RESET, 0);
  195. }
  196. static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
  197. struct snd_kcontrol *kcontrol, int event)
  198. {
  199. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  200. u16 hpctl1 = snd_soc_component_read(component, WM8900_REG_HPCTL1);
  201. switch (event) {
  202. case SND_SOC_DAPM_PRE_PMU:
  203. /* Clamp headphone outputs */
  204. hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
  205. WM8900_REG_HPCTL1_HP_CLAMP_OP;
  206. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  207. break;
  208. case SND_SOC_DAPM_POST_PMU:
  209. /* Enable the input stage */
  210. hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
  211. hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
  212. WM8900_REG_HPCTL1_HP_SHORT2 |
  213. WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
  214. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  215. msleep(400);
  216. /* Enable the output stage */
  217. hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
  218. hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
  219. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  220. /* Remove the shorts */
  221. hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
  222. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  223. hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
  224. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  225. break;
  226. case SND_SOC_DAPM_PRE_PMD:
  227. /* Short the output */
  228. hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
  229. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  230. /* Disable the output stage */
  231. hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
  232. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  233. /* Clamp the outputs and power down input */
  234. hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
  235. WM8900_REG_HPCTL1_HP_CLAMP_OP;
  236. hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
  237. snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
  238. break;
  239. case SND_SOC_DAPM_POST_PMD:
  240. /* Disable everything */
  241. snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
  242. break;
  243. default:
  244. WARN(1, "Invalid event %d\n", event);
  245. break;
  246. }
  247. return 0;
  248. }
  249. static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
  250. static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
  251. static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
  252. static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
  253. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  254. static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
  255. static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
  256. static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
  257. static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
  258. static SOC_ENUM_SINGLE_DECL(mic_bias_level,
  259. WM8900_REG_INCTL, 8, mic_bias_level_txt);
  260. static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
  261. static SOC_ENUM_SINGLE_DECL(dac_mute_rate,
  262. WM8900_REG_DACCTRL, 7, dac_mute_rate_txt);
  263. static const char *dac_deemphasis_txt[] = {
  264. "Disabled", "32kHz", "44.1kHz", "48kHz"
  265. };
  266. static SOC_ENUM_SINGLE_DECL(dac_deemphasis,
  267. WM8900_REG_DACCTRL, 4, dac_deemphasis_txt);
  268. static const char *adc_hpf_cut_txt[] = {
  269. "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
  270. };
  271. static SOC_ENUM_SINGLE_DECL(adc_hpf_cut,
  272. WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt);
  273. static const char *lr_txt[] = {
  274. "Left", "Right"
  275. };
  276. static SOC_ENUM_SINGLE_DECL(aifl_src,
  277. WM8900_REG_AUDIO1, 15, lr_txt);
  278. static SOC_ENUM_SINGLE_DECL(aifr_src,
  279. WM8900_REG_AUDIO1, 14, lr_txt);
  280. static SOC_ENUM_SINGLE_DECL(dacl_src,
  281. WM8900_REG_AUDIO2, 15, lr_txt);
  282. static SOC_ENUM_SINGLE_DECL(dacr_src,
  283. WM8900_REG_AUDIO2, 14, lr_txt);
  284. static const char *sidetone_txt[] = {
  285. "Disabled", "Left ADC", "Right ADC"
  286. };
  287. static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
  288. WM8900_REG_SIDETONE, 2, sidetone_txt);
  289. static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
  290. WM8900_REG_SIDETONE, 0, sidetone_txt);
  291. static const struct snd_kcontrol_new wm8900_snd_controls[] = {
  292. SOC_ENUM("Mic Bias Level", mic_bias_level),
  293. SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
  294. in_pga_tlv),
  295. SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
  296. SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
  297. SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
  298. in_pga_tlv),
  299. SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
  300. SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
  301. SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
  302. SOC_ENUM("DAC Mute Rate", dac_mute_rate),
  303. SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
  304. SOC_ENUM("DAC Deemphasis", dac_deemphasis),
  305. SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
  306. 12, 1, 0),
  307. SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
  308. SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
  309. SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
  310. SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
  311. adc_svol_tlv),
  312. SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
  313. adc_svol_tlv),
  314. SOC_ENUM("Left Digital Audio Source", aifl_src),
  315. SOC_ENUM("Right Digital Audio Source", aifr_src),
  316. SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
  317. dac_boost_tlv),
  318. SOC_ENUM("Left DAC Source", dacl_src),
  319. SOC_ENUM("Right DAC Source", dacr_src),
  320. SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
  321. SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
  322. SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
  323. SOC_DOUBLE_R_TLV("Digital Playback Volume",
  324. WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
  325. 1, 96, 0, dac_tlv),
  326. SOC_DOUBLE_R_TLV("Digital Capture Volume",
  327. WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
  328. SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
  329. out_mix_tlv),
  330. SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
  331. out_mix_tlv),
  332. SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
  333. out_mix_tlv),
  334. SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
  335. out_mix_tlv),
  336. SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
  337. out_mix_tlv),
  338. SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
  339. out_mix_tlv),
  340. SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
  341. out_mix_tlv),
  342. SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
  343. out_mix_tlv),
  344. SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
  345. in_boost_tlv),
  346. SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
  347. in_boost_tlv),
  348. SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
  349. in_boost_tlv),
  350. SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
  351. in_boost_tlv),
  352. SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
  353. in_boost_tlv),
  354. SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
  355. in_boost_tlv),
  356. SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
  357. 0, 63, 0, out_pga_tlv),
  358. SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
  359. 6, 1, 1),
  360. SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
  361. 7, 1, 0),
  362. SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
  363. WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
  364. 0, 63, 0, out_pga_tlv),
  365. SOC_DOUBLE_R("LINEOUT2 Switch",
  366. WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
  367. SOC_DOUBLE_R("LINEOUT2 ZC Switch",
  368. WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
  369. SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
  370. 0, 1, 1),
  371. };
  372. static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
  373. SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
  374. SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
  375. SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
  376. SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
  377. SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
  378. };
  379. static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
  380. SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
  381. SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
  382. SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
  383. SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
  384. SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
  385. };
  386. static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
  387. SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
  388. SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
  389. SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
  390. SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
  391. };
  392. static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
  393. SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
  394. SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
  395. SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
  396. SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
  397. };
  398. static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
  399. SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
  400. SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
  401. SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
  402. };
  403. static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
  404. SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
  405. SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
  406. SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
  407. };
  408. static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
  409. static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux,
  410. WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux);
  411. static const struct snd_kcontrol_new wm8900_lineout2_lp =
  412. SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
  413. static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
  414. /* Externally visible pins */
  415. SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
  416. SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
  417. SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
  418. SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
  419. SND_SOC_DAPM_OUTPUT("HP_L"),
  420. SND_SOC_DAPM_OUTPUT("HP_R"),
  421. SND_SOC_DAPM_INPUT("RINPUT1"),
  422. SND_SOC_DAPM_INPUT("LINPUT1"),
  423. SND_SOC_DAPM_INPUT("RINPUT2"),
  424. SND_SOC_DAPM_INPUT("LINPUT2"),
  425. SND_SOC_DAPM_INPUT("RINPUT3"),
  426. SND_SOC_DAPM_INPUT("LINPUT3"),
  427. SND_SOC_DAPM_INPUT("AUX"),
  428. SND_SOC_DAPM_VMID("VMID"),
  429. /* Input */
  430. SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
  431. wm8900_linpga_controls,
  432. ARRAY_SIZE(wm8900_linpga_controls)),
  433. SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
  434. wm8900_rinpga_controls,
  435. ARRAY_SIZE(wm8900_rinpga_controls)),
  436. SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
  437. wm8900_linmix_controls,
  438. ARRAY_SIZE(wm8900_linmix_controls)),
  439. SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
  440. wm8900_rinmix_controls,
  441. ARRAY_SIZE(wm8900_rinmix_controls)),
  442. SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
  443. SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
  444. SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
  445. /* Output */
  446. SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
  447. SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
  448. SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
  449. wm8900_hp_event,
  450. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  451. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  452. SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
  453. SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
  454. SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
  455. SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
  456. SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
  457. SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
  458. wm8900_loutmix_controls,
  459. ARRAY_SIZE(wm8900_loutmix_controls)),
  460. SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
  461. wm8900_routmix_controls,
  462. ARRAY_SIZE(wm8900_routmix_controls)),
  463. };
  464. /* Target, Path, Source */
  465. static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
  466. /* Inputs */
  467. {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
  468. {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
  469. {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
  470. {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
  471. {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
  472. {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
  473. {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
  474. {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
  475. {"Left Input Mixer", "AUX Switch", "AUX"},
  476. {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
  477. {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
  478. {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
  479. {"Right Input Mixer", "AUX Switch", "AUX"},
  480. {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
  481. {"ADCL", NULL, "Left Input Mixer"},
  482. {"ADCR", NULL, "Right Input Mixer"},
  483. /* Outputs */
  484. {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
  485. {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
  486. {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
  487. {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
  488. {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
  489. {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
  490. {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
  491. {"LINEOUT2L", NULL, "LINEOUT2 LP"},
  492. {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
  493. {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
  494. {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
  495. {"LINEOUT2R", NULL, "LINEOUT2 LP"},
  496. {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
  497. {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
  498. {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
  499. {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
  500. {"Left Output Mixer", "DACL Switch", "DACL"},
  501. {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
  502. {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
  503. {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
  504. {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
  505. {"Right Output Mixer", "DACR Switch", "DACR"},
  506. /* Note that the headphone output stage needs to be connected
  507. * externally to LINEOUT2 via DC blocking capacitors. Other
  508. * configurations are not supported.
  509. *
  510. * Note also that left and right headphone paths are treated as a
  511. * mono path.
  512. */
  513. {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
  514. {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
  515. {"HP_L", NULL, "Headphone Amplifier"},
  516. {"HP_R", NULL, "Headphone Amplifier"},
  517. };
  518. static int wm8900_hw_params(struct snd_pcm_substream *substream,
  519. struct snd_pcm_hw_params *params,
  520. struct snd_soc_dai *dai)
  521. {
  522. struct snd_soc_component *component = dai->component;
  523. u16 reg;
  524. reg = snd_soc_component_read(component, WM8900_REG_AUDIO1) & ~0x60;
  525. switch (params_width(params)) {
  526. case 16:
  527. break;
  528. case 20:
  529. reg |= 0x20;
  530. break;
  531. case 24:
  532. reg |= 0x40;
  533. break;
  534. case 32:
  535. reg |= 0x60;
  536. break;
  537. default:
  538. return -EINVAL;
  539. }
  540. snd_soc_component_write(component, WM8900_REG_AUDIO1, reg);
  541. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  542. reg = snd_soc_component_read(component, WM8900_REG_DACCTRL);
  543. if (params_rate(params) <= 24000)
  544. reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
  545. else
  546. reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
  547. snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
  548. }
  549. return 0;
  550. }
  551. /* FLL divisors */
  552. struct _fll_div {
  553. u16 fll_ratio;
  554. u16 fllclk_div;
  555. u16 fll_slow_lock_ref;
  556. u16 n;
  557. u16 k;
  558. };
  559. /* The size in bits of the FLL divide multiplied by 10
  560. * to allow rounding later */
  561. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  562. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  563. unsigned int Fout)
  564. {
  565. u64 Kpart;
  566. unsigned int K, Ndiv, Nmod, target;
  567. unsigned int div;
  568. if (WARN_ON(!Fout))
  569. return -EINVAL;
  570. /* The FLL must run at 90-100MHz which is then scaled down to
  571. * the output value by FLLCLK_DIV. */
  572. target = Fout;
  573. div = 1;
  574. while (target < 90000000) {
  575. div *= 2;
  576. target *= 2;
  577. }
  578. if (target > 100000000)
  579. printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
  580. " Fout=%u\n", target, Fref, Fout);
  581. if (div > 32) {
  582. printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
  583. "Fref=%u, Fout=%u, target=%u\n",
  584. div, Fref, Fout, target);
  585. return -EINVAL;
  586. }
  587. fll_div->fllclk_div = div >> 2;
  588. if (Fref < 48000)
  589. fll_div->fll_slow_lock_ref = 1;
  590. else
  591. fll_div->fll_slow_lock_ref = 0;
  592. Ndiv = target / Fref;
  593. if (Fref < 1000000)
  594. fll_div->fll_ratio = 8;
  595. else
  596. fll_div->fll_ratio = 1;
  597. fll_div->n = Ndiv / fll_div->fll_ratio;
  598. Nmod = (target / fll_div->fll_ratio) % Fref;
  599. /* Calculate fractional part - scale up so we can round. */
  600. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  601. do_div(Kpart, Fref);
  602. K = Kpart & 0xFFFFFFFF;
  603. if ((K % 10) >= 5)
  604. K += 5;
  605. /* Move down to proper range now rounding is done */
  606. fll_div->k = K / 10;
  607. if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
  608. WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
  609. return -EINVAL;
  610. return 0;
  611. }
  612. static int wm8900_set_fll(struct snd_soc_component *component,
  613. int fll_id, unsigned int freq_in, unsigned int freq_out)
  614. {
  615. struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
  616. struct _fll_div fll_div;
  617. if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
  618. return 0;
  619. /* The digital side should be disabled during any change. */
  620. snd_soc_component_update_bits(component, WM8900_REG_POWER1,
  621. WM8900_REG_POWER1_FLL_ENA, 0);
  622. /* Disable the FLL? */
  623. if (!freq_in || !freq_out) {
  624. snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
  625. WM8900_REG_CLOCKING1_MCLK_SRC, 0);
  626. snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1,
  627. WM8900_REG_FLLCTL1_OSC_ENA, 0);
  628. wm8900->fll_in = freq_in;
  629. wm8900->fll_out = freq_out;
  630. return 0;
  631. }
  632. if (fll_factors(&fll_div, freq_in, freq_out) != 0)
  633. goto reenable;
  634. wm8900->fll_in = freq_in;
  635. wm8900->fll_out = freq_out;
  636. /* The osclilator *MUST* be enabled before we enable the
  637. * digital circuit. */
  638. snd_soc_component_write(component, WM8900_REG_FLLCTL1,
  639. fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
  640. snd_soc_component_write(component, WM8900_REG_FLLCTL4, fll_div.n >> 5);
  641. snd_soc_component_write(component, WM8900_REG_FLLCTL5,
  642. (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
  643. if (fll_div.k) {
  644. snd_soc_component_write(component, WM8900_REG_FLLCTL2,
  645. (fll_div.k >> 8) | 0x100);
  646. snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
  647. } else
  648. snd_soc_component_write(component, WM8900_REG_FLLCTL2, 0);
  649. if (fll_div.fll_slow_lock_ref)
  650. snd_soc_component_write(component, WM8900_REG_FLLCTL6,
  651. WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
  652. else
  653. snd_soc_component_write(component, WM8900_REG_FLLCTL6, 0);
  654. snd_soc_component_update_bits(component, WM8900_REG_POWER1,
  655. WM8900_REG_POWER1_FLL_ENA,
  656. WM8900_REG_POWER1_FLL_ENA);
  657. reenable:
  658. snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
  659. WM8900_REG_CLOCKING1_MCLK_SRC,
  660. WM8900_REG_CLOCKING1_MCLK_SRC);
  661. return 0;
  662. }
  663. static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
  664. int source, unsigned int freq_in, unsigned int freq_out)
  665. {
  666. return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out);
  667. }
  668. static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  669. int div_id, int div)
  670. {
  671. struct snd_soc_component *component = codec_dai->component;
  672. switch (div_id) {
  673. case WM8900_BCLK_DIV:
  674. snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
  675. WM8900_REG_CLOCKING1_BCLK_MASK, div);
  676. break;
  677. case WM8900_OPCLK_DIV:
  678. snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
  679. WM8900_REG_CLOCKING1_OPCLK_MASK, div);
  680. break;
  681. case WM8900_DAC_LRCLK:
  682. snd_soc_component_update_bits(component, WM8900_REG_AUDIO4,
  683. WM8900_LRC_MASK, div);
  684. break;
  685. case WM8900_ADC_LRCLK:
  686. snd_soc_component_update_bits(component, WM8900_REG_AUDIO3,
  687. WM8900_LRC_MASK, div);
  688. break;
  689. case WM8900_DAC_CLKDIV:
  690. snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
  691. WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
  692. break;
  693. case WM8900_ADC_CLKDIV:
  694. snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
  695. WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
  696. break;
  697. case WM8900_LRCLK_MODE:
  698. snd_soc_component_update_bits(component, WM8900_REG_DACCTRL,
  699. WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
  700. break;
  701. default:
  702. return -EINVAL;
  703. }
  704. return 0;
  705. }
  706. static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
  707. unsigned int fmt)
  708. {
  709. struct snd_soc_component *component = codec_dai->component;
  710. unsigned int clocking1, aif1, aif3, aif4;
  711. clocking1 = snd_soc_component_read(component, WM8900_REG_CLOCKING1);
  712. aif1 = snd_soc_component_read(component, WM8900_REG_AUDIO1);
  713. aif3 = snd_soc_component_read(component, WM8900_REG_AUDIO3);
  714. aif4 = snd_soc_component_read(component, WM8900_REG_AUDIO4);
  715. /* set master/slave audio interface */
  716. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  717. case SND_SOC_DAIFMT_CBS_CFS:
  718. clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
  719. aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
  720. aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
  721. break;
  722. case SND_SOC_DAIFMT_CBS_CFM:
  723. clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
  724. aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
  725. aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
  726. break;
  727. case SND_SOC_DAIFMT_CBM_CFM:
  728. clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
  729. aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
  730. aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
  731. break;
  732. case SND_SOC_DAIFMT_CBM_CFS:
  733. clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
  734. aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
  735. aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
  736. break;
  737. default:
  738. return -EINVAL;
  739. }
  740. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  741. case SND_SOC_DAIFMT_DSP_A:
  742. aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
  743. aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
  744. break;
  745. case SND_SOC_DAIFMT_DSP_B:
  746. aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
  747. aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
  748. break;
  749. case SND_SOC_DAIFMT_I2S:
  750. aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
  751. aif1 |= 0x10;
  752. break;
  753. case SND_SOC_DAIFMT_RIGHT_J:
  754. aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
  755. break;
  756. case SND_SOC_DAIFMT_LEFT_J:
  757. aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
  758. aif1 |= 0x8;
  759. break;
  760. default:
  761. return -EINVAL;
  762. }
  763. /* Clock inversion */
  764. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  765. case SND_SOC_DAIFMT_DSP_A:
  766. case SND_SOC_DAIFMT_DSP_B:
  767. /* frame inversion not valid for DSP modes */
  768. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  769. case SND_SOC_DAIFMT_NB_NF:
  770. aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
  771. break;
  772. case SND_SOC_DAIFMT_IB_NF:
  773. aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
  774. break;
  775. default:
  776. return -EINVAL;
  777. }
  778. break;
  779. case SND_SOC_DAIFMT_I2S:
  780. case SND_SOC_DAIFMT_RIGHT_J:
  781. case SND_SOC_DAIFMT_LEFT_J:
  782. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  783. case SND_SOC_DAIFMT_NB_NF:
  784. aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
  785. aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
  786. break;
  787. case SND_SOC_DAIFMT_IB_IF:
  788. aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
  789. aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
  790. break;
  791. case SND_SOC_DAIFMT_IB_NF:
  792. aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
  793. aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
  794. break;
  795. case SND_SOC_DAIFMT_NB_IF:
  796. aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
  797. aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
  798. break;
  799. default:
  800. return -EINVAL;
  801. }
  802. break;
  803. default:
  804. return -EINVAL;
  805. }
  806. snd_soc_component_write(component, WM8900_REG_CLOCKING1, clocking1);
  807. snd_soc_component_write(component, WM8900_REG_AUDIO1, aif1);
  808. snd_soc_component_write(component, WM8900_REG_AUDIO3, aif3);
  809. snd_soc_component_write(component, WM8900_REG_AUDIO4, aif4);
  810. return 0;
  811. }
  812. static int wm8900_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
  813. {
  814. struct snd_soc_component *component = codec_dai->component;
  815. u16 reg;
  816. reg = snd_soc_component_read(component, WM8900_REG_DACCTRL);
  817. if (mute)
  818. reg |= WM8900_REG_DACCTRL_MUTE;
  819. else
  820. reg &= ~WM8900_REG_DACCTRL_MUTE;
  821. snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
  822. return 0;
  823. }
  824. #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  825. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
  826. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  827. #define WM8900_PCM_FORMATS \
  828. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  829. SNDRV_PCM_FMTBIT_S24_LE)
  830. static const struct snd_soc_dai_ops wm8900_dai_ops = {
  831. .hw_params = wm8900_hw_params,
  832. .set_clkdiv = wm8900_set_dai_clkdiv,
  833. .set_pll = wm8900_set_dai_pll,
  834. .set_fmt = wm8900_set_dai_fmt,
  835. .mute_stream = wm8900_mute,
  836. .no_capture_mute = 1,
  837. };
  838. static struct snd_soc_dai_driver wm8900_dai = {
  839. .name = "wm8900-hifi",
  840. .playback = {
  841. .stream_name = "HiFi Playback",
  842. .channels_min = 1,
  843. .channels_max = 2,
  844. .rates = WM8900_RATES,
  845. .formats = WM8900_PCM_FORMATS,
  846. },
  847. .capture = {
  848. .stream_name = "HiFi Capture",
  849. .channels_min = 1,
  850. .channels_max = 2,
  851. .rates = WM8900_RATES,
  852. .formats = WM8900_PCM_FORMATS,
  853. },
  854. .ops = &wm8900_dai_ops,
  855. };
  856. static int wm8900_set_bias_level(struct snd_soc_component *component,
  857. enum snd_soc_bias_level level)
  858. {
  859. u16 reg;
  860. switch (level) {
  861. case SND_SOC_BIAS_ON:
  862. /* Enable thermal shutdown */
  863. snd_soc_component_update_bits(component, WM8900_REG_GPIO,
  864. WM8900_REG_GPIO_TEMP_ENA,
  865. WM8900_REG_GPIO_TEMP_ENA);
  866. snd_soc_component_update_bits(component, WM8900_REG_ADDCTL,
  867. WM8900_REG_ADDCTL_TEMP_SD,
  868. WM8900_REG_ADDCTL_TEMP_SD);
  869. break;
  870. case SND_SOC_BIAS_PREPARE:
  871. break;
  872. case SND_SOC_BIAS_STANDBY:
  873. /* Charge capacitors if initial power up */
  874. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  875. /* STARTUP_BIAS_ENA on */
  876. snd_soc_component_write(component, WM8900_REG_POWER1,
  877. WM8900_REG_POWER1_STARTUP_BIAS_ENA);
  878. /* Startup bias mode */
  879. snd_soc_component_write(component, WM8900_REG_ADDCTL,
  880. WM8900_REG_ADDCTL_BIAS_SRC |
  881. WM8900_REG_ADDCTL_VMID_SOFTST);
  882. /* VMID 2x50k */
  883. snd_soc_component_write(component, WM8900_REG_POWER1,
  884. WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
  885. /* Allow capacitors to charge */
  886. schedule_timeout_interruptible(msecs_to_jiffies(400));
  887. /* Enable bias */
  888. snd_soc_component_write(component, WM8900_REG_POWER1,
  889. WM8900_REG_POWER1_STARTUP_BIAS_ENA |
  890. WM8900_REG_POWER1_BIAS_ENA | 0x1);
  891. snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
  892. snd_soc_component_write(component, WM8900_REG_POWER1,
  893. WM8900_REG_POWER1_BIAS_ENA | 0x1);
  894. }
  895. reg = snd_soc_component_read(component, WM8900_REG_POWER1);
  896. snd_soc_component_write(component, WM8900_REG_POWER1,
  897. (reg & WM8900_REG_POWER1_FLL_ENA) |
  898. WM8900_REG_POWER1_BIAS_ENA | 0x1);
  899. snd_soc_component_write(component, WM8900_REG_POWER2,
  900. WM8900_REG_POWER2_SYSCLK_ENA);
  901. snd_soc_component_write(component, WM8900_REG_POWER3, 0);
  902. break;
  903. case SND_SOC_BIAS_OFF:
  904. /* Startup bias enable */
  905. reg = snd_soc_component_read(component, WM8900_REG_POWER1);
  906. snd_soc_component_write(component, WM8900_REG_POWER1,
  907. reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
  908. snd_soc_component_write(component, WM8900_REG_ADDCTL,
  909. WM8900_REG_ADDCTL_BIAS_SRC |
  910. WM8900_REG_ADDCTL_VMID_SOFTST);
  911. /* Discharge caps */
  912. snd_soc_component_write(component, WM8900_REG_POWER1,
  913. WM8900_REG_POWER1_STARTUP_BIAS_ENA);
  914. schedule_timeout_interruptible(msecs_to_jiffies(500));
  915. /* Remove clamp */
  916. snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
  917. /* Power down */
  918. snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
  919. snd_soc_component_write(component, WM8900_REG_POWER1, 0);
  920. snd_soc_component_write(component, WM8900_REG_POWER2, 0);
  921. snd_soc_component_write(component, WM8900_REG_POWER3, 0);
  922. /* Need to let things settle before stopping the clock
  923. * to ensure that restart works, see "Stopping the
  924. * master clock" in the datasheet. */
  925. schedule_timeout_interruptible(msecs_to_jiffies(1));
  926. snd_soc_component_write(component, WM8900_REG_POWER2,
  927. WM8900_REG_POWER2_SYSCLK_ENA);
  928. break;
  929. }
  930. return 0;
  931. }
  932. static int wm8900_suspend(struct snd_soc_component *component)
  933. {
  934. struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
  935. int fll_out = wm8900->fll_out;
  936. int fll_in = wm8900->fll_in;
  937. int ret;
  938. /* Stop the FLL in an orderly fashion */
  939. ret = wm8900_set_fll(component, 0, 0, 0);
  940. if (ret != 0) {
  941. dev_err(component->dev, "Failed to stop FLL\n");
  942. return ret;
  943. }
  944. wm8900->fll_out = fll_out;
  945. wm8900->fll_in = fll_in;
  946. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
  947. return 0;
  948. }
  949. static int wm8900_resume(struct snd_soc_component *component)
  950. {
  951. struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
  952. int ret;
  953. wm8900_reset(component);
  954. ret = regcache_sync(wm8900->regmap);
  955. if (ret != 0) {
  956. dev_err(component->dev, "Failed to restore cache: %d\n", ret);
  957. return ret;
  958. }
  959. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  960. /* Restart the FLL? */
  961. if (wm8900->fll_out) {
  962. int fll_out = wm8900->fll_out;
  963. int fll_in = wm8900->fll_in;
  964. wm8900->fll_in = 0;
  965. wm8900->fll_out = 0;
  966. ret = wm8900_set_fll(component, 0, fll_in, fll_out);
  967. if (ret != 0) {
  968. dev_err(component->dev, "Failed to restart FLL\n");
  969. return ret;
  970. }
  971. }
  972. return 0;
  973. }
  974. static int wm8900_probe(struct snd_soc_component *component)
  975. {
  976. int reg;
  977. reg = snd_soc_component_read(component, WM8900_REG_ID);
  978. if (reg != 0x8900) {
  979. dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg);
  980. return -ENODEV;
  981. }
  982. wm8900_reset(component);
  983. /* Turn the chip on */
  984. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  985. /* Latch the volume update bits */
  986. snd_soc_component_update_bits(component, WM8900_REG_LINVOL, 0x100, 0x100);
  987. snd_soc_component_update_bits(component, WM8900_REG_RINVOL, 0x100, 0x100);
  988. snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, 0x100, 0x100);
  989. snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, 0x100, 0x100);
  990. snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, 0x100, 0x100);
  991. snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, 0x100, 0x100);
  992. snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, 0x100, 0x100);
  993. snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, 0x100, 0x100);
  994. snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, 0x100, 0x100);
  995. snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, 0x100, 0x100);
  996. /* Set the DAC and mixer output bias */
  997. snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, 0x81);
  998. return 0;
  999. }
  1000. static const struct snd_soc_component_driver soc_component_dev_wm8900 = {
  1001. .probe = wm8900_probe,
  1002. .suspend = wm8900_suspend,
  1003. .resume = wm8900_resume,
  1004. .set_bias_level = wm8900_set_bias_level,
  1005. .controls = wm8900_snd_controls,
  1006. .num_controls = ARRAY_SIZE(wm8900_snd_controls),
  1007. .dapm_widgets = wm8900_dapm_widgets,
  1008. .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
  1009. .dapm_routes = wm8900_dapm_routes,
  1010. .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
  1011. .idle_bias_on = 1,
  1012. .use_pmdown_time = 1,
  1013. .endianness = 1,
  1014. .non_legacy_dai_naming = 1,
  1015. };
  1016. static const struct regmap_config wm8900_regmap = {
  1017. .reg_bits = 8,
  1018. .val_bits = 16,
  1019. .max_register = WM8900_MAXREG,
  1020. .reg_defaults = wm8900_reg_defaults,
  1021. .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
  1022. .cache_type = REGCACHE_RBTREE,
  1023. .volatile_reg = wm8900_volatile_register,
  1024. };
  1025. #if defined(CONFIG_SPI_MASTER)
  1026. static int wm8900_spi_probe(struct spi_device *spi)
  1027. {
  1028. struct wm8900_priv *wm8900;
  1029. int ret;
  1030. wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
  1031. GFP_KERNEL);
  1032. if (wm8900 == NULL)
  1033. return -ENOMEM;
  1034. wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
  1035. if (IS_ERR(wm8900->regmap))
  1036. return PTR_ERR(wm8900->regmap);
  1037. spi_set_drvdata(spi, wm8900);
  1038. ret = devm_snd_soc_register_component(&spi->dev,
  1039. &soc_component_dev_wm8900, &wm8900_dai, 1);
  1040. return ret;
  1041. }
  1042. static int wm8900_spi_remove(struct spi_device *spi)
  1043. {
  1044. return 0;
  1045. }
  1046. static struct spi_driver wm8900_spi_driver = {
  1047. .driver = {
  1048. .name = "wm8900",
  1049. },
  1050. .probe = wm8900_spi_probe,
  1051. .remove = wm8900_spi_remove,
  1052. };
  1053. #endif /* CONFIG_SPI_MASTER */
  1054. #if IS_ENABLED(CONFIG_I2C)
  1055. static int wm8900_i2c_probe(struct i2c_client *i2c,
  1056. const struct i2c_device_id *id)
  1057. {
  1058. struct wm8900_priv *wm8900;
  1059. int ret;
  1060. wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
  1061. GFP_KERNEL);
  1062. if (wm8900 == NULL)
  1063. return -ENOMEM;
  1064. wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
  1065. if (IS_ERR(wm8900->regmap))
  1066. return PTR_ERR(wm8900->regmap);
  1067. i2c_set_clientdata(i2c, wm8900);
  1068. ret = devm_snd_soc_register_component(&i2c->dev,
  1069. &soc_component_dev_wm8900, &wm8900_dai, 1);
  1070. return ret;
  1071. }
  1072. static int wm8900_i2c_remove(struct i2c_client *client)
  1073. {
  1074. return 0;
  1075. }
  1076. static const struct i2c_device_id wm8900_i2c_id[] = {
  1077. { "wm8900", 0 },
  1078. { }
  1079. };
  1080. MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
  1081. static struct i2c_driver wm8900_i2c_driver = {
  1082. .driver = {
  1083. .name = "wm8900",
  1084. },
  1085. .probe = wm8900_i2c_probe,
  1086. .remove = wm8900_i2c_remove,
  1087. .id_table = wm8900_i2c_id,
  1088. };
  1089. #endif
  1090. static int __init wm8900_modinit(void)
  1091. {
  1092. int ret = 0;
  1093. #if IS_ENABLED(CONFIG_I2C)
  1094. ret = i2c_add_driver(&wm8900_i2c_driver);
  1095. if (ret != 0) {
  1096. printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
  1097. ret);
  1098. }
  1099. #endif
  1100. #if defined(CONFIG_SPI_MASTER)
  1101. ret = spi_register_driver(&wm8900_spi_driver);
  1102. if (ret != 0) {
  1103. printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
  1104. ret);
  1105. }
  1106. #endif
  1107. return ret;
  1108. }
  1109. module_init(wm8900_modinit);
  1110. static void __exit wm8900_exit(void)
  1111. {
  1112. #if IS_ENABLED(CONFIG_I2C)
  1113. i2c_del_driver(&wm8900_i2c_driver);
  1114. #endif
  1115. #if defined(CONFIG_SPI_MASTER)
  1116. spi_unregister_driver(&wm8900_spi_driver);
  1117. #endif
  1118. }
  1119. module_exit(wm8900_exit);
  1120. MODULE_DESCRIPTION("ASoC WM8900 driver");
  1121. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
  1122. MODULE_LICENSE("GPL");