wm8737.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8737.c -- WM8737 ALSA SoC Audio driver
  4. *
  5. * Copyright 2010 Wolfson Microelectronics plc
  6. *
  7. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/pm.h>
  14. #include <linux/i2c.h>
  15. #include <linux/regmap.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/slab.h>
  19. #include <linux/of_device.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/soc-dapm.h>
  25. #include <sound/initval.h>
  26. #include <sound/tlv.h>
  27. #include "wm8737.h"
  28. #define WM8737_NUM_SUPPLIES 4
  29. static const char *wm8737_supply_names[WM8737_NUM_SUPPLIES] = {
  30. "DCVDD",
  31. "DBVDD",
  32. "AVDD",
  33. "MVDD",
  34. };
  35. /* codec private data */
  36. struct wm8737_priv {
  37. struct regmap *regmap;
  38. struct regulator_bulk_data supplies[WM8737_NUM_SUPPLIES];
  39. unsigned int mclk;
  40. };
  41. static const struct reg_default wm8737_reg_defaults[] = {
  42. { 0, 0x00C3 }, /* R0 - Left PGA volume */
  43. { 1, 0x00C3 }, /* R1 - Right PGA volume */
  44. { 2, 0x0007 }, /* R2 - AUDIO path L */
  45. { 3, 0x0007 }, /* R3 - AUDIO path R */
  46. { 4, 0x0000 }, /* R4 - 3D Enhance */
  47. { 5, 0x0000 }, /* R5 - ADC Control */
  48. { 6, 0x0000 }, /* R6 - Power Management */
  49. { 7, 0x000A }, /* R7 - Audio Format */
  50. { 8, 0x0000 }, /* R8 - Clocking */
  51. { 9, 0x000F }, /* R9 - MIC Preamp Control */
  52. { 10, 0x0003 }, /* R10 - Misc Bias Control */
  53. { 11, 0x0000 }, /* R11 - Noise Gate */
  54. { 12, 0x007C }, /* R12 - ALC1 */
  55. { 13, 0x0000 }, /* R13 - ALC2 */
  56. { 14, 0x0032 }, /* R14 - ALC3 */
  57. };
  58. static bool wm8737_volatile(struct device *dev, unsigned int reg)
  59. {
  60. switch (reg) {
  61. case WM8737_RESET:
  62. return true;
  63. default:
  64. return false;
  65. }
  66. }
  67. static int wm8737_reset(struct snd_soc_component *component)
  68. {
  69. return snd_soc_component_write(component, WM8737_RESET, 0);
  70. }
  71. static const DECLARE_TLV_DB_RANGE(micboost_tlv,
  72. 0, 0, TLV_DB_SCALE_ITEM(1300, 0, 0),
  73. 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
  74. 2, 2, TLV_DB_SCALE_ITEM(2800, 0, 0),
  75. 3, 3, TLV_DB_SCALE_ITEM(3300, 0, 0)
  76. );
  77. static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1);
  78. static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0);
  79. static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0);
  80. static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -1200, 600, 0);
  81. static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -1800, 100, 0);
  82. static const char *micbias_enum_text[] = {
  83. "25%",
  84. "50%",
  85. "75%",
  86. "100%",
  87. };
  88. static SOC_ENUM_SINGLE_DECL(micbias_enum,
  89. WM8737_MIC_PREAMP_CONTROL, 0, micbias_enum_text);
  90. static const char *low_cutoff_text[] = {
  91. "Low", "High"
  92. };
  93. static SOC_ENUM_SINGLE_DECL(low_3d,
  94. WM8737_3D_ENHANCE, 6, low_cutoff_text);
  95. static const char *high_cutoff_text[] = {
  96. "High", "Low"
  97. };
  98. static SOC_ENUM_SINGLE_DECL(high_3d,
  99. WM8737_3D_ENHANCE, 5, high_cutoff_text);
  100. static const char *alc_fn_text[] = {
  101. "Disabled", "Right", "Left", "Stereo"
  102. };
  103. static SOC_ENUM_SINGLE_DECL(alc_fn,
  104. WM8737_ALC1, 7, alc_fn_text);
  105. static const char *alc_hold_text[] = {
  106. "0", "2.67ms", "5.33ms", "10.66ms", "21.32ms", "42.64ms", "85.28ms",
  107. "170.56ms", "341.12ms", "682.24ms", "1.364s", "2.728s", "5.458s",
  108. "10.916s", "21.832s", "43.691s"
  109. };
  110. static SOC_ENUM_SINGLE_DECL(alc_hold,
  111. WM8737_ALC2, 0, alc_hold_text);
  112. static const char *alc_atk_text[] = {
  113. "8.4ms", "16.8ms", "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms",
  114. "1.075s", "2.15s", "4.3s", "8.6s"
  115. };
  116. static SOC_ENUM_SINGLE_DECL(alc_atk,
  117. WM8737_ALC3, 0, alc_atk_text);
  118. static const char *alc_dcy_text[] = {
  119. "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", "1.075s", "2.15s",
  120. "4.3s", "8.6s", "17.2s", "34.41s"
  121. };
  122. static SOC_ENUM_SINGLE_DECL(alc_dcy,
  123. WM8737_ALC3, 4, alc_dcy_text);
  124. static const struct snd_kcontrol_new wm8737_snd_controls[] = {
  125. SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
  126. 6, 3, 0, micboost_tlv),
  127. SOC_DOUBLE_R("Mic Boost Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
  128. 4, 1, 0),
  129. SOC_DOUBLE("Mic ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
  130. 3, 1, 0),
  131. SOC_DOUBLE_R_TLV("Capture Volume", WM8737_LEFT_PGA_VOLUME,
  132. WM8737_RIGHT_PGA_VOLUME, 0, 255, 0, pga_tlv),
  133. SOC_DOUBLE("Capture ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
  134. 2, 1, 0),
  135. SOC_DOUBLE("INPUT1 DC Bias Switch", WM8737_MISC_BIAS_CONTROL, 0, 1, 1, 0),
  136. SOC_ENUM("Mic PGA Bias", micbias_enum),
  137. SOC_SINGLE("ADC Low Power Switch", WM8737_ADC_CONTROL, 2, 1, 0),
  138. SOC_SINGLE("High Pass Filter Switch", WM8737_ADC_CONTROL, 0, 1, 1),
  139. SOC_DOUBLE("Polarity Invert Switch", WM8737_ADC_CONTROL, 5, 6, 1, 0),
  140. SOC_SINGLE("3D Switch", WM8737_3D_ENHANCE, 0, 1, 0),
  141. SOC_SINGLE("3D Depth", WM8737_3D_ENHANCE, 1, 15, 0),
  142. SOC_ENUM("3D Low Cut-off", low_3d),
  143. SOC_ENUM("3D High Cut-off", high_3d),
  144. SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv),
  145. SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0),
  146. SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0,
  147. ng_tlv),
  148. SOC_ENUM("ALC", alc_fn),
  149. SOC_SINGLE_TLV("ALC Max Gain Volume", WM8737_ALC1, 4, 7, 0, alc_max_tlv),
  150. SOC_SINGLE_TLV("ALC Target Volume", WM8737_ALC1, 0, 15, 0, alc_target_tlv),
  151. SOC_ENUM("ALC Hold Time", alc_hold),
  152. SOC_SINGLE("ALC ZC Switch", WM8737_ALC2, 4, 1, 0),
  153. SOC_ENUM("ALC Attack Time", alc_atk),
  154. SOC_ENUM("ALC Decay Time", alc_dcy),
  155. };
  156. static const char *linsel_text[] = {
  157. "LINPUT1", "LINPUT2", "LINPUT3", "LINPUT1 DC",
  158. };
  159. static SOC_ENUM_SINGLE_DECL(linsel_enum,
  160. WM8737_AUDIO_PATH_L, 7, linsel_text);
  161. static const struct snd_kcontrol_new linsel_mux =
  162. SOC_DAPM_ENUM("LINSEL", linsel_enum);
  163. static const char *rinsel_text[] = {
  164. "RINPUT1", "RINPUT2", "RINPUT3", "RINPUT1 DC",
  165. };
  166. static SOC_ENUM_SINGLE_DECL(rinsel_enum,
  167. WM8737_AUDIO_PATH_R, 7, rinsel_text);
  168. static const struct snd_kcontrol_new rinsel_mux =
  169. SOC_DAPM_ENUM("RINSEL", rinsel_enum);
  170. static const char *bypass_text[] = {
  171. "Direct", "Preamp"
  172. };
  173. static SOC_ENUM_SINGLE_DECL(lbypass_enum,
  174. WM8737_MIC_PREAMP_CONTROL, 2, bypass_text);
  175. static const struct snd_kcontrol_new lbypass_mux =
  176. SOC_DAPM_ENUM("Left Bypass", lbypass_enum);
  177. static SOC_ENUM_SINGLE_DECL(rbypass_enum,
  178. WM8737_MIC_PREAMP_CONTROL, 3, bypass_text);
  179. static const struct snd_kcontrol_new rbypass_mux =
  180. SOC_DAPM_ENUM("Left Bypass", rbypass_enum);
  181. static const struct snd_soc_dapm_widget wm8737_dapm_widgets[] = {
  182. SND_SOC_DAPM_INPUT("LINPUT1"),
  183. SND_SOC_DAPM_INPUT("LINPUT2"),
  184. SND_SOC_DAPM_INPUT("LINPUT3"),
  185. SND_SOC_DAPM_INPUT("RINPUT1"),
  186. SND_SOC_DAPM_INPUT("RINPUT2"),
  187. SND_SOC_DAPM_INPUT("RINPUT3"),
  188. SND_SOC_DAPM_INPUT("LACIN"),
  189. SND_SOC_DAPM_INPUT("RACIN"),
  190. SND_SOC_DAPM_MUX("LINSEL", SND_SOC_NOPM, 0, 0, &linsel_mux),
  191. SND_SOC_DAPM_MUX("RINSEL", SND_SOC_NOPM, 0, 0, &rinsel_mux),
  192. SND_SOC_DAPM_MUX("Left Preamp Mux", SND_SOC_NOPM, 0, 0, &lbypass_mux),
  193. SND_SOC_DAPM_MUX("Right Preamp Mux", SND_SOC_NOPM, 0, 0, &rbypass_mux),
  194. SND_SOC_DAPM_PGA("PGAL", WM8737_POWER_MANAGEMENT, 5, 0, NULL, 0),
  195. SND_SOC_DAPM_PGA("PGAR", WM8737_POWER_MANAGEMENT, 4, 0, NULL, 0),
  196. SND_SOC_DAPM_DAC("ADCL", NULL, WM8737_POWER_MANAGEMENT, 3, 0),
  197. SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0),
  198. SND_SOC_DAPM_AIF_OUT("AIF", "Capture", 0, WM8737_POWER_MANAGEMENT, 6, 0),
  199. };
  200. static const struct snd_soc_dapm_route intercon[] = {
  201. { "LINSEL", "LINPUT1", "LINPUT1" },
  202. { "LINSEL", "LINPUT2", "LINPUT2" },
  203. { "LINSEL", "LINPUT3", "LINPUT3" },
  204. { "LINSEL", "LINPUT1 DC", "LINPUT1" },
  205. { "RINSEL", "RINPUT1", "RINPUT1" },
  206. { "RINSEL", "RINPUT2", "RINPUT2" },
  207. { "RINSEL", "RINPUT3", "RINPUT3" },
  208. { "RINSEL", "RINPUT1 DC", "RINPUT1" },
  209. { "Left Preamp Mux", "Preamp", "LINSEL" },
  210. { "Left Preamp Mux", "Direct", "LACIN" },
  211. { "Right Preamp Mux", "Preamp", "RINSEL" },
  212. { "Right Preamp Mux", "Direct", "RACIN" },
  213. { "PGAL", NULL, "Left Preamp Mux" },
  214. { "PGAR", NULL, "Right Preamp Mux" },
  215. { "ADCL", NULL, "PGAL" },
  216. { "ADCR", NULL, "PGAR" },
  217. { "AIF", NULL, "ADCL" },
  218. { "AIF", NULL, "ADCR" },
  219. };
  220. /* codec mclk clock divider coefficients */
  221. static const struct {
  222. u32 mclk;
  223. u32 rate;
  224. u8 usb;
  225. u8 sr;
  226. } coeff_div[] = {
  227. { 12288000, 8000, 0, 0x4 },
  228. { 12288000, 12000, 0, 0x8 },
  229. { 12288000, 16000, 0, 0xa },
  230. { 12288000, 24000, 0, 0x1c },
  231. { 12288000, 32000, 0, 0xc },
  232. { 12288000, 48000, 0, 0 },
  233. { 12288000, 96000, 0, 0xe },
  234. { 11289600, 8000, 0, 0x14 },
  235. { 11289600, 11025, 0, 0x18 },
  236. { 11289600, 22050, 0, 0x1a },
  237. { 11289600, 44100, 0, 0x10 },
  238. { 11289600, 88200, 0, 0x1e },
  239. { 18432000, 8000, 0, 0x5 },
  240. { 18432000, 12000, 0, 0x9 },
  241. { 18432000, 16000, 0, 0xb },
  242. { 18432000, 24000, 0, 0x1b },
  243. { 18432000, 32000, 0, 0xd },
  244. { 18432000, 48000, 0, 0x1 },
  245. { 18432000, 96000, 0, 0x1f },
  246. { 16934400, 8000, 0, 0x15 },
  247. { 16934400, 11025, 0, 0x19 },
  248. { 16934400, 22050, 0, 0x1b },
  249. { 16934400, 44100, 0, 0x11 },
  250. { 16934400, 88200, 0, 0x1f },
  251. { 12000000, 8000, 1, 0x4 },
  252. { 12000000, 11025, 1, 0x19 },
  253. { 12000000, 12000, 1, 0x8 },
  254. { 12000000, 16000, 1, 0xa },
  255. { 12000000, 22050, 1, 0x1b },
  256. { 12000000, 24000, 1, 0x1c },
  257. { 12000000, 32000, 1, 0xc },
  258. { 12000000, 44100, 1, 0x11 },
  259. { 12000000, 48000, 1, 0x0 },
  260. { 12000000, 88200, 1, 0x1f },
  261. { 12000000, 96000, 1, 0xe },
  262. };
  263. static int wm8737_hw_params(struct snd_pcm_substream *substream,
  264. struct snd_pcm_hw_params *params,
  265. struct snd_soc_dai *dai)
  266. {
  267. struct snd_soc_component *component = dai->component;
  268. struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
  269. int i;
  270. u16 clocking = 0;
  271. u16 af = 0;
  272. for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
  273. if (coeff_div[i].rate != params_rate(params))
  274. continue;
  275. if (coeff_div[i].mclk == wm8737->mclk)
  276. break;
  277. if (coeff_div[i].mclk == wm8737->mclk * 2) {
  278. clocking |= WM8737_CLKDIV2;
  279. break;
  280. }
  281. }
  282. if (i == ARRAY_SIZE(coeff_div)) {
  283. dev_err(component->dev, "%dHz MCLK can't support %dHz\n",
  284. wm8737->mclk, params_rate(params));
  285. return -EINVAL;
  286. }
  287. clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT);
  288. switch (params_width(params)) {
  289. case 16:
  290. break;
  291. case 20:
  292. af |= 0x8;
  293. break;
  294. case 24:
  295. af |= 0x10;
  296. break;
  297. case 32:
  298. af |= 0x18;
  299. break;
  300. default:
  301. return -EINVAL;
  302. }
  303. snd_soc_component_update_bits(component, WM8737_AUDIO_FORMAT, WM8737_WL_MASK, af);
  304. snd_soc_component_update_bits(component, WM8737_CLOCKING,
  305. WM8737_USB_MODE | WM8737_CLKDIV2 | WM8737_SR_MASK,
  306. clocking);
  307. return 0;
  308. }
  309. static int wm8737_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  310. int clk_id, unsigned int freq, int dir)
  311. {
  312. struct snd_soc_component *component = codec_dai->component;
  313. struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
  314. int i;
  315. for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
  316. if (freq == coeff_div[i].mclk ||
  317. freq == coeff_div[i].mclk * 2) {
  318. wm8737->mclk = freq;
  319. return 0;
  320. }
  321. }
  322. dev_err(component->dev, "MCLK rate %dHz not supported\n", freq);
  323. return -EINVAL;
  324. }
  325. static int wm8737_set_dai_fmt(struct snd_soc_dai *codec_dai,
  326. unsigned int fmt)
  327. {
  328. struct snd_soc_component *component = codec_dai->component;
  329. u16 af = 0;
  330. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  331. case SND_SOC_DAIFMT_CBM_CFM:
  332. af |= WM8737_MS;
  333. break;
  334. case SND_SOC_DAIFMT_CBS_CFS:
  335. break;
  336. default:
  337. return -EINVAL;
  338. }
  339. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  340. case SND_SOC_DAIFMT_I2S:
  341. af |= 0x2;
  342. break;
  343. case SND_SOC_DAIFMT_RIGHT_J:
  344. break;
  345. case SND_SOC_DAIFMT_LEFT_J:
  346. af |= 0x1;
  347. break;
  348. case SND_SOC_DAIFMT_DSP_A:
  349. af |= 0x3;
  350. break;
  351. case SND_SOC_DAIFMT_DSP_B:
  352. af |= 0x13;
  353. break;
  354. default:
  355. return -EINVAL;
  356. }
  357. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  358. case SND_SOC_DAIFMT_NB_NF:
  359. break;
  360. case SND_SOC_DAIFMT_NB_IF:
  361. af |= WM8737_LRP;
  362. break;
  363. default:
  364. return -EINVAL;
  365. }
  366. snd_soc_component_update_bits(component, WM8737_AUDIO_FORMAT,
  367. WM8737_FORMAT_MASK | WM8737_LRP | WM8737_MS, af);
  368. return 0;
  369. }
  370. static int wm8737_set_bias_level(struct snd_soc_component *component,
  371. enum snd_soc_bias_level level)
  372. {
  373. struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
  374. int ret;
  375. switch (level) {
  376. case SND_SOC_BIAS_ON:
  377. break;
  378. case SND_SOC_BIAS_PREPARE:
  379. /* VMID at 2*75k */
  380. snd_soc_component_update_bits(component, WM8737_MISC_BIAS_CONTROL,
  381. WM8737_VMIDSEL_MASK, 0);
  382. break;
  383. case SND_SOC_BIAS_STANDBY:
  384. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  385. ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
  386. wm8737->supplies);
  387. if (ret != 0) {
  388. dev_err(component->dev,
  389. "Failed to enable supplies: %d\n",
  390. ret);
  391. return ret;
  392. }
  393. regcache_sync(wm8737->regmap);
  394. /* Fast VMID ramp at 2*2.5k */
  395. snd_soc_component_update_bits(component, WM8737_MISC_BIAS_CONTROL,
  396. WM8737_VMIDSEL_MASK,
  397. 2 << WM8737_VMIDSEL_SHIFT);
  398. /* Bring VMID up */
  399. snd_soc_component_update_bits(component, WM8737_POWER_MANAGEMENT,
  400. WM8737_VMID_MASK |
  401. WM8737_VREF_MASK,
  402. WM8737_VMID_MASK |
  403. WM8737_VREF_MASK);
  404. msleep(500);
  405. }
  406. /* VMID at 2*300k */
  407. snd_soc_component_update_bits(component, WM8737_MISC_BIAS_CONTROL,
  408. WM8737_VMIDSEL_MASK,
  409. 1 << WM8737_VMIDSEL_SHIFT);
  410. break;
  411. case SND_SOC_BIAS_OFF:
  412. snd_soc_component_update_bits(component, WM8737_POWER_MANAGEMENT,
  413. WM8737_VMID_MASK | WM8737_VREF_MASK, 0);
  414. regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies),
  415. wm8737->supplies);
  416. break;
  417. }
  418. return 0;
  419. }
  420. #define WM8737_RATES SNDRV_PCM_RATE_8000_96000
  421. #define WM8737_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  422. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  423. static const struct snd_soc_dai_ops wm8737_dai_ops = {
  424. .hw_params = wm8737_hw_params,
  425. .set_sysclk = wm8737_set_dai_sysclk,
  426. .set_fmt = wm8737_set_dai_fmt,
  427. };
  428. static struct snd_soc_dai_driver wm8737_dai = {
  429. .name = "wm8737",
  430. .capture = {
  431. .stream_name = "Capture",
  432. .channels_min = 2, /* Mono modes not yet supported */
  433. .channels_max = 2,
  434. .rates = WM8737_RATES,
  435. .formats = WM8737_FORMATS,
  436. },
  437. .ops = &wm8737_dai_ops,
  438. };
  439. static int wm8737_probe(struct snd_soc_component *component)
  440. {
  441. struct wm8737_priv *wm8737 = snd_soc_component_get_drvdata(component);
  442. int ret;
  443. ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
  444. wm8737->supplies);
  445. if (ret != 0) {
  446. dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
  447. goto err_get;
  448. }
  449. ret = wm8737_reset(component);
  450. if (ret < 0) {
  451. dev_err(component->dev, "Failed to issue reset\n");
  452. goto err_enable;
  453. }
  454. snd_soc_component_update_bits(component, WM8737_LEFT_PGA_VOLUME, WM8737_LVU,
  455. WM8737_LVU);
  456. snd_soc_component_update_bits(component, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU,
  457. WM8737_RVU);
  458. snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
  459. /* Bias level configuration will have done an extra enable */
  460. regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
  461. return 0;
  462. err_enable:
  463. regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
  464. err_get:
  465. return ret;
  466. }
  467. static const struct snd_soc_component_driver soc_component_dev_wm8737 = {
  468. .probe = wm8737_probe,
  469. .set_bias_level = wm8737_set_bias_level,
  470. .controls = wm8737_snd_controls,
  471. .num_controls = ARRAY_SIZE(wm8737_snd_controls),
  472. .dapm_widgets = wm8737_dapm_widgets,
  473. .num_dapm_widgets = ARRAY_SIZE(wm8737_dapm_widgets),
  474. .dapm_routes = intercon,
  475. .num_dapm_routes = ARRAY_SIZE(intercon),
  476. .suspend_bias_off = 1,
  477. .idle_bias_on = 1,
  478. .use_pmdown_time = 1,
  479. .endianness = 1,
  480. .non_legacy_dai_naming = 1,
  481. };
  482. static const struct of_device_id wm8737_of_match[] = {
  483. { .compatible = "wlf,wm8737", },
  484. { }
  485. };
  486. MODULE_DEVICE_TABLE(of, wm8737_of_match);
  487. static const struct regmap_config wm8737_regmap = {
  488. .reg_bits = 7,
  489. .val_bits = 9,
  490. .max_register = WM8737_MAX_REGISTER,
  491. .reg_defaults = wm8737_reg_defaults,
  492. .num_reg_defaults = ARRAY_SIZE(wm8737_reg_defaults),
  493. .cache_type = REGCACHE_RBTREE,
  494. .volatile_reg = wm8737_volatile,
  495. };
  496. #if IS_ENABLED(CONFIG_I2C)
  497. static int wm8737_i2c_probe(struct i2c_client *i2c,
  498. const struct i2c_device_id *id)
  499. {
  500. struct wm8737_priv *wm8737;
  501. int ret, i;
  502. wm8737 = devm_kzalloc(&i2c->dev, sizeof(struct wm8737_priv),
  503. GFP_KERNEL);
  504. if (wm8737 == NULL)
  505. return -ENOMEM;
  506. for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
  507. wm8737->supplies[i].supply = wm8737_supply_names[i];
  508. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8737->supplies),
  509. wm8737->supplies);
  510. if (ret != 0) {
  511. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  512. return ret;
  513. }
  514. wm8737->regmap = devm_regmap_init_i2c(i2c, &wm8737_regmap);
  515. if (IS_ERR(wm8737->regmap))
  516. return PTR_ERR(wm8737->regmap);
  517. i2c_set_clientdata(i2c, wm8737);
  518. ret = devm_snd_soc_register_component(&i2c->dev,
  519. &soc_component_dev_wm8737, &wm8737_dai, 1);
  520. return ret;
  521. }
  522. static const struct i2c_device_id wm8737_i2c_id[] = {
  523. { "wm8737", 0 },
  524. { }
  525. };
  526. MODULE_DEVICE_TABLE(i2c, wm8737_i2c_id);
  527. static struct i2c_driver wm8737_i2c_driver = {
  528. .driver = {
  529. .name = "wm8737",
  530. .of_match_table = wm8737_of_match,
  531. },
  532. .probe = wm8737_i2c_probe,
  533. .id_table = wm8737_i2c_id,
  534. };
  535. #endif
  536. #if defined(CONFIG_SPI_MASTER)
  537. static int wm8737_spi_probe(struct spi_device *spi)
  538. {
  539. struct wm8737_priv *wm8737;
  540. int ret, i;
  541. wm8737 = devm_kzalloc(&spi->dev, sizeof(struct wm8737_priv),
  542. GFP_KERNEL);
  543. if (wm8737 == NULL)
  544. return -ENOMEM;
  545. for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
  546. wm8737->supplies[i].supply = wm8737_supply_names[i];
  547. ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(wm8737->supplies),
  548. wm8737->supplies);
  549. if (ret != 0) {
  550. dev_err(&spi->dev, "Failed to request supplies: %d\n", ret);
  551. return ret;
  552. }
  553. wm8737->regmap = devm_regmap_init_spi(spi, &wm8737_regmap);
  554. if (IS_ERR(wm8737->regmap))
  555. return PTR_ERR(wm8737->regmap);
  556. spi_set_drvdata(spi, wm8737);
  557. ret = devm_snd_soc_register_component(&spi->dev,
  558. &soc_component_dev_wm8737, &wm8737_dai, 1);
  559. return ret;
  560. }
  561. static struct spi_driver wm8737_spi_driver = {
  562. .driver = {
  563. .name = "wm8737",
  564. .of_match_table = wm8737_of_match,
  565. },
  566. .probe = wm8737_spi_probe,
  567. };
  568. #endif /* CONFIG_SPI_MASTER */
  569. static int __init wm8737_modinit(void)
  570. {
  571. int ret;
  572. #if IS_ENABLED(CONFIG_I2C)
  573. ret = i2c_add_driver(&wm8737_i2c_driver);
  574. if (ret != 0) {
  575. printk(KERN_ERR "Failed to register WM8737 I2C driver: %d\n",
  576. ret);
  577. }
  578. #endif
  579. #if defined(CONFIG_SPI_MASTER)
  580. ret = spi_register_driver(&wm8737_spi_driver);
  581. if (ret != 0) {
  582. printk(KERN_ERR "Failed to register WM8737 SPI driver: %d\n",
  583. ret);
  584. }
  585. #endif
  586. return 0;
  587. }
  588. module_init(wm8737_modinit);
  589. static void __exit wm8737_exit(void)
  590. {
  591. #if defined(CONFIG_SPI_MASTER)
  592. spi_unregister_driver(&wm8737_spi_driver);
  593. #endif
  594. #if IS_ENABLED(CONFIG_I2C)
  595. i2c_del_driver(&wm8737_i2c_driver);
  596. #endif
  597. }
  598. module_exit(wm8737_exit);
  599. MODULE_DESCRIPTION("ASoC WM8737 driver");
  600. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  601. MODULE_LICENSE("GPL");