wm8400.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * wm8400.c -- WM8400 ALSA Soc Audio driver
  4. *
  5. * Copyright 2008-11 Wolfson Microelectronics PLC.
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/moduleparam.h>
  10. #include <linux/kernel.h>
  11. #include <linux/slab.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/mfd/wm8400-audio.h>
  18. #include <linux/mfd/wm8400-private.h>
  19. #include <linux/mfd/core.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <sound/initval.h>
  25. #include <sound/tlv.h>
  26. #include "wm8400.h"
  27. static struct regulator_bulk_data power[] = {
  28. {
  29. .supply = "I2S1VDD",
  30. },
  31. {
  32. .supply = "I2S2VDD",
  33. },
  34. {
  35. .supply = "DCVDD",
  36. },
  37. {
  38. .supply = "AVDD",
  39. },
  40. {
  41. .supply = "FLLVDD",
  42. },
  43. {
  44. .supply = "HPVDD",
  45. },
  46. {
  47. .supply = "SPKVDD",
  48. },
  49. };
  50. /* codec private data */
  51. struct wm8400_priv {
  52. struct wm8400 *wm8400;
  53. u16 fake_register;
  54. unsigned int sysclk;
  55. unsigned int pcmclk;
  56. int fll_in, fll_out;
  57. };
  58. static void wm8400_component_reset(struct snd_soc_component *component)
  59. {
  60. struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
  61. wm8400_reset_codec_reg_cache(wm8400->wm8400);
  62. }
  63. static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
  64. static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
  65. static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
  66. static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
  67. static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
  68. static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
  69. static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
  70. struct snd_ctl_elem_value *ucontrol)
  71. {
  72. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  73. struct soc_mixer_control *mc =
  74. (struct soc_mixer_control *)kcontrol->private_value;
  75. int reg = mc->reg;
  76. int ret;
  77. u16 val;
  78. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  79. if (ret < 0)
  80. return ret;
  81. /* now hit the volume update bits (always bit 8) */
  82. val = snd_soc_component_read(component, reg);
  83. return snd_soc_component_write(component, reg, val | 0x0100);
  84. }
  85. #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
  86. SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
  87. snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
  88. static const char *wm8400_digital_sidetone[] =
  89. {"None", "Left ADC", "Right ADC", "Reserved"};
  90. static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
  91. WM8400_DIGITAL_SIDE_TONE,
  92. WM8400_ADC_TO_DACL_SHIFT,
  93. wm8400_digital_sidetone);
  94. static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
  95. WM8400_DIGITAL_SIDE_TONE,
  96. WM8400_ADC_TO_DACR_SHIFT,
  97. wm8400_digital_sidetone);
  98. static const char *wm8400_adcmode[] =
  99. {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
  100. static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
  101. WM8400_ADC_CTRL,
  102. WM8400_ADC_HPF_CUT_SHIFT,
  103. wm8400_adcmode);
  104. static const struct snd_kcontrol_new wm8400_snd_controls[] = {
  105. /* INMIXL */
  106. SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
  107. 1, 0),
  108. SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
  109. 1, 0),
  110. /* INMIXR */
  111. SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
  112. 1, 0),
  113. SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
  114. 1, 0),
  115. /* LOMIX */
  116. SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
  117. WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
  118. SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
  119. WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
  120. SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
  121. WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
  122. SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
  123. WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
  124. SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
  125. WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
  126. SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
  127. WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
  128. /* ROMIX */
  129. SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
  130. WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
  131. SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
  132. WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
  133. SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
  134. WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
  135. SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
  136. WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
  137. SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
  138. WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
  139. SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
  140. WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
  141. /* LOUT */
  142. WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
  143. WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
  144. SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
  145. /* ROUT */
  146. WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
  147. WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
  148. SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
  149. /* LOPGA */
  150. WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
  151. WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
  152. SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
  153. WM8400_LOPGAZC_SHIFT, 1, 0),
  154. /* ROPGA */
  155. WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
  156. WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
  157. SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
  158. WM8400_ROPGAZC_SHIFT, 1, 0),
  159. SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
  160. WM8400_LONMUTE_SHIFT, 1, 0),
  161. SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
  162. WM8400_LOPMUTE_SHIFT, 1, 0),
  163. SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
  164. WM8400_LOATTN_SHIFT, 1, 0),
  165. SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
  166. WM8400_RONMUTE_SHIFT, 1, 0),
  167. SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
  168. WM8400_ROPMUTE_SHIFT, 1, 0),
  169. SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
  170. WM8400_ROATTN_SHIFT, 1, 0),
  171. SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
  172. WM8400_OUT3MUTE_SHIFT, 1, 0),
  173. SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
  174. WM8400_OUT3ATTN_SHIFT, 1, 0),
  175. SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
  176. WM8400_OUT4MUTE_SHIFT, 1, 0),
  177. SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
  178. WM8400_OUT4ATTN_SHIFT, 1, 0),
  179. SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
  180. WM8400_CDMODE_SHIFT, 1, 0),
  181. SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
  182. WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
  183. SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
  184. WM8400_DCGAIN_SHIFT, 6, 0),
  185. SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
  186. WM8400_ACGAIN_SHIFT, 6, 0),
  187. WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
  188. WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
  189. 127, 0, out_dac_tlv),
  190. WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
  191. WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
  192. 127, 0, out_dac_tlv),
  193. SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
  194. SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
  195. SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
  196. WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
  197. SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
  198. WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
  199. SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
  200. WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
  201. SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
  202. WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
  203. WM8400_LEFT_ADC_DIGITAL_VOLUME,
  204. WM8400_ADCL_VOL_SHIFT,
  205. WM8400_ADCL_VOL_MASK,
  206. 0,
  207. in_adc_tlv),
  208. WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
  209. WM8400_RIGHT_ADC_DIGITAL_VOLUME,
  210. WM8400_ADCR_VOL_SHIFT,
  211. WM8400_ADCR_VOL_MASK,
  212. 0,
  213. in_adc_tlv),
  214. WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
  215. WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
  216. WM8400_LIN12VOL_SHIFT,
  217. WM8400_LIN12VOL_MASK,
  218. 0,
  219. in_pga_tlv),
  220. SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
  221. WM8400_LI12ZC_SHIFT, 1, 0),
  222. SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
  223. WM8400_LI12MUTE_SHIFT, 1, 0),
  224. WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
  225. WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
  226. WM8400_LIN34VOL_SHIFT,
  227. WM8400_LIN34VOL_MASK,
  228. 0,
  229. in_pga_tlv),
  230. SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
  231. WM8400_LI34ZC_SHIFT, 1, 0),
  232. SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
  233. WM8400_LI34MUTE_SHIFT, 1, 0),
  234. WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
  235. WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
  236. WM8400_RIN12VOL_SHIFT,
  237. WM8400_RIN12VOL_MASK,
  238. 0,
  239. in_pga_tlv),
  240. SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
  241. WM8400_RI12ZC_SHIFT, 1, 0),
  242. SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
  243. WM8400_RI12MUTE_SHIFT, 1, 0),
  244. WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
  245. WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
  246. WM8400_RIN34VOL_SHIFT,
  247. WM8400_RIN34VOL_MASK,
  248. 0,
  249. in_pga_tlv),
  250. SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
  251. WM8400_RI34ZC_SHIFT, 1, 0),
  252. SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
  253. WM8400_RI34MUTE_SHIFT, 1, 0),
  254. };
  255. /*
  256. * _DAPM_ Controls
  257. */
  258. static int outmixer_event (struct snd_soc_dapm_widget *w,
  259. struct snd_kcontrol * kcontrol, int event)
  260. {
  261. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  262. struct soc_mixer_control *mc =
  263. (struct soc_mixer_control *)kcontrol->private_value;
  264. u32 reg_shift = mc->shift;
  265. int ret = 0;
  266. u16 reg;
  267. switch (reg_shift) {
  268. case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
  269. reg = snd_soc_component_read(component, WM8400_OUTPUT_MIXER1);
  270. if (reg & WM8400_LDLO) {
  271. printk(KERN_WARNING
  272. "Cannot set as Output Mixer 1 LDLO Set\n");
  273. ret = -1;
  274. }
  275. break;
  276. case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
  277. reg = snd_soc_component_read(component, WM8400_OUTPUT_MIXER2);
  278. if (reg & WM8400_RDRO) {
  279. printk(KERN_WARNING
  280. "Cannot set as Output Mixer 2 RDRO Set\n");
  281. ret = -1;
  282. }
  283. break;
  284. case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
  285. reg = snd_soc_component_read(component, WM8400_SPEAKER_MIXER);
  286. if (reg & WM8400_LDSPK) {
  287. printk(KERN_WARNING
  288. "Cannot set as Speaker Mixer LDSPK Set\n");
  289. ret = -1;
  290. }
  291. break;
  292. case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
  293. reg = snd_soc_component_read(component, WM8400_SPEAKER_MIXER);
  294. if (reg & WM8400_RDSPK) {
  295. printk(KERN_WARNING
  296. "Cannot set as Speaker Mixer RDSPK Set\n");
  297. ret = -1;
  298. }
  299. break;
  300. }
  301. return ret;
  302. }
  303. /* INMIX dB values */
  304. static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
  305. /* Left In PGA Connections */
  306. static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
  307. SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
  308. SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
  309. };
  310. static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
  311. SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
  312. SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
  313. };
  314. /* Right In PGA Connections */
  315. static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
  316. SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
  317. SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
  318. };
  319. static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
  320. SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
  321. SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
  322. };
  323. /* INMIXL */
  324. static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
  325. SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
  326. WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
  327. SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
  328. 7, 0, in_mix_tlv),
  329. SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
  330. 1, 0),
  331. SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
  332. 1, 0),
  333. };
  334. /* INMIXR */
  335. static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
  336. SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
  337. WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
  338. SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
  339. 7, 0, in_mix_tlv),
  340. SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
  341. 1, 0),
  342. SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
  343. 1, 0),
  344. };
  345. /* AINLMUX */
  346. static const char *wm8400_ainlmux[] =
  347. {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
  348. static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
  349. WM8400_INPUT_MIXER1,
  350. WM8400_AINLMODE_SHIFT,
  351. wm8400_ainlmux);
  352. static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
  353. SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
  354. /* DIFFINL */
  355. /* AINRMUX */
  356. static const char *wm8400_ainrmux[] =
  357. {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
  358. static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
  359. WM8400_INPUT_MIXER1,
  360. WM8400_AINRMODE_SHIFT,
  361. wm8400_ainrmux);
  362. static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
  363. SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
  364. /* LOMIX */
  365. static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
  366. SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
  367. WM8400_LRBLO_SHIFT, 1, 0),
  368. SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
  369. WM8400_LLBLO_SHIFT, 1, 0),
  370. SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
  371. WM8400_LRI3LO_SHIFT, 1, 0),
  372. SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
  373. WM8400_LLI3LO_SHIFT, 1, 0),
  374. SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
  375. WM8400_LR12LO_SHIFT, 1, 0),
  376. SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
  377. WM8400_LL12LO_SHIFT, 1, 0),
  378. SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
  379. WM8400_LDLO_SHIFT, 1, 0),
  380. };
  381. /* ROMIX */
  382. static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
  383. SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
  384. WM8400_RLBRO_SHIFT, 1, 0),
  385. SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
  386. WM8400_RRBRO_SHIFT, 1, 0),
  387. SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
  388. WM8400_RLI3RO_SHIFT, 1, 0),
  389. SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
  390. WM8400_RRI3RO_SHIFT, 1, 0),
  391. SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
  392. WM8400_RL12RO_SHIFT, 1, 0),
  393. SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
  394. WM8400_RR12RO_SHIFT, 1, 0),
  395. SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
  396. WM8400_RDRO_SHIFT, 1, 0),
  397. };
  398. /* LONMIX */
  399. static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
  400. SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
  401. WM8400_LLOPGALON_SHIFT, 1, 0),
  402. SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
  403. WM8400_LROPGALON_SHIFT, 1, 0),
  404. SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
  405. WM8400_LOPLON_SHIFT, 1, 0),
  406. };
  407. /* LOPMIX */
  408. static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
  409. SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
  410. WM8400_LR12LOP_SHIFT, 1, 0),
  411. SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
  412. WM8400_LL12LOP_SHIFT, 1, 0),
  413. SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
  414. WM8400_LLOPGALOP_SHIFT, 1, 0),
  415. };
  416. /* RONMIX */
  417. static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
  418. SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
  419. WM8400_RROPGARON_SHIFT, 1, 0),
  420. SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
  421. WM8400_RLOPGARON_SHIFT, 1, 0),
  422. SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
  423. WM8400_ROPRON_SHIFT, 1, 0),
  424. };
  425. /* ROPMIX */
  426. static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
  427. SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
  428. WM8400_RL12ROP_SHIFT, 1, 0),
  429. SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
  430. WM8400_RR12ROP_SHIFT, 1, 0),
  431. SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
  432. WM8400_RROPGAROP_SHIFT, 1, 0),
  433. };
  434. /* OUT3MIX */
  435. static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
  436. SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
  437. WM8400_LI4O3_SHIFT, 1, 0),
  438. SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
  439. WM8400_LPGAO3_SHIFT, 1, 0),
  440. };
  441. /* OUT4MIX */
  442. static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
  443. SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
  444. WM8400_RPGAO4_SHIFT, 1, 0),
  445. SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
  446. WM8400_RI4O4_SHIFT, 1, 0),
  447. };
  448. /* SPKMIX */
  449. static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
  450. SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
  451. WM8400_LI2SPK_SHIFT, 1, 0),
  452. SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
  453. WM8400_LB2SPK_SHIFT, 1, 0),
  454. SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
  455. WM8400_LOPGASPK_SHIFT, 1, 0),
  456. SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
  457. WM8400_LDSPK_SHIFT, 1, 0),
  458. SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
  459. WM8400_RDSPK_SHIFT, 1, 0),
  460. SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
  461. WM8400_ROPGASPK_SHIFT, 1, 0),
  462. SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
  463. WM8400_RL12ROP_SHIFT, 1, 0),
  464. SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
  465. WM8400_RI2SPK_SHIFT, 1, 0),
  466. };
  467. static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
  468. /* Input Side */
  469. /* Input Lines */
  470. SND_SOC_DAPM_INPUT("LIN1"),
  471. SND_SOC_DAPM_INPUT("LIN2"),
  472. SND_SOC_DAPM_INPUT("LIN3"),
  473. SND_SOC_DAPM_INPUT("LIN4/RXN"),
  474. SND_SOC_DAPM_INPUT("RIN3"),
  475. SND_SOC_DAPM_INPUT("RIN4/RXP"),
  476. SND_SOC_DAPM_INPUT("RIN1"),
  477. SND_SOC_DAPM_INPUT("RIN2"),
  478. SND_SOC_DAPM_INPUT("Internal ADC Source"),
  479. /* DACs */
  480. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
  481. WM8400_ADCL_ENA_SHIFT, 0),
  482. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
  483. WM8400_ADCR_ENA_SHIFT, 0),
  484. /* Input PGAs */
  485. SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
  486. WM8400_LIN12_ENA_SHIFT,
  487. 0, &wm8400_dapm_lin12_pga_controls[0],
  488. ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
  489. SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
  490. WM8400_LIN34_ENA_SHIFT,
  491. 0, &wm8400_dapm_lin34_pga_controls[0],
  492. ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
  493. SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
  494. WM8400_RIN12_ENA_SHIFT,
  495. 0, &wm8400_dapm_rin12_pga_controls[0],
  496. ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
  497. SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
  498. WM8400_RIN34_ENA_SHIFT,
  499. 0, &wm8400_dapm_rin34_pga_controls[0],
  500. ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
  501. SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
  502. 0, NULL, 0),
  503. SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
  504. 0, NULL, 0),
  505. /* INMIXL */
  506. SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
  507. &wm8400_dapm_inmixl_controls[0],
  508. ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
  509. /* AINLMUX */
  510. SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
  511. /* INMIXR */
  512. SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
  513. &wm8400_dapm_inmixr_controls[0],
  514. ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
  515. /* AINRMUX */
  516. SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
  517. /* Output Side */
  518. /* DACs */
  519. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
  520. WM8400_DACL_ENA_SHIFT, 0),
  521. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
  522. WM8400_DACR_ENA_SHIFT, 0),
  523. /* LOMIX */
  524. SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
  525. WM8400_LOMIX_ENA_SHIFT,
  526. 0, &wm8400_dapm_lomix_controls[0],
  527. ARRAY_SIZE(wm8400_dapm_lomix_controls),
  528. outmixer_event, SND_SOC_DAPM_PRE_REG),
  529. /* LONMIX */
  530. SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
  531. 0, &wm8400_dapm_lonmix_controls[0],
  532. ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
  533. /* LOPMIX */
  534. SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
  535. 0, &wm8400_dapm_lopmix_controls[0],
  536. ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
  537. /* OUT3MIX */
  538. SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
  539. 0, &wm8400_dapm_out3mix_controls[0],
  540. ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
  541. /* SPKMIX */
  542. SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
  543. 0, &wm8400_dapm_spkmix_controls[0],
  544. ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
  545. SND_SOC_DAPM_PRE_REG),
  546. /* OUT4MIX */
  547. SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
  548. 0, &wm8400_dapm_out4mix_controls[0],
  549. ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
  550. /* ROPMIX */
  551. SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
  552. 0, &wm8400_dapm_ropmix_controls[0],
  553. ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
  554. /* RONMIX */
  555. SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
  556. 0, &wm8400_dapm_ronmix_controls[0],
  557. ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
  558. /* ROMIX */
  559. SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
  560. WM8400_ROMIX_ENA_SHIFT,
  561. 0, &wm8400_dapm_romix_controls[0],
  562. ARRAY_SIZE(wm8400_dapm_romix_controls),
  563. outmixer_event, SND_SOC_DAPM_PRE_REG),
  564. /* LOUT PGA */
  565. SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
  566. 0, NULL, 0),
  567. /* ROUT PGA */
  568. SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
  569. 0, NULL, 0),
  570. /* LOPGA */
  571. SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
  572. NULL, 0),
  573. /* ROPGA */
  574. SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
  575. NULL, 0),
  576. /* MICBIAS */
  577. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
  578. WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
  579. SND_SOC_DAPM_OUTPUT("LON"),
  580. SND_SOC_DAPM_OUTPUT("LOP"),
  581. SND_SOC_DAPM_OUTPUT("OUT3"),
  582. SND_SOC_DAPM_OUTPUT("LOUT"),
  583. SND_SOC_DAPM_OUTPUT("SPKN"),
  584. SND_SOC_DAPM_OUTPUT("SPKP"),
  585. SND_SOC_DAPM_OUTPUT("ROUT"),
  586. SND_SOC_DAPM_OUTPUT("OUT4"),
  587. SND_SOC_DAPM_OUTPUT("ROP"),
  588. SND_SOC_DAPM_OUTPUT("RON"),
  589. SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
  590. };
  591. static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
  592. /* Make DACs turn on when playing even if not mixed into any outputs */
  593. {"Internal DAC Sink", NULL, "Left DAC"},
  594. {"Internal DAC Sink", NULL, "Right DAC"},
  595. /* Make ADCs turn on when recording
  596. * even if not mixed from any inputs */
  597. {"Left ADC", NULL, "Internal ADC Source"},
  598. {"Right ADC", NULL, "Internal ADC Source"},
  599. /* Input Side */
  600. /* LIN12 PGA */
  601. {"LIN12 PGA", "LIN1 Switch", "LIN1"},
  602. {"LIN12 PGA", "LIN2 Switch", "LIN2"},
  603. /* LIN34 PGA */
  604. {"LIN34 PGA", "LIN3 Switch", "LIN3"},
  605. {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
  606. /* INMIXL */
  607. {"INMIXL", NULL, "INL"},
  608. {"INMIXL", "Record Left Volume", "LOMIX"},
  609. {"INMIXL", "LIN2 Volume", "LIN2"},
  610. {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
  611. {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
  612. /* AILNMUX */
  613. {"AILNMUX", NULL, "INL"},
  614. {"AILNMUX", "INMIXL Mix", "INMIXL"},
  615. {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
  616. {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
  617. {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
  618. {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
  619. /* ADC */
  620. {"Left ADC", NULL, "AILNMUX"},
  621. /* RIN12 PGA */
  622. {"RIN12 PGA", "RIN1 Switch", "RIN1"},
  623. {"RIN12 PGA", "RIN2 Switch", "RIN2"},
  624. /* RIN34 PGA */
  625. {"RIN34 PGA", "RIN3 Switch", "RIN3"},
  626. {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
  627. /* INMIXR */
  628. {"INMIXR", NULL, "INR"},
  629. {"INMIXR", "Record Right Volume", "ROMIX"},
  630. {"INMIXR", "RIN2 Volume", "RIN2"},
  631. {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
  632. {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
  633. /* AIRNMUX */
  634. {"AIRNMUX", NULL, "INR"},
  635. {"AIRNMUX", "INMIXR Mix", "INMIXR"},
  636. {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
  637. {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
  638. {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
  639. {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
  640. /* ADC */
  641. {"Right ADC", NULL, "AIRNMUX"},
  642. /* LOMIX */
  643. {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
  644. {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
  645. {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
  646. {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
  647. {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
  648. {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
  649. {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
  650. /* ROMIX */
  651. {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
  652. {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
  653. {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
  654. {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
  655. {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
  656. {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
  657. {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
  658. /* SPKMIX */
  659. {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
  660. {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
  661. {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
  662. {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
  663. {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
  664. {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
  665. {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
  666. {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
  667. /* LONMIX */
  668. {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
  669. {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
  670. {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
  671. /* LOPMIX */
  672. {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
  673. {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
  674. {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
  675. /* OUT3MIX */
  676. {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
  677. {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
  678. /* OUT4MIX */
  679. {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
  680. {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
  681. /* RONMIX */
  682. {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
  683. {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
  684. {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
  685. /* ROPMIX */
  686. {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
  687. {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
  688. {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
  689. /* Out Mixer PGAs */
  690. {"LOPGA", NULL, "LOMIX"},
  691. {"ROPGA", NULL, "ROMIX"},
  692. {"LOUT PGA", NULL, "LOMIX"},
  693. {"ROUT PGA", NULL, "ROMIX"},
  694. /* Output Pins */
  695. {"LON", NULL, "LONMIX"},
  696. {"LOP", NULL, "LOPMIX"},
  697. {"OUT3", NULL, "OUT3MIX"},
  698. {"LOUT", NULL, "LOUT PGA"},
  699. {"SPKN", NULL, "SPKMIX"},
  700. {"ROUT", NULL, "ROUT PGA"},
  701. {"OUT4", NULL, "OUT4MIX"},
  702. {"ROP", NULL, "ROPMIX"},
  703. {"RON", NULL, "RONMIX"},
  704. };
  705. /*
  706. * Clock after FLL and dividers
  707. */
  708. static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  709. int clk_id, unsigned int freq, int dir)
  710. {
  711. struct snd_soc_component *component = codec_dai->component;
  712. struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
  713. wm8400->sysclk = freq;
  714. return 0;
  715. }
  716. struct fll_factors {
  717. u16 n;
  718. u16 k;
  719. u16 outdiv;
  720. u16 fratio;
  721. u16 freq_ref;
  722. };
  723. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  724. static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
  725. unsigned int Fref, unsigned int Fout)
  726. {
  727. u64 Kpart;
  728. unsigned int K, Nmod, target;
  729. factors->outdiv = 2;
  730. while (Fout * factors->outdiv < 90000000 ||
  731. Fout * factors->outdiv > 100000000) {
  732. factors->outdiv *= 2;
  733. if (factors->outdiv > 32) {
  734. dev_err(wm8400->wm8400->dev,
  735. "Unsupported FLL output frequency %uHz\n",
  736. Fout);
  737. return -EINVAL;
  738. }
  739. }
  740. target = Fout * factors->outdiv;
  741. factors->outdiv = factors->outdiv >> 2;
  742. if (Fref < 48000)
  743. factors->freq_ref = 1;
  744. else
  745. factors->freq_ref = 0;
  746. if (Fref < 1000000)
  747. factors->fratio = 9;
  748. else
  749. factors->fratio = 0;
  750. /* Ensure we have a fractional part */
  751. do {
  752. if (Fref < 1000000)
  753. factors->fratio--;
  754. else
  755. factors->fratio++;
  756. if (factors->fratio < 1 || factors->fratio > 8) {
  757. dev_err(wm8400->wm8400->dev,
  758. "Unable to calculate FRATIO\n");
  759. return -EINVAL;
  760. }
  761. factors->n = target / (Fref * factors->fratio);
  762. Nmod = target % (Fref * factors->fratio);
  763. } while (Nmod == 0);
  764. /* Calculate fractional part - scale up so we can round. */
  765. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  766. do_div(Kpart, (Fref * factors->fratio));
  767. K = Kpart & 0xFFFFFFFF;
  768. if ((K % 10) >= 5)
  769. K += 5;
  770. /* Move down to proper range now rounding is done */
  771. factors->k = K / 10;
  772. dev_dbg(wm8400->wm8400->dev,
  773. "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
  774. Fref, Fout,
  775. factors->n, factors->k, factors->fratio, factors->outdiv);
  776. return 0;
  777. }
  778. static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
  779. int source, unsigned int freq_in,
  780. unsigned int freq_out)
  781. {
  782. struct snd_soc_component *component = codec_dai->component;
  783. struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
  784. struct fll_factors factors;
  785. int ret;
  786. u16 reg;
  787. if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
  788. return 0;
  789. if (freq_out) {
  790. ret = fll_factors(wm8400, &factors, freq_in, freq_out);
  791. if (ret != 0)
  792. return ret;
  793. } else {
  794. /* Bodge GCC 4.4.0 uninitialised variable warning - it
  795. * doesn't seem capable of working out that we exit if
  796. * freq_out is 0 before any of the uses. */
  797. memset(&factors, 0, sizeof(factors));
  798. }
  799. wm8400->fll_out = freq_out;
  800. wm8400->fll_in = freq_in;
  801. /* We *must* disable the FLL before any changes */
  802. reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_2);
  803. reg &= ~WM8400_FLL_ENA;
  804. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_2, reg);
  805. reg = snd_soc_component_read(component, WM8400_FLL_CONTROL_1);
  806. reg &= ~WM8400_FLL_OSC_ENA;
  807. snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg);
  808. if (!freq_out)
  809. return 0;
  810. reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
  811. reg |= WM8400_FLL_FRAC | factors.fratio;
  812. reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
  813. snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg);
  814. snd_soc_component_write(component, WM8400_FLL_CONTROL_2, factors.k);
  815. snd_soc_component_write(component, WM8400_FLL_CONTROL_3, factors.n);
  816. reg = snd_soc_component_read(component, WM8400_FLL_CONTROL_4);
  817. reg &= ~WM8400_FLL_OUTDIV_MASK;
  818. reg |= factors.outdiv;
  819. snd_soc_component_write(component, WM8400_FLL_CONTROL_4, reg);
  820. return 0;
  821. }
  822. /*
  823. * Sets ADC and Voice DAC format.
  824. */
  825. static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
  826. unsigned int fmt)
  827. {
  828. struct snd_soc_component *component = codec_dai->component;
  829. u16 audio1, audio3;
  830. audio1 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_1);
  831. audio3 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_3);
  832. /* set master/slave audio interface */
  833. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  834. case SND_SOC_DAIFMT_CBS_CFS:
  835. audio3 &= ~WM8400_AIF_MSTR1;
  836. break;
  837. case SND_SOC_DAIFMT_CBM_CFM:
  838. audio3 |= WM8400_AIF_MSTR1;
  839. break;
  840. default:
  841. return -EINVAL;
  842. }
  843. audio1 &= ~WM8400_AIF_FMT_MASK;
  844. /* interface format */
  845. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  846. case SND_SOC_DAIFMT_I2S:
  847. audio1 |= WM8400_AIF_FMT_I2S;
  848. audio1 &= ~WM8400_AIF_LRCLK_INV;
  849. break;
  850. case SND_SOC_DAIFMT_RIGHT_J:
  851. audio1 |= WM8400_AIF_FMT_RIGHTJ;
  852. audio1 &= ~WM8400_AIF_LRCLK_INV;
  853. break;
  854. case SND_SOC_DAIFMT_LEFT_J:
  855. audio1 |= WM8400_AIF_FMT_LEFTJ;
  856. audio1 &= ~WM8400_AIF_LRCLK_INV;
  857. break;
  858. case SND_SOC_DAIFMT_DSP_A:
  859. audio1 |= WM8400_AIF_FMT_DSP;
  860. audio1 &= ~WM8400_AIF_LRCLK_INV;
  861. break;
  862. case SND_SOC_DAIFMT_DSP_B:
  863. audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
  864. break;
  865. default:
  866. return -EINVAL;
  867. }
  868. snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, audio1);
  869. snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_3, audio3);
  870. return 0;
  871. }
  872. static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
  873. int div_id, int div)
  874. {
  875. struct snd_soc_component *component = codec_dai->component;
  876. u16 reg;
  877. switch (div_id) {
  878. case WM8400_MCLK_DIV:
  879. reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
  880. ~WM8400_MCLK_DIV_MASK;
  881. snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
  882. break;
  883. case WM8400_DACCLK_DIV:
  884. reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
  885. ~WM8400_DAC_CLKDIV_MASK;
  886. snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
  887. break;
  888. case WM8400_ADCCLK_DIV:
  889. reg = snd_soc_component_read(component, WM8400_CLOCKING_2) &
  890. ~WM8400_ADC_CLKDIV_MASK;
  891. snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
  892. break;
  893. case WM8400_BCLK_DIV:
  894. reg = snd_soc_component_read(component, WM8400_CLOCKING_1) &
  895. ~WM8400_BCLK_DIV_MASK;
  896. snd_soc_component_write(component, WM8400_CLOCKING_1, reg | div);
  897. break;
  898. default:
  899. return -EINVAL;
  900. }
  901. return 0;
  902. }
  903. /*
  904. * Set PCM DAI bit size and sample rate.
  905. */
  906. static int wm8400_hw_params(struct snd_pcm_substream *substream,
  907. struct snd_pcm_hw_params *params,
  908. struct snd_soc_dai *dai)
  909. {
  910. struct snd_soc_component *component = dai->component;
  911. u16 audio1 = snd_soc_component_read(component, WM8400_AUDIO_INTERFACE_1);
  912. audio1 &= ~WM8400_AIF_WL_MASK;
  913. /* bit size */
  914. switch (params_width(params)) {
  915. case 16:
  916. break;
  917. case 20:
  918. audio1 |= WM8400_AIF_WL_20BITS;
  919. break;
  920. case 24:
  921. audio1 |= WM8400_AIF_WL_24BITS;
  922. break;
  923. case 32:
  924. audio1 |= WM8400_AIF_WL_32BITS;
  925. break;
  926. }
  927. snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, audio1);
  928. return 0;
  929. }
  930. static int wm8400_mute(struct snd_soc_dai *dai, int mute, int direction)
  931. {
  932. struct snd_soc_component *component = dai->component;
  933. u16 val = snd_soc_component_read(component, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
  934. if (mute)
  935. snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
  936. else
  937. snd_soc_component_write(component, WM8400_DAC_CTRL, val);
  938. return 0;
  939. }
  940. /* TODO: set bias for best performance at standby */
  941. static int wm8400_set_bias_level(struct snd_soc_component *component,
  942. enum snd_soc_bias_level level)
  943. {
  944. struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
  945. u16 val;
  946. int ret;
  947. switch (level) {
  948. case SND_SOC_BIAS_ON:
  949. break;
  950. case SND_SOC_BIAS_PREPARE:
  951. /* VMID=2*50k */
  952. val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1) &
  953. ~WM8400_VMID_MODE_MASK;
  954. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x2);
  955. break;
  956. case SND_SOC_BIAS_STANDBY:
  957. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  958. ret = regulator_bulk_enable(ARRAY_SIZE(power),
  959. &power[0]);
  960. if (ret != 0) {
  961. dev_err(wm8400->wm8400->dev,
  962. "Failed to enable regulators: %d\n",
  963. ret);
  964. return ret;
  965. }
  966. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
  967. WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
  968. /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
  969. snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
  970. WM8400_BUFDCOPEN | WM8400_POBCTRL);
  971. msleep(50);
  972. /* Enable VREF & VMID at 2x50k */
  973. val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
  974. val |= 0x2 | WM8400_VREF_ENA;
  975. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
  976. /* Enable BUFIOEN */
  977. snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
  978. WM8400_BUFDCOPEN | WM8400_POBCTRL |
  979. WM8400_BUFIOEN);
  980. /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
  981. snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_BUFIOEN);
  982. }
  983. /* VMID=2*300k */
  984. val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1) &
  985. ~WM8400_VMID_MODE_MASK;
  986. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x4);
  987. break;
  988. case SND_SOC_BIAS_OFF:
  989. /* Enable POBCTRL and SOFT_ST */
  990. snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
  991. WM8400_POBCTRL | WM8400_BUFIOEN);
  992. /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
  993. snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
  994. WM8400_BUFDCOPEN | WM8400_POBCTRL |
  995. WM8400_BUFIOEN);
  996. /* mute DAC */
  997. val = snd_soc_component_read(component, WM8400_DAC_CTRL);
  998. snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
  999. /* Enable any disabled outputs */
  1000. val = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
  1001. val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
  1002. WM8400_OUT4_ENA | WM8400_LOUT_ENA |
  1003. WM8400_ROUT_ENA;
  1004. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
  1005. /* Disable VMID */
  1006. val &= ~WM8400_VMID_MODE_MASK;
  1007. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
  1008. msleep(300);
  1009. /* Enable all output discharge bits */
  1010. snd_soc_component_write(component, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
  1011. WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
  1012. WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
  1013. WM8400_DIS_ROUT);
  1014. /* Disable VREF */
  1015. val &= ~WM8400_VREF_ENA;
  1016. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
  1017. /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
  1018. snd_soc_component_write(component, WM8400_ANTIPOP2, 0x0);
  1019. ret = regulator_bulk_disable(ARRAY_SIZE(power),
  1020. &power[0]);
  1021. if (ret != 0)
  1022. return ret;
  1023. break;
  1024. }
  1025. return 0;
  1026. }
  1027. #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
  1028. #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1029. SNDRV_PCM_FMTBIT_S24_LE)
  1030. static const struct snd_soc_dai_ops wm8400_dai_ops = {
  1031. .hw_params = wm8400_hw_params,
  1032. .mute_stream = wm8400_mute,
  1033. .set_fmt = wm8400_set_dai_fmt,
  1034. .set_clkdiv = wm8400_set_dai_clkdiv,
  1035. .set_sysclk = wm8400_set_dai_sysclk,
  1036. .set_pll = wm8400_set_dai_pll,
  1037. .no_capture_mute = 1,
  1038. };
  1039. /*
  1040. * The WM8400 supports 2 different and mutually exclusive DAI
  1041. * configurations.
  1042. *
  1043. * 1. ADC/DAC on Primary Interface
  1044. * 2. ADC on Primary Interface/DAC on secondary
  1045. */
  1046. static struct snd_soc_dai_driver wm8400_dai = {
  1047. /* ADC/DAC on primary */
  1048. .name = "wm8400-hifi",
  1049. .playback = {
  1050. .stream_name = "Playback",
  1051. .channels_min = 1,
  1052. .channels_max = 2,
  1053. .rates = WM8400_RATES,
  1054. .formats = WM8400_FORMATS,
  1055. },
  1056. .capture = {
  1057. .stream_name = "Capture",
  1058. .channels_min = 1,
  1059. .channels_max = 2,
  1060. .rates = WM8400_RATES,
  1061. .formats = WM8400_FORMATS,
  1062. },
  1063. .ops = &wm8400_dai_ops,
  1064. };
  1065. static int wm8400_component_probe(struct snd_soc_component *component)
  1066. {
  1067. struct wm8400 *wm8400 = dev_get_platdata(component->dev);
  1068. struct wm8400_priv *priv;
  1069. int ret;
  1070. u16 reg;
  1071. priv = devm_kzalloc(component->dev, sizeof(struct wm8400_priv),
  1072. GFP_KERNEL);
  1073. if (priv == NULL)
  1074. return -ENOMEM;
  1075. snd_soc_component_init_regmap(component, wm8400->regmap);
  1076. snd_soc_component_set_drvdata(component, priv);
  1077. priv->wm8400 = wm8400;
  1078. ret = devm_regulator_bulk_get(wm8400->dev,
  1079. ARRAY_SIZE(power), &power[0]);
  1080. if (ret != 0) {
  1081. dev_err(component->dev, "Failed to get regulators: %d\n", ret);
  1082. return ret;
  1083. }
  1084. wm8400_component_reset(component);
  1085. reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
  1086. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
  1087. /* Latch volume update bits */
  1088. reg = snd_soc_component_read(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
  1089. snd_soc_component_write(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
  1090. reg & WM8400_IPVU);
  1091. reg = snd_soc_component_read(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
  1092. snd_soc_component_write(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
  1093. reg & WM8400_IPVU);
  1094. snd_soc_component_write(component, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
  1095. snd_soc_component_write(component, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
  1096. return 0;
  1097. }
  1098. static void wm8400_component_remove(struct snd_soc_component *component)
  1099. {
  1100. u16 reg;
  1101. reg = snd_soc_component_read(component, WM8400_POWER_MANAGEMENT_1);
  1102. snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
  1103. reg & (~WM8400_CODEC_ENA));
  1104. }
  1105. static const struct snd_soc_component_driver soc_component_dev_wm8400 = {
  1106. .probe = wm8400_component_probe,
  1107. .remove = wm8400_component_remove,
  1108. .set_bias_level = wm8400_set_bias_level,
  1109. .controls = wm8400_snd_controls,
  1110. .num_controls = ARRAY_SIZE(wm8400_snd_controls),
  1111. .dapm_widgets = wm8400_dapm_widgets,
  1112. .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
  1113. .dapm_routes = wm8400_dapm_routes,
  1114. .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
  1115. .suspend_bias_off = 1,
  1116. .idle_bias_on = 1,
  1117. .use_pmdown_time = 1,
  1118. .endianness = 1,
  1119. .non_legacy_dai_naming = 1,
  1120. };
  1121. static int wm8400_probe(struct platform_device *pdev)
  1122. {
  1123. return devm_snd_soc_register_component(&pdev->dev,
  1124. &soc_component_dev_wm8400,
  1125. &wm8400_dai, 1);
  1126. }
  1127. static struct platform_driver wm8400_codec_driver = {
  1128. .driver = {
  1129. .name = "wm8400-codec",
  1130. },
  1131. .probe = wm8400_probe,
  1132. };
  1133. module_platform_driver(wm8400_codec_driver);
  1134. MODULE_DESCRIPTION("ASoC WM8400 driver");
  1135. MODULE_AUTHOR("Mark Brown");
  1136. MODULE_LICENSE("GPL");
  1137. MODULE_ALIAS("platform:wm8400-codec");