wm8350.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm8350.c -- WM8350 ALSA SoC audio driver
  4. *
  5. * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
  6. *
  7. * Author: Liam Girdwood <lrg@slimlogic.co.uk>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/moduleparam.h>
  11. #include <linux/init.h>
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/pm.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mfd/wm8350/audio.h>
  17. #include <linux/mfd/wm8350/core.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include <sound/initval.h>
  24. #include <sound/tlv.h>
  25. #include <trace/events/asoc.h>
  26. #include "wm8350.h"
  27. #define WM8350_OUTn_0dB 0x39
  28. #define WM8350_RAMP_NONE 0
  29. #define WM8350_RAMP_UP 1
  30. #define WM8350_RAMP_DOWN 2
  31. /* We only include the analogue supplies here; the digital supplies
  32. * need to be available well before this driver can be probed.
  33. */
  34. static const char *supply_names[] = {
  35. "AVDD",
  36. "HPVDD",
  37. };
  38. struct wm8350_output {
  39. u16 active;
  40. u16 left_vol;
  41. u16 right_vol;
  42. u16 ramp;
  43. u16 mute;
  44. };
  45. struct wm8350_jack_data {
  46. struct snd_soc_jack *jack;
  47. struct delayed_work work;
  48. int report;
  49. int short_report;
  50. };
  51. struct wm8350_data {
  52. struct wm8350 *wm8350;
  53. struct wm8350_output out1;
  54. struct wm8350_output out2;
  55. struct wm8350_jack_data hpl;
  56. struct wm8350_jack_data hpr;
  57. struct wm8350_jack_data mic;
  58. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  59. int fll_freq_out;
  60. int fll_freq_in;
  61. struct delayed_work pga_work;
  62. };
  63. /*
  64. * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  65. */
  66. static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
  67. {
  68. struct wm8350_output *out1 = &wm8350_data->out1;
  69. struct wm8350 *wm8350 = wm8350_data->wm8350;
  70. int left_complete = 0, right_complete = 0;
  71. u16 reg, val;
  72. /* left channel */
  73. reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
  74. val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  75. if (out1->ramp == WM8350_RAMP_UP) {
  76. /* ramp step up */
  77. if (val < out1->left_vol) {
  78. val++;
  79. reg &= ~WM8350_OUT1L_VOL_MASK;
  80. wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  81. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  82. } else
  83. left_complete = 1;
  84. } else if (out1->ramp == WM8350_RAMP_DOWN) {
  85. /* ramp step down */
  86. if (val > 0) {
  87. val--;
  88. reg &= ~WM8350_OUT1L_VOL_MASK;
  89. wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  90. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  91. } else
  92. left_complete = 1;
  93. } else
  94. return 1;
  95. /* right channel */
  96. reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
  97. val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  98. if (out1->ramp == WM8350_RAMP_UP) {
  99. /* ramp step up */
  100. if (val < out1->right_vol) {
  101. val++;
  102. reg &= ~WM8350_OUT1R_VOL_MASK;
  103. wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
  104. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  105. } else
  106. right_complete = 1;
  107. } else if (out1->ramp == WM8350_RAMP_DOWN) {
  108. /* ramp step down */
  109. if (val > 0) {
  110. val--;
  111. reg &= ~WM8350_OUT1R_VOL_MASK;
  112. wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
  113. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  114. } else
  115. right_complete = 1;
  116. }
  117. /* only hit the update bit if either volume has changed this step */
  118. if (!left_complete || !right_complete)
  119. wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
  120. return left_complete & right_complete;
  121. }
  122. /*
  123. * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
  124. */
  125. static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
  126. {
  127. struct wm8350_output *out2 = &wm8350_data->out2;
  128. struct wm8350 *wm8350 = wm8350_data->wm8350;
  129. int left_complete = 0, right_complete = 0;
  130. u16 reg, val;
  131. /* left channel */
  132. reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
  133. val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  134. if (out2->ramp == WM8350_RAMP_UP) {
  135. /* ramp step up */
  136. if (val < out2->left_vol) {
  137. val++;
  138. reg &= ~WM8350_OUT2L_VOL_MASK;
  139. wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
  140. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  141. } else
  142. left_complete = 1;
  143. } else if (out2->ramp == WM8350_RAMP_DOWN) {
  144. /* ramp step down */
  145. if (val > 0) {
  146. val--;
  147. reg &= ~WM8350_OUT2L_VOL_MASK;
  148. wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
  149. reg | (val << WM8350_OUT1L_VOL_SHIFT));
  150. } else
  151. left_complete = 1;
  152. } else
  153. return 1;
  154. /* right channel */
  155. reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
  156. val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  157. if (out2->ramp == WM8350_RAMP_UP) {
  158. /* ramp step up */
  159. if (val < out2->right_vol) {
  160. val++;
  161. reg &= ~WM8350_OUT2R_VOL_MASK;
  162. wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
  163. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  164. } else
  165. right_complete = 1;
  166. } else if (out2->ramp == WM8350_RAMP_DOWN) {
  167. /* ramp step down */
  168. if (val > 0) {
  169. val--;
  170. reg &= ~WM8350_OUT2R_VOL_MASK;
  171. wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
  172. reg | (val << WM8350_OUT1R_VOL_SHIFT));
  173. } else
  174. right_complete = 1;
  175. }
  176. /* only hit the update bit if either volume has changed this step */
  177. if (!left_complete || !right_complete)
  178. wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
  179. return left_complete & right_complete;
  180. }
  181. /*
  182. * This work ramps both output PGAs at stream start/stop time to
  183. * minimise pop associated with DAPM power switching.
  184. * It's best to enable Zero Cross when ramping occurs to minimise any
  185. * zipper noises.
  186. */
  187. static void wm8350_pga_work(struct work_struct *work)
  188. {
  189. struct wm8350_data *wm8350_data =
  190. container_of(work, struct wm8350_data, pga_work.work);
  191. struct wm8350_output *out1 = &wm8350_data->out1,
  192. *out2 = &wm8350_data->out2;
  193. int i, out1_complete, out2_complete;
  194. /* do we need to ramp at all ? */
  195. if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
  196. return;
  197. /* PGA volumes have 6 bits of resolution to ramp */
  198. for (i = 0; i <= 63; i++) {
  199. out1_complete = 1, out2_complete = 1;
  200. if (out1->ramp != WM8350_RAMP_NONE)
  201. out1_complete = wm8350_out1_ramp_step(wm8350_data);
  202. if (out2->ramp != WM8350_RAMP_NONE)
  203. out2_complete = wm8350_out2_ramp_step(wm8350_data);
  204. /* ramp finished ? */
  205. if (out1_complete && out2_complete)
  206. break;
  207. /* we need to delay longer on the up ramp */
  208. if (out1->ramp == WM8350_RAMP_UP ||
  209. out2->ramp == WM8350_RAMP_UP) {
  210. /* delay is longer over 0dB as increases are larger */
  211. if (i >= WM8350_OUTn_0dB)
  212. schedule_timeout_interruptible(msecs_to_jiffies
  213. (2));
  214. else
  215. schedule_timeout_interruptible(msecs_to_jiffies
  216. (1));
  217. } else
  218. udelay(50); /* doesn't matter if we delay longer */
  219. }
  220. out1->ramp = WM8350_RAMP_NONE;
  221. out2->ramp = WM8350_RAMP_NONE;
  222. }
  223. /*
  224. * WM8350 Controls
  225. */
  226. static int pga_event(struct snd_soc_dapm_widget *w,
  227. struct snd_kcontrol *kcontrol, int event)
  228. {
  229. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  230. struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
  231. struct wm8350_output *out;
  232. switch (w->shift) {
  233. case 0:
  234. case 1:
  235. out = &wm8350_data->out1;
  236. break;
  237. case 2:
  238. case 3:
  239. out = &wm8350_data->out2;
  240. break;
  241. default:
  242. WARN(1, "Invalid shift %d\n", w->shift);
  243. return -1;
  244. }
  245. switch (event) {
  246. case SND_SOC_DAPM_POST_PMU:
  247. out->ramp = WM8350_RAMP_UP;
  248. out->active = 1;
  249. schedule_delayed_work(&wm8350_data->pga_work,
  250. msecs_to_jiffies(1));
  251. break;
  252. case SND_SOC_DAPM_PRE_PMD:
  253. out->ramp = WM8350_RAMP_DOWN;
  254. out->active = 0;
  255. schedule_delayed_work(&wm8350_data->pga_work,
  256. msecs_to_jiffies(1));
  257. break;
  258. }
  259. return 0;
  260. }
  261. static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
  262. struct snd_ctl_elem_value *ucontrol)
  263. {
  264. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  265. struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
  266. struct wm8350_output *out = NULL;
  267. struct soc_mixer_control *mc =
  268. (struct soc_mixer_control *)kcontrol->private_value;
  269. int ret;
  270. unsigned int reg = mc->reg;
  271. u16 val;
  272. /* For OUT1 and OUT2 we shadow the values and only actually write
  273. * them out when active in order to ensure the amplifier comes on
  274. * as quietly as possible. */
  275. switch (reg) {
  276. case WM8350_LOUT1_VOLUME:
  277. out = &wm8350_priv->out1;
  278. break;
  279. case WM8350_LOUT2_VOLUME:
  280. out = &wm8350_priv->out2;
  281. break;
  282. default:
  283. break;
  284. }
  285. if (out) {
  286. out->left_vol = ucontrol->value.integer.value[0];
  287. out->right_vol = ucontrol->value.integer.value[1];
  288. if (!out->active)
  289. return 1;
  290. }
  291. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  292. if (ret < 0)
  293. return ret;
  294. /* now hit the volume update bits (always bit 8) */
  295. val = snd_soc_component_read(component, reg);
  296. snd_soc_component_write(component, reg, val | WM8350_OUT1_VU);
  297. return 1;
  298. }
  299. static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
  300. struct snd_ctl_elem_value *ucontrol)
  301. {
  302. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  303. struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
  304. struct wm8350_output *out1 = &wm8350_priv->out1;
  305. struct wm8350_output *out2 = &wm8350_priv->out2;
  306. struct soc_mixer_control *mc =
  307. (struct soc_mixer_control *)kcontrol->private_value;
  308. unsigned int reg = mc->reg;
  309. /* If these are cached registers use the cache */
  310. switch (reg) {
  311. case WM8350_LOUT1_VOLUME:
  312. ucontrol->value.integer.value[0] = out1->left_vol;
  313. ucontrol->value.integer.value[1] = out1->right_vol;
  314. return 0;
  315. case WM8350_LOUT2_VOLUME:
  316. ucontrol->value.integer.value[0] = out2->left_vol;
  317. ucontrol->value.integer.value[1] = out2->right_vol;
  318. return 0;
  319. default:
  320. break;
  321. }
  322. return snd_soc_get_volsw(kcontrol, ucontrol);
  323. }
  324. static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
  325. static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
  326. static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
  327. static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
  328. static const char *wm8350_adcfilter[] = { "None", "High Pass" };
  329. static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
  330. static const char *wm8350_lr[] = { "Left", "Right" };
  331. static const struct soc_enum wm8350_enum[] = {
  332. SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
  333. SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
  334. SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
  335. SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
  336. SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
  337. SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
  338. SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
  339. SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
  340. };
  341. static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
  342. static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
  343. static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
  344. static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
  345. static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
  346. static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,
  347. 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
  348. 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)
  349. );
  350. static const struct snd_kcontrol_new wm8350_snd_controls[] = {
  351. SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
  352. SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
  353. SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
  354. WM8350_DAC_DIGITAL_VOLUME_L,
  355. WM8350_DAC_DIGITAL_VOLUME_R,
  356. 0, 255, 0, wm8350_get_volsw_2r,
  357. wm8350_put_volsw_2r_vu, dac_pcm_tlv),
  358. SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
  359. SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
  360. SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
  361. SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
  362. SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
  363. SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
  364. WM8350_ADC_DIGITAL_VOLUME_L,
  365. WM8350_ADC_DIGITAL_VOLUME_R,
  366. 0, 255, 0, wm8350_get_volsw_2r,
  367. wm8350_put_volsw_2r_vu, adc_pcm_tlv),
  368. SOC_DOUBLE_TLV("Capture Sidetone Volume",
  369. WM8350_ADC_DIVIDER,
  370. 8, 4, 15, 1, capture_sd_tlv),
  371. SOC_DOUBLE_R_EXT_TLV("Capture Volume",
  372. WM8350_LEFT_INPUT_VOLUME,
  373. WM8350_RIGHT_INPUT_VOLUME,
  374. 2, 63, 0, wm8350_get_volsw_2r,
  375. wm8350_put_volsw_2r_vu, pre_amp_tlv),
  376. SOC_DOUBLE_R("Capture ZC Switch",
  377. WM8350_LEFT_INPUT_VOLUME,
  378. WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
  379. SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
  380. WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
  381. SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
  382. WM8350_OUTPUT_LEFT_MIXER_VOLUME,
  383. 5, 7, 0, out_mix_tlv),
  384. SOC_SINGLE_TLV("Left Input Bypass Volume",
  385. WM8350_OUTPUT_LEFT_MIXER_VOLUME,
  386. 9, 7, 0, out_mix_tlv),
  387. SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
  388. WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
  389. 1, 7, 0, out_mix_tlv),
  390. SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
  391. WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
  392. 5, 7, 0, out_mix_tlv),
  393. SOC_SINGLE_TLV("Right Input Bypass Volume",
  394. WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
  395. 13, 7, 0, out_mix_tlv),
  396. SOC_SINGLE("Left Input Mixer +20dB Switch",
  397. WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
  398. SOC_SINGLE("Right Input Mixer +20dB Switch",
  399. WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
  400. SOC_SINGLE_TLV("Out4 Capture Volume",
  401. WM8350_INPUT_MIXER_VOLUME,
  402. 1, 7, 0, out_mix_tlv),
  403. SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
  404. WM8350_LOUT1_VOLUME,
  405. WM8350_ROUT1_VOLUME,
  406. 2, 63, 0, wm8350_get_volsw_2r,
  407. wm8350_put_volsw_2r_vu, out_pga_tlv),
  408. SOC_DOUBLE_R("Out1 Playback ZC Switch",
  409. WM8350_LOUT1_VOLUME,
  410. WM8350_ROUT1_VOLUME, 13, 1, 0),
  411. SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
  412. WM8350_LOUT2_VOLUME,
  413. WM8350_ROUT2_VOLUME,
  414. 2, 63, 0, wm8350_get_volsw_2r,
  415. wm8350_put_volsw_2r_vu, out_pga_tlv),
  416. SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
  417. WM8350_ROUT2_VOLUME, 13, 1, 0),
  418. SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
  419. SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
  420. 5, 7, 0, out_mix_tlv),
  421. SOC_DOUBLE_R("Out1 Playback Switch",
  422. WM8350_LOUT1_VOLUME,
  423. WM8350_ROUT1_VOLUME,
  424. 14, 1, 1),
  425. SOC_DOUBLE_R("Out2 Playback Switch",
  426. WM8350_LOUT2_VOLUME,
  427. WM8350_ROUT2_VOLUME,
  428. 14, 1, 1),
  429. };
  430. /*
  431. * DAPM Controls
  432. */
  433. /* Left Playback Mixer */
  434. static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
  435. SOC_DAPM_SINGLE("Playback Switch",
  436. WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
  437. SOC_DAPM_SINGLE("Left Bypass Switch",
  438. WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
  439. SOC_DAPM_SINGLE("Right Playback Switch",
  440. WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
  441. SOC_DAPM_SINGLE("Left Sidetone Switch",
  442. WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
  443. SOC_DAPM_SINGLE("Right Sidetone Switch",
  444. WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
  445. };
  446. /* Right Playback Mixer */
  447. static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
  448. SOC_DAPM_SINGLE("Playback Switch",
  449. WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
  450. SOC_DAPM_SINGLE("Right Bypass Switch",
  451. WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
  452. SOC_DAPM_SINGLE("Left Playback Switch",
  453. WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
  454. SOC_DAPM_SINGLE("Left Sidetone Switch",
  455. WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
  456. SOC_DAPM_SINGLE("Right Sidetone Switch",
  457. WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
  458. };
  459. /* Out4 Mixer */
  460. static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
  461. SOC_DAPM_SINGLE("Right Playback Switch",
  462. WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
  463. SOC_DAPM_SINGLE("Left Playback Switch",
  464. WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
  465. SOC_DAPM_SINGLE("Right Capture Switch",
  466. WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
  467. SOC_DAPM_SINGLE("Out3 Playback Switch",
  468. WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
  469. SOC_DAPM_SINGLE("Right Mixer Switch",
  470. WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
  471. SOC_DAPM_SINGLE("Left Mixer Switch",
  472. WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
  473. };
  474. /* Out3 Mixer */
  475. static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
  476. SOC_DAPM_SINGLE("Left Playback Switch",
  477. WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
  478. SOC_DAPM_SINGLE("Left Capture Switch",
  479. WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
  480. SOC_DAPM_SINGLE("Out4 Playback Switch",
  481. WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
  482. SOC_DAPM_SINGLE("Left Mixer Switch",
  483. WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
  484. };
  485. /* Left Input Mixer */
  486. static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
  487. SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
  488. WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
  489. SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
  490. WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
  491. SOC_DAPM_SINGLE("PGA Capture Switch",
  492. WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
  493. };
  494. /* Right Input Mixer */
  495. static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
  496. SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
  497. WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
  498. SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
  499. WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
  500. SOC_DAPM_SINGLE("PGA Capture Switch",
  501. WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
  502. };
  503. /* Left Mic Mixer */
  504. static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
  505. SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
  506. SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
  507. SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
  508. };
  509. /* Right Mic Mixer */
  510. static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
  511. SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
  512. SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
  513. SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
  514. };
  515. /* Beep Switch */
  516. static const struct snd_kcontrol_new wm8350_beep_switch_controls =
  517. SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
  518. /* Out4 Capture Mux */
  519. static const struct snd_kcontrol_new wm8350_out4_capture_controls =
  520. SOC_DAPM_ENUM("Route", wm8350_enum[7]);
  521. static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
  522. SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
  523. SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
  524. SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
  525. 0, pga_event,
  526. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  527. SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
  528. pga_event,
  529. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  530. SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
  531. 0, pga_event,
  532. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  533. SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
  534. pga_event,
  535. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  536. SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
  537. 7, 0, &wm8350_right_capt_mixer_controls[0],
  538. ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
  539. SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
  540. 6, 0, &wm8350_left_capt_mixer_controls[0],
  541. ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
  542. SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
  543. &wm8350_out4_mixer_controls[0],
  544. ARRAY_SIZE(wm8350_out4_mixer_controls)),
  545. SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
  546. &wm8350_out3_mixer_controls[0],
  547. ARRAY_SIZE(wm8350_out3_mixer_controls)),
  548. SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
  549. &wm8350_right_play_mixer_controls[0],
  550. ARRAY_SIZE(wm8350_right_play_mixer_controls)),
  551. SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
  552. &wm8350_left_play_mixer_controls[0],
  553. ARRAY_SIZE(wm8350_left_play_mixer_controls)),
  554. SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
  555. &wm8350_left_mic_mixer_controls[0],
  556. ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
  557. SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
  558. &wm8350_right_mic_mixer_controls[0],
  559. ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
  560. /* virtual mixer for Beep and Out2R */
  561. SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
  562. SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
  563. &wm8350_beep_switch_controls),
  564. SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
  565. WM8350_POWER_MGMT_4, 3, 0),
  566. SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
  567. WM8350_POWER_MGMT_4, 2, 0),
  568. SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
  569. WM8350_POWER_MGMT_4, 5, 0),
  570. SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
  571. WM8350_POWER_MGMT_4, 4, 0),
  572. SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
  573. SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
  574. &wm8350_out4_capture_controls),
  575. SND_SOC_DAPM_OUTPUT("OUT1R"),
  576. SND_SOC_DAPM_OUTPUT("OUT1L"),
  577. SND_SOC_DAPM_OUTPUT("OUT2R"),
  578. SND_SOC_DAPM_OUTPUT("OUT2L"),
  579. SND_SOC_DAPM_OUTPUT("OUT3"),
  580. SND_SOC_DAPM_OUTPUT("OUT4"),
  581. SND_SOC_DAPM_INPUT("IN1RN"),
  582. SND_SOC_DAPM_INPUT("IN1RP"),
  583. SND_SOC_DAPM_INPUT("IN2R"),
  584. SND_SOC_DAPM_INPUT("IN1LP"),
  585. SND_SOC_DAPM_INPUT("IN1LN"),
  586. SND_SOC_DAPM_INPUT("IN2L"),
  587. SND_SOC_DAPM_INPUT("IN3R"),
  588. SND_SOC_DAPM_INPUT("IN3L"),
  589. };
  590. static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
  591. /* left playback mixer */
  592. {"Left Playback Mixer", "Playback Switch", "Left DAC"},
  593. {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
  594. {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
  595. {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
  596. {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
  597. /* right playback mixer */
  598. {"Right Playback Mixer", "Playback Switch", "Right DAC"},
  599. {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
  600. {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
  601. {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
  602. {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
  603. /* out4 playback mixer */
  604. {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
  605. {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
  606. {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
  607. {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
  608. {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
  609. {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
  610. {"OUT4", NULL, "Out4 Mixer"},
  611. /* out3 playback mixer */
  612. {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
  613. {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
  614. {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
  615. {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
  616. {"OUT3", NULL, "Out3 Mixer"},
  617. /* out2 */
  618. {"Right Out2 PGA", NULL, "Right Playback Mixer"},
  619. {"Left Out2 PGA", NULL, "Left Playback Mixer"},
  620. {"OUT2L", NULL, "Left Out2 PGA"},
  621. {"OUT2R", NULL, "Right Out2 PGA"},
  622. /* out1 */
  623. {"Right Out1 PGA", NULL, "Right Playback Mixer"},
  624. {"Left Out1 PGA", NULL, "Left Playback Mixer"},
  625. {"OUT1L", NULL, "Left Out1 PGA"},
  626. {"OUT1R", NULL, "Right Out1 PGA"},
  627. /* ADCs */
  628. {"Left ADC", NULL, "Left Capture Mixer"},
  629. {"Right ADC", NULL, "Right Capture Mixer"},
  630. /* Left capture mixer */
  631. {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
  632. {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
  633. {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
  634. {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
  635. /* Right capture mixer */
  636. {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
  637. {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
  638. {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
  639. {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
  640. /* L3 Inputs */
  641. {"IN3L PGA", NULL, "IN3L"},
  642. {"IN3R PGA", NULL, "IN3R"},
  643. /* Left Mic mixer */
  644. {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
  645. {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
  646. {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
  647. /* Right Mic mixer */
  648. {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
  649. {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
  650. {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
  651. /* out 4 capture */
  652. {"Out4 Capture Channel", NULL, "Out4 Mixer"},
  653. /* Beep */
  654. {"Beep", NULL, "IN3R PGA"},
  655. };
  656. static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  657. int clk_id, unsigned int freq, int dir)
  658. {
  659. struct snd_soc_component *component = codec_dai->component;
  660. struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
  661. struct wm8350 *wm8350 = wm8350_data->wm8350;
  662. u16 fll_4;
  663. switch (clk_id) {
  664. case WM8350_MCLK_SEL_MCLK:
  665. wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
  666. WM8350_MCLK_SEL);
  667. break;
  668. case WM8350_MCLK_SEL_PLL_MCLK:
  669. case WM8350_MCLK_SEL_PLL_DAC:
  670. case WM8350_MCLK_SEL_PLL_ADC:
  671. case WM8350_MCLK_SEL_PLL_32K:
  672. wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
  673. WM8350_MCLK_SEL);
  674. fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
  675. ~WM8350_FLL_CLK_SRC_MASK;
  676. snd_soc_component_write(component, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
  677. break;
  678. }
  679. /* MCLK direction */
  680. if (dir == SND_SOC_CLOCK_OUT)
  681. wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
  682. WM8350_MCLK_DIR);
  683. else
  684. wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
  685. WM8350_MCLK_DIR);
  686. return 0;
  687. }
  688. static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
  689. {
  690. struct snd_soc_component *component = codec_dai->component;
  691. u16 val;
  692. switch (div_id) {
  693. case WM8350_ADC_CLKDIV:
  694. val = snd_soc_component_read(component, WM8350_ADC_DIVIDER) &
  695. ~WM8350_ADC_CLKDIV_MASK;
  696. snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div);
  697. break;
  698. case WM8350_DAC_CLKDIV:
  699. val = snd_soc_component_read(component, WM8350_DAC_CLOCK_CONTROL) &
  700. ~WM8350_DAC_CLKDIV_MASK;
  701. snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div);
  702. break;
  703. case WM8350_BCLK_CLKDIV:
  704. val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
  705. ~WM8350_BCLK_DIV_MASK;
  706. snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
  707. break;
  708. case WM8350_OPCLK_CLKDIV:
  709. val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
  710. ~WM8350_OPCLK_DIV_MASK;
  711. snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
  712. break;
  713. case WM8350_SYS_CLKDIV:
  714. val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
  715. ~WM8350_MCLK_DIV_MASK;
  716. snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
  717. break;
  718. case WM8350_DACLR_CLKDIV:
  719. val = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
  720. ~WM8350_DACLRC_RATE_MASK;
  721. snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div);
  722. break;
  723. case WM8350_ADCLR_CLKDIV:
  724. val = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
  725. ~WM8350_ADCLRC_RATE_MASK;
  726. snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div);
  727. break;
  728. default:
  729. return -EINVAL;
  730. }
  731. return 0;
  732. }
  733. static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  734. {
  735. struct snd_soc_component *component = codec_dai->component;
  736. u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
  737. ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
  738. u16 master = snd_soc_component_read(component, WM8350_AI_DAC_CONTROL) &
  739. ~WM8350_BCLK_MSTR;
  740. u16 dac_lrc = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
  741. ~WM8350_DACLRC_ENA;
  742. u16 adc_lrc = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
  743. ~WM8350_ADCLRC_ENA;
  744. /* set master/slave audio interface */
  745. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  746. case SND_SOC_DAIFMT_CBM_CFM:
  747. master |= WM8350_BCLK_MSTR;
  748. dac_lrc |= WM8350_DACLRC_ENA;
  749. adc_lrc |= WM8350_ADCLRC_ENA;
  750. break;
  751. case SND_SOC_DAIFMT_CBS_CFS:
  752. break;
  753. default:
  754. return -EINVAL;
  755. }
  756. /* interface format */
  757. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  758. case SND_SOC_DAIFMT_I2S:
  759. iface |= 0x2 << 8;
  760. break;
  761. case SND_SOC_DAIFMT_RIGHT_J:
  762. break;
  763. case SND_SOC_DAIFMT_LEFT_J:
  764. iface |= 0x1 << 8;
  765. break;
  766. case SND_SOC_DAIFMT_DSP_A:
  767. iface |= 0x3 << 8;
  768. break;
  769. case SND_SOC_DAIFMT_DSP_B:
  770. iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
  771. break;
  772. default:
  773. return -EINVAL;
  774. }
  775. /* clock inversion */
  776. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  777. case SND_SOC_DAIFMT_NB_NF:
  778. break;
  779. case SND_SOC_DAIFMT_IB_IF:
  780. iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
  781. break;
  782. case SND_SOC_DAIFMT_IB_NF:
  783. iface |= WM8350_AIF_BCLK_INV;
  784. break;
  785. case SND_SOC_DAIFMT_NB_IF:
  786. iface |= WM8350_AIF_LRCLK_INV;
  787. break;
  788. default:
  789. return -EINVAL;
  790. }
  791. snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
  792. snd_soc_component_write(component, WM8350_AI_DAC_CONTROL, master);
  793. snd_soc_component_write(component, WM8350_DAC_LR_RATE, dac_lrc);
  794. snd_soc_component_write(component, WM8350_ADC_LR_RATE, adc_lrc);
  795. return 0;
  796. }
  797. static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
  798. struct snd_pcm_hw_params *params,
  799. struct snd_soc_dai *codec_dai)
  800. {
  801. struct snd_soc_component *component = codec_dai->component;
  802. struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
  803. struct wm8350 *wm8350 = wm8350_data->wm8350;
  804. u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
  805. ~WM8350_AIF_WL_MASK;
  806. /* bit size */
  807. switch (params_width(params)) {
  808. case 16:
  809. break;
  810. case 20:
  811. iface |= 0x1 << 10;
  812. break;
  813. case 24:
  814. iface |= 0x2 << 10;
  815. break;
  816. case 32:
  817. iface |= 0x3 << 10;
  818. break;
  819. }
  820. snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
  821. /* The sloping stopband filter is recommended for use with
  822. * lower sample rates to improve performance.
  823. */
  824. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  825. if (params_rate(params) < 24000)
  826. wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
  827. WM8350_DAC_SB_FILT);
  828. else
  829. wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
  830. WM8350_DAC_SB_FILT);
  831. }
  832. return 0;
  833. }
  834. static int wm8350_mute(struct snd_soc_dai *dai, int mute, int direction)
  835. {
  836. struct snd_soc_component *component = dai->component;
  837. unsigned int val;
  838. if (mute)
  839. val = WM8350_DAC_MUTE_ENA;
  840. else
  841. val = 0;
  842. snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
  843. return 0;
  844. }
  845. /* FLL divisors */
  846. struct _fll_div {
  847. int div; /* FLL_OUTDIV */
  848. int n;
  849. int k;
  850. int ratio; /* FLL_FRATIO */
  851. };
  852. /* The size in bits of the fll divide multiplied by 10
  853. * to allow rounding later */
  854. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  855. static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
  856. unsigned int output)
  857. {
  858. u64 Kpart;
  859. unsigned int t1, t2, K, Nmod;
  860. if (output >= 2815250 && output <= 3125000)
  861. fll_div->div = 0x4;
  862. else if (output >= 5625000 && output <= 6250000)
  863. fll_div->div = 0x3;
  864. else if (output >= 11250000 && output <= 12500000)
  865. fll_div->div = 0x2;
  866. else if (output >= 22500000 && output <= 25000000)
  867. fll_div->div = 0x1;
  868. else {
  869. printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
  870. return -EINVAL;
  871. }
  872. if (input > 48000)
  873. fll_div->ratio = 1;
  874. else
  875. fll_div->ratio = 8;
  876. t1 = output * (1 << (fll_div->div + 1));
  877. t2 = input * fll_div->ratio;
  878. fll_div->n = t1 / t2;
  879. Nmod = t1 % t2;
  880. if (Nmod) {
  881. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  882. do_div(Kpart, t2);
  883. K = Kpart & 0xFFFFFFFF;
  884. /* Check if we need to round */
  885. if ((K % 10) >= 5)
  886. K += 5;
  887. /* Move down to proper range now rounding is done */
  888. K /= 10;
  889. fll_div->k = K;
  890. } else
  891. fll_div->k = 0;
  892. return 0;
  893. }
  894. static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
  895. int pll_id, int source, unsigned int freq_in,
  896. unsigned int freq_out)
  897. {
  898. struct snd_soc_component *component = codec_dai->component;
  899. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  900. struct wm8350 *wm8350 = priv->wm8350;
  901. struct _fll_div fll_div;
  902. int ret = 0;
  903. u16 fll_1, fll_4;
  904. if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
  905. return 0;
  906. /* power down FLL - we need to do this for reconfiguration */
  907. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
  908. WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
  909. if (freq_out == 0 || freq_in == 0)
  910. return ret;
  911. ret = fll_factors(&fll_div, freq_in, freq_out);
  912. if (ret < 0)
  913. return ret;
  914. dev_dbg(wm8350->dev,
  915. "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
  916. freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
  917. fll_div.ratio);
  918. /* set up N.K & dividers */
  919. fll_1 = snd_soc_component_read(component, WM8350_FLL_CONTROL_1) &
  920. ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
  921. snd_soc_component_write(component, WM8350_FLL_CONTROL_1,
  922. fll_1 | (fll_div.div << 8) | 0x50);
  923. snd_soc_component_write(component, WM8350_FLL_CONTROL_2,
  924. (fll_div.ratio << 11) | (fll_div.
  925. n & WM8350_FLL_N_MASK));
  926. snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);
  927. fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
  928. ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
  929. snd_soc_component_write(component, WM8350_FLL_CONTROL_4,
  930. fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
  931. (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
  932. /* power FLL on */
  933. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
  934. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
  935. priv->fll_freq_out = freq_out;
  936. priv->fll_freq_in = freq_in;
  937. return 0;
  938. }
  939. static int wm8350_set_bias_level(struct snd_soc_component *component,
  940. enum snd_soc_bias_level level)
  941. {
  942. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  943. struct wm8350 *wm8350 = priv->wm8350;
  944. struct wm8350_audio_platform_data *platform =
  945. wm8350->codec.platform_data;
  946. u16 pm1;
  947. int ret;
  948. switch (level) {
  949. case SND_SOC_BIAS_ON:
  950. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  951. ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
  952. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  953. pm1 | WM8350_VMID_50K |
  954. platform->codec_current_on << 14);
  955. break;
  956. case SND_SOC_BIAS_PREPARE:
  957. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
  958. pm1 &= ~WM8350_VMID_MASK;
  959. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  960. pm1 | WM8350_VMID_50K);
  961. break;
  962. case SND_SOC_BIAS_STANDBY:
  963. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
  964. ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
  965. priv->supplies);
  966. if (ret != 0)
  967. return ret;
  968. /* Enable the system clock */
  969. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
  970. WM8350_SYSCLK_ENA);
  971. /* mute DAC & outputs */
  972. wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
  973. WM8350_DAC_MUTE_ENA);
  974. /* discharge cap memory */
  975. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  976. platform->dis_out1 |
  977. (platform->dis_out2 << 2) |
  978. (platform->dis_out3 << 4) |
  979. (platform->dis_out4 << 6));
  980. /* wait for discharge */
  981. schedule_timeout_interruptible(msecs_to_jiffies
  982. (platform->
  983. cap_discharge_msecs));
  984. /* enable antipop */
  985. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  986. (platform->vmid_s_curve << 8));
  987. /* ramp up vmid */
  988. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  989. (platform->
  990. codec_current_charge << 14) |
  991. WM8350_VMID_5K | WM8350_VMIDEN |
  992. WM8350_VBUFEN);
  993. /* wait for vmid */
  994. schedule_timeout_interruptible(msecs_to_jiffies
  995. (platform->
  996. vmid_charge_msecs));
  997. /* turn on vmid 300k */
  998. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  999. ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
  1000. pm1 |= WM8350_VMID_300K |
  1001. (platform->codec_current_standby << 14);
  1002. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  1003. pm1);
  1004. /* enable analogue bias */
  1005. pm1 |= WM8350_BIASEN;
  1006. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
  1007. /* disable antipop */
  1008. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
  1009. } else {
  1010. /* turn on vmid 300k and reduce current */
  1011. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1012. ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
  1013. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  1014. pm1 | WM8350_VMID_300K |
  1015. (platform->
  1016. codec_current_standby << 14));
  1017. }
  1018. break;
  1019. case SND_SOC_BIAS_OFF:
  1020. /* mute DAC & enable outputs */
  1021. wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
  1022. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
  1023. WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
  1024. WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
  1025. /* enable anti pop S curve */
  1026. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  1027. (platform->vmid_s_curve << 8));
  1028. /* turn off vmid */
  1029. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1030. ~WM8350_VMIDEN;
  1031. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
  1032. /* wait */
  1033. schedule_timeout_interruptible(msecs_to_jiffies
  1034. (platform->
  1035. vmid_discharge_msecs));
  1036. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
  1037. (platform->vmid_s_curve << 8) |
  1038. platform->dis_out1 |
  1039. (platform->dis_out2 << 2) |
  1040. (platform->dis_out3 << 4) |
  1041. (platform->dis_out4 << 6));
  1042. /* turn off VBuf and drain */
  1043. pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
  1044. ~(WM8350_VBUFEN | WM8350_VMID_MASK);
  1045. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
  1046. pm1 | WM8350_OUTPUT_DRAIN_EN);
  1047. /* wait */
  1048. schedule_timeout_interruptible(msecs_to_jiffies
  1049. (platform->drain_msecs));
  1050. pm1 &= ~WM8350_BIASEN;
  1051. wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
  1052. /* disable anti-pop */
  1053. wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
  1054. wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
  1055. WM8350_OUT1L_ENA);
  1056. wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
  1057. WM8350_OUT1R_ENA);
  1058. wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
  1059. WM8350_OUT2L_ENA);
  1060. wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
  1061. WM8350_OUT2R_ENA);
  1062. /* disable clock gen */
  1063. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
  1064. WM8350_SYSCLK_ENA);
  1065. regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  1066. priv->supplies);
  1067. break;
  1068. }
  1069. return 0;
  1070. }
  1071. static void wm8350_hp_work(struct wm8350_data *priv,
  1072. struct wm8350_jack_data *jack,
  1073. u16 mask)
  1074. {
  1075. struct wm8350 *wm8350 = priv->wm8350;
  1076. u16 reg;
  1077. int report;
  1078. reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
  1079. if (reg & mask)
  1080. report = jack->report;
  1081. else
  1082. report = 0;
  1083. snd_soc_jack_report(jack->jack, report, jack->report);
  1084. }
  1085. static void wm8350_hpl_work(struct work_struct *work)
  1086. {
  1087. struct wm8350_data *priv =
  1088. container_of(work, struct wm8350_data, hpl.work.work);
  1089. wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
  1090. }
  1091. static void wm8350_hpr_work(struct work_struct *work)
  1092. {
  1093. struct wm8350_data *priv =
  1094. container_of(work, struct wm8350_data, hpr.work.work);
  1095. wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
  1096. }
  1097. static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
  1098. {
  1099. struct wm8350_data *priv = data;
  1100. struct wm8350 *wm8350 = priv->wm8350;
  1101. #ifndef CONFIG_SND_SOC_WM8350_MODULE
  1102. trace_snd_soc_jack_irq("WM8350 HPL");
  1103. #endif
  1104. if (device_may_wakeup(wm8350->dev))
  1105. pm_wakeup_event(wm8350->dev, 250);
  1106. queue_delayed_work(system_power_efficient_wq,
  1107. &priv->hpl.work, msecs_to_jiffies(200));
  1108. return IRQ_HANDLED;
  1109. }
  1110. static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
  1111. {
  1112. struct wm8350_data *priv = data;
  1113. struct wm8350 *wm8350 = priv->wm8350;
  1114. #ifndef CONFIG_SND_SOC_WM8350_MODULE
  1115. trace_snd_soc_jack_irq("WM8350 HPR");
  1116. #endif
  1117. if (device_may_wakeup(wm8350->dev))
  1118. pm_wakeup_event(wm8350->dev, 250);
  1119. queue_delayed_work(system_power_efficient_wq,
  1120. &priv->hpr.work, msecs_to_jiffies(200));
  1121. return IRQ_HANDLED;
  1122. }
  1123. /**
  1124. * wm8350_hp_jack_detect - Enable headphone jack detection.
  1125. *
  1126. * @component: WM8350 component
  1127. * @which: left or right jack detect signal
  1128. * @jack: jack to report detection events on
  1129. * @report: value to report
  1130. *
  1131. * Enables the headphone jack detection of the WM8350. If no report
  1132. * is specified then detection is disabled.
  1133. */
  1134. int wm8350_hp_jack_detect(struct snd_soc_component *component, enum wm8350_jack which,
  1135. struct snd_soc_jack *jack, int report)
  1136. {
  1137. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  1138. struct wm8350 *wm8350 = priv->wm8350;
  1139. int ena;
  1140. switch (which) {
  1141. case WM8350_JDL:
  1142. priv->hpl.jack = jack;
  1143. priv->hpl.report = report;
  1144. ena = WM8350_JDL_ENA;
  1145. break;
  1146. case WM8350_JDR:
  1147. priv->hpr.jack = jack;
  1148. priv->hpr.report = report;
  1149. ena = WM8350_JDR_ENA;
  1150. break;
  1151. default:
  1152. return -EINVAL;
  1153. }
  1154. if (report) {
  1155. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
  1156. wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
  1157. } else {
  1158. wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
  1159. }
  1160. /* Sync status */
  1161. switch (which) {
  1162. case WM8350_JDL:
  1163. wm8350_hpl_jack_handler(0, priv);
  1164. break;
  1165. case WM8350_JDR:
  1166. wm8350_hpr_jack_handler(0, priv);
  1167. break;
  1168. }
  1169. return 0;
  1170. }
  1171. EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
  1172. static irqreturn_t wm8350_mic_handler(int irq, void *data)
  1173. {
  1174. struct wm8350_data *priv = data;
  1175. struct wm8350 *wm8350 = priv->wm8350;
  1176. u16 reg;
  1177. int report = 0;
  1178. #ifndef CONFIG_SND_SOC_WM8350_MODULE
  1179. trace_snd_soc_jack_irq("WM8350 mic");
  1180. #endif
  1181. reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
  1182. if (reg & WM8350_JACK_MICSCD_LVL)
  1183. report |= priv->mic.short_report;
  1184. if (reg & WM8350_JACK_MICSD_LVL)
  1185. report |= priv->mic.report;
  1186. snd_soc_jack_report(priv->mic.jack, report,
  1187. priv->mic.report | priv->mic.short_report);
  1188. return IRQ_HANDLED;
  1189. }
  1190. /**
  1191. * wm8350_mic_jack_detect - Enable microphone jack detection.
  1192. *
  1193. * @component: WM8350 component
  1194. * @jack: jack to report detection events on
  1195. * @detect_report: value to report when presence detected
  1196. * @short_report: value to report when microphone short detected
  1197. *
  1198. * Enables the microphone jack detection of the WM8350. If both reports
  1199. * are specified as zero then detection is disabled.
  1200. */
  1201. int wm8350_mic_jack_detect(struct snd_soc_component *component,
  1202. struct snd_soc_jack *jack,
  1203. int detect_report, int short_report)
  1204. {
  1205. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  1206. struct wm8350 *wm8350 = priv->wm8350;
  1207. priv->mic.jack = jack;
  1208. priv->mic.report = detect_report;
  1209. priv->mic.short_report = short_report;
  1210. if (detect_report || short_report) {
  1211. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
  1212. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
  1213. WM8350_MIC_DET_ENA);
  1214. } else {
  1215. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
  1216. WM8350_MIC_DET_ENA);
  1217. }
  1218. return 0;
  1219. }
  1220. EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
  1221. #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
  1222. #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  1223. SNDRV_PCM_FMTBIT_S20_3LE |\
  1224. SNDRV_PCM_FMTBIT_S24_LE)
  1225. static const struct snd_soc_dai_ops wm8350_dai_ops = {
  1226. .hw_params = wm8350_pcm_hw_params,
  1227. .mute_stream = wm8350_mute,
  1228. .set_fmt = wm8350_set_dai_fmt,
  1229. .set_sysclk = wm8350_set_dai_sysclk,
  1230. .set_pll = wm8350_set_fll,
  1231. .set_clkdiv = wm8350_set_clkdiv,
  1232. .no_capture_mute = 1,
  1233. };
  1234. static struct snd_soc_dai_driver wm8350_dai = {
  1235. .name = "wm8350-hifi",
  1236. .playback = {
  1237. .stream_name = "Playback",
  1238. .channels_min = 1,
  1239. .channels_max = 2,
  1240. .rates = WM8350_RATES,
  1241. .formats = WM8350_FORMATS,
  1242. },
  1243. .capture = {
  1244. .stream_name = "Capture",
  1245. .channels_min = 1,
  1246. .channels_max = 2,
  1247. .rates = WM8350_RATES,
  1248. .formats = WM8350_FORMATS,
  1249. },
  1250. .ops = &wm8350_dai_ops,
  1251. };
  1252. static int wm8350_component_probe(struct snd_soc_component *component)
  1253. {
  1254. struct wm8350 *wm8350 = dev_get_platdata(component->dev);
  1255. struct wm8350_data *priv;
  1256. struct wm8350_output *out1;
  1257. struct wm8350_output *out2;
  1258. int ret, i;
  1259. if (wm8350->codec.platform_data == NULL) {
  1260. dev_err(component->dev, "No audio platform data supplied\n");
  1261. return -EINVAL;
  1262. }
  1263. priv = devm_kzalloc(component->dev, sizeof(struct wm8350_data),
  1264. GFP_KERNEL);
  1265. if (priv == NULL)
  1266. return -ENOMEM;
  1267. snd_soc_component_init_regmap(component, wm8350->regmap);
  1268. snd_soc_component_set_drvdata(component, priv);
  1269. priv->wm8350 = wm8350;
  1270. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  1271. priv->supplies[i].supply = supply_names[i];
  1272. ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
  1273. priv->supplies);
  1274. if (ret != 0)
  1275. return ret;
  1276. /* Put the codec into reset if it wasn't already */
  1277. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
  1278. INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
  1279. INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
  1280. INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
  1281. /* Enable the codec */
  1282. wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
  1283. /* Enable robust clocking mode in ADC */
  1284. snd_soc_component_write(component, WM8350_SECURITY, 0xa7);
  1285. snd_soc_component_write(component, 0xde, 0x13);
  1286. snd_soc_component_write(component, WM8350_SECURITY, 0);
  1287. /* read OUT1 & OUT2 volumes */
  1288. out1 = &priv->out1;
  1289. out2 = &priv->out2;
  1290. out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
  1291. WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  1292. out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
  1293. WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  1294. out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
  1295. WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  1296. out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
  1297. WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
  1298. wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
  1299. wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
  1300. wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
  1301. wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
  1302. /* Latch VU bits & mute */
  1303. wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
  1304. WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
  1305. wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
  1306. WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
  1307. wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
  1308. WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
  1309. wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
  1310. WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
  1311. /* Make sure AIF tristating is disabled by default */
  1312. wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
  1313. /* Make sure we've got a sane companding setup too */
  1314. wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
  1315. WM8350_DAC_COMP | WM8350_LOOPBACK);
  1316. /* Make sure jack detect is disabled to start off with */
  1317. wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
  1318. WM8350_JDL_ENA | WM8350_JDR_ENA);
  1319. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
  1320. wm8350_hpl_jack_handler, 0, "Left jack detect",
  1321. priv);
  1322. if (ret != 0)
  1323. goto err;
  1324. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
  1325. wm8350_hpr_jack_handler, 0, "Right jack detect",
  1326. priv);
  1327. if (ret != 0)
  1328. goto free_jck_det_l;
  1329. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
  1330. wm8350_mic_handler, 0, "Microphone short", priv);
  1331. if (ret != 0)
  1332. goto free_jck_det_r;
  1333. ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
  1334. wm8350_mic_handler, 0, "Microphone detect", priv);
  1335. if (ret != 0)
  1336. goto free_micscd;
  1337. return 0;
  1338. free_micscd:
  1339. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
  1340. free_jck_det_r:
  1341. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
  1342. free_jck_det_l:
  1343. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
  1344. err:
  1345. return ret;
  1346. }
  1347. static void wm8350_component_remove(struct snd_soc_component *component)
  1348. {
  1349. struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
  1350. struct wm8350 *wm8350 = dev_get_platdata(component->dev);
  1351. wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
  1352. WM8350_JDL_ENA | WM8350_JDR_ENA);
  1353. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
  1354. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
  1355. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
  1356. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
  1357. wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
  1358. priv->hpl.jack = NULL;
  1359. priv->hpr.jack = NULL;
  1360. priv->mic.jack = NULL;
  1361. cancel_delayed_work_sync(&priv->hpl.work);
  1362. cancel_delayed_work_sync(&priv->hpr.work);
  1363. /* if there was any work waiting then we run it now and
  1364. * wait for its completion */
  1365. flush_delayed_work(&priv->pga_work);
  1366. wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
  1367. }
  1368. static const struct snd_soc_component_driver soc_component_dev_wm8350 = {
  1369. .probe = wm8350_component_probe,
  1370. .remove = wm8350_component_remove,
  1371. .set_bias_level = wm8350_set_bias_level,
  1372. .controls = wm8350_snd_controls,
  1373. .num_controls = ARRAY_SIZE(wm8350_snd_controls),
  1374. .dapm_widgets = wm8350_dapm_widgets,
  1375. .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
  1376. .dapm_routes = wm8350_dapm_routes,
  1377. .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
  1378. .suspend_bias_off = 1,
  1379. .idle_bias_on = 1,
  1380. .use_pmdown_time = 1,
  1381. .endianness = 1,
  1382. .non_legacy_dai_naming = 1,
  1383. };
  1384. static int wm8350_probe(struct platform_device *pdev)
  1385. {
  1386. return devm_snd_soc_register_component(&pdev->dev,
  1387. &soc_component_dev_wm8350,
  1388. &wm8350_dai, 1);
  1389. }
  1390. static struct platform_driver wm8350_codec_driver = {
  1391. .driver = {
  1392. .name = "wm8350-codec",
  1393. },
  1394. .probe = wm8350_probe,
  1395. };
  1396. module_platform_driver(wm8350_codec_driver);
  1397. MODULE_DESCRIPTION("ASoC WM8350 driver");
  1398. MODULE_AUTHOR("Liam Girdwood");
  1399. MODULE_LICENSE("GPL");
  1400. MODULE_ALIAS("platform:wm8350-codec");