wm2200.h 181 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * wm2200.h - WM2200 audio codec interface
  4. *
  5. * Copyright 2012 Wolfson Microelectronics PLC.
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. */
  8. #ifndef _WM2200_H
  9. #define _WM2200_H
  10. #define WM2200_CLK_SYSCLK 1
  11. #define WM2200_CLKSRC_MCLK1 0
  12. #define WM2200_CLKSRC_MCLK2 1
  13. #define WM2200_CLKSRC_FLL 4
  14. #define WM2200_CLKSRC_BCLK1 8
  15. #define WM2200_FLL_SRC_MCLK1 0
  16. #define WM2200_FLL_SRC_MCLK2 1
  17. #define WM2200_FLL_SRC_BCLK 2
  18. /*
  19. * Register values.
  20. */
  21. #define WM2200_SOFTWARE_RESET 0x00
  22. #define WM2200_DEVICE_REVISION 0x01
  23. #define WM2200_TONE_GENERATOR_1 0x0B
  24. #define WM2200_CLOCKING_3 0x102
  25. #define WM2200_CLOCKING_4 0x103
  26. #define WM2200_FLL_CONTROL_1 0x111
  27. #define WM2200_FLL_CONTROL_2 0x112
  28. #define WM2200_FLL_CONTROL_3 0x113
  29. #define WM2200_FLL_CONTROL_4 0x114
  30. #define WM2200_FLL_CONTROL_6 0x116
  31. #define WM2200_FLL_CONTROL_7 0x117
  32. #define WM2200_FLL_EFS_1 0x119
  33. #define WM2200_FLL_EFS_2 0x11A
  34. #define WM2200_MIC_CHARGE_PUMP_1 0x200
  35. #define WM2200_MIC_CHARGE_PUMP_2 0x201
  36. #define WM2200_DM_CHARGE_PUMP_1 0x202
  37. #define WM2200_MIC_BIAS_CTRL_1 0x20C
  38. #define WM2200_MIC_BIAS_CTRL_2 0x20D
  39. #define WM2200_EAR_PIECE_CTRL_1 0x20F
  40. #define WM2200_EAR_PIECE_CTRL_2 0x210
  41. #define WM2200_INPUT_ENABLES 0x301
  42. #define WM2200_IN1L_CONTROL 0x302
  43. #define WM2200_IN1R_CONTROL 0x303
  44. #define WM2200_IN2L_CONTROL 0x304
  45. #define WM2200_IN2R_CONTROL 0x305
  46. #define WM2200_IN3L_CONTROL 0x306
  47. #define WM2200_IN3R_CONTROL 0x307
  48. #define WM2200_RXANC_SRC 0x30A
  49. #define WM2200_INPUT_VOLUME_RAMP 0x30B
  50. #define WM2200_ADC_DIGITAL_VOLUME_1L 0x30C
  51. #define WM2200_ADC_DIGITAL_VOLUME_1R 0x30D
  52. #define WM2200_ADC_DIGITAL_VOLUME_2L 0x30E
  53. #define WM2200_ADC_DIGITAL_VOLUME_2R 0x30F
  54. #define WM2200_ADC_DIGITAL_VOLUME_3L 0x310
  55. #define WM2200_ADC_DIGITAL_VOLUME_3R 0x311
  56. #define WM2200_OUTPUT_ENABLES 0x400
  57. #define WM2200_DAC_VOLUME_LIMIT_1L 0x401
  58. #define WM2200_DAC_VOLUME_LIMIT_1R 0x402
  59. #define WM2200_DAC_VOLUME_LIMIT_2L 0x403
  60. #define WM2200_DAC_VOLUME_LIMIT_2R 0x404
  61. #define WM2200_DAC_AEC_CONTROL_1 0x409
  62. #define WM2200_OUTPUT_VOLUME_RAMP 0x40A
  63. #define WM2200_DAC_DIGITAL_VOLUME_1L 0x40B
  64. #define WM2200_DAC_DIGITAL_VOLUME_1R 0x40C
  65. #define WM2200_DAC_DIGITAL_VOLUME_2L 0x40D
  66. #define WM2200_DAC_DIGITAL_VOLUME_2R 0x40E
  67. #define WM2200_PDM_1 0x417
  68. #define WM2200_PDM_2 0x418
  69. #define WM2200_AUDIO_IF_1_1 0x500
  70. #define WM2200_AUDIO_IF_1_2 0x501
  71. #define WM2200_AUDIO_IF_1_3 0x502
  72. #define WM2200_AUDIO_IF_1_4 0x503
  73. #define WM2200_AUDIO_IF_1_5 0x504
  74. #define WM2200_AUDIO_IF_1_6 0x505
  75. #define WM2200_AUDIO_IF_1_7 0x506
  76. #define WM2200_AUDIO_IF_1_8 0x507
  77. #define WM2200_AUDIO_IF_1_9 0x508
  78. #define WM2200_AUDIO_IF_1_10 0x509
  79. #define WM2200_AUDIO_IF_1_11 0x50A
  80. #define WM2200_AUDIO_IF_1_12 0x50B
  81. #define WM2200_AUDIO_IF_1_13 0x50C
  82. #define WM2200_AUDIO_IF_1_14 0x50D
  83. #define WM2200_AUDIO_IF_1_15 0x50E
  84. #define WM2200_AUDIO_IF_1_16 0x50F
  85. #define WM2200_AUDIO_IF_1_17 0x510
  86. #define WM2200_AUDIO_IF_1_18 0x511
  87. #define WM2200_AUDIO_IF_1_19 0x512
  88. #define WM2200_AUDIO_IF_1_20 0x513
  89. #define WM2200_AUDIO_IF_1_21 0x514
  90. #define WM2200_AUDIO_IF_1_22 0x515
  91. #define WM2200_OUT1LMIX_INPUT_1_SOURCE 0x600
  92. #define WM2200_OUT1LMIX_INPUT_1_VOLUME 0x601
  93. #define WM2200_OUT1LMIX_INPUT_2_SOURCE 0x602
  94. #define WM2200_OUT1LMIX_INPUT_2_VOLUME 0x603
  95. #define WM2200_OUT1LMIX_INPUT_3_SOURCE 0x604
  96. #define WM2200_OUT1LMIX_INPUT_3_VOLUME 0x605
  97. #define WM2200_OUT1LMIX_INPUT_4_SOURCE 0x606
  98. #define WM2200_OUT1LMIX_INPUT_4_VOLUME 0x607
  99. #define WM2200_OUT1RMIX_INPUT_1_SOURCE 0x608
  100. #define WM2200_OUT1RMIX_INPUT_1_VOLUME 0x609
  101. #define WM2200_OUT1RMIX_INPUT_2_SOURCE 0x60A
  102. #define WM2200_OUT1RMIX_INPUT_2_VOLUME 0x60B
  103. #define WM2200_OUT1RMIX_INPUT_3_SOURCE 0x60C
  104. #define WM2200_OUT1RMIX_INPUT_3_VOLUME 0x60D
  105. #define WM2200_OUT1RMIX_INPUT_4_SOURCE 0x60E
  106. #define WM2200_OUT1RMIX_INPUT_4_VOLUME 0x60F
  107. #define WM2200_OUT2LMIX_INPUT_1_SOURCE 0x610
  108. #define WM2200_OUT2LMIX_INPUT_1_VOLUME 0x611
  109. #define WM2200_OUT2LMIX_INPUT_2_SOURCE 0x612
  110. #define WM2200_OUT2LMIX_INPUT_2_VOLUME 0x613
  111. #define WM2200_OUT2LMIX_INPUT_3_SOURCE 0x614
  112. #define WM2200_OUT2LMIX_INPUT_3_VOLUME 0x615
  113. #define WM2200_OUT2LMIX_INPUT_4_SOURCE 0x616
  114. #define WM2200_OUT2LMIX_INPUT_4_VOLUME 0x617
  115. #define WM2200_OUT2RMIX_INPUT_1_SOURCE 0x618
  116. #define WM2200_OUT2RMIX_INPUT_1_VOLUME 0x619
  117. #define WM2200_OUT2RMIX_INPUT_2_SOURCE 0x61A
  118. #define WM2200_OUT2RMIX_INPUT_2_VOLUME 0x61B
  119. #define WM2200_OUT2RMIX_INPUT_3_SOURCE 0x61C
  120. #define WM2200_OUT2RMIX_INPUT_3_VOLUME 0x61D
  121. #define WM2200_OUT2RMIX_INPUT_4_SOURCE 0x61E
  122. #define WM2200_OUT2RMIX_INPUT_4_VOLUME 0x61F
  123. #define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0x620
  124. #define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0x621
  125. #define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0x622
  126. #define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0x623
  127. #define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0x624
  128. #define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0x625
  129. #define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0x626
  130. #define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0x627
  131. #define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0x628
  132. #define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0x629
  133. #define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0x62A
  134. #define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0x62B
  135. #define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0x62C
  136. #define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0x62D
  137. #define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0x62E
  138. #define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0x62F
  139. #define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0x630
  140. #define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0x631
  141. #define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0x632
  142. #define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0x633
  143. #define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0x634
  144. #define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0x635
  145. #define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0x636
  146. #define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0x637
  147. #define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0x638
  148. #define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0x639
  149. #define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0x63A
  150. #define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0x63B
  151. #define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0x63C
  152. #define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0x63D
  153. #define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0x63E
  154. #define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0x63F
  155. #define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0x640
  156. #define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0x641
  157. #define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0x642
  158. #define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0x643
  159. #define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0x644
  160. #define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0x645
  161. #define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0x646
  162. #define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0x647
  163. #define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0x648
  164. #define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0x649
  165. #define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0x64A
  166. #define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0x64B
  167. #define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0x64C
  168. #define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0x64D
  169. #define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0x64E
  170. #define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0x64F
  171. #define WM2200_EQLMIX_INPUT_1_SOURCE 0x650
  172. #define WM2200_EQLMIX_INPUT_1_VOLUME 0x651
  173. #define WM2200_EQLMIX_INPUT_2_SOURCE 0x652
  174. #define WM2200_EQLMIX_INPUT_2_VOLUME 0x653
  175. #define WM2200_EQLMIX_INPUT_3_SOURCE 0x654
  176. #define WM2200_EQLMIX_INPUT_3_VOLUME 0x655
  177. #define WM2200_EQLMIX_INPUT_4_SOURCE 0x656
  178. #define WM2200_EQLMIX_INPUT_4_VOLUME 0x657
  179. #define WM2200_EQRMIX_INPUT_1_SOURCE 0x658
  180. #define WM2200_EQRMIX_INPUT_1_VOLUME 0x659
  181. #define WM2200_EQRMIX_INPUT_2_SOURCE 0x65A
  182. #define WM2200_EQRMIX_INPUT_2_VOLUME 0x65B
  183. #define WM2200_EQRMIX_INPUT_3_SOURCE 0x65C
  184. #define WM2200_EQRMIX_INPUT_3_VOLUME 0x65D
  185. #define WM2200_EQRMIX_INPUT_4_SOURCE 0x65E
  186. #define WM2200_EQRMIX_INPUT_4_VOLUME 0x65F
  187. #define WM2200_LHPF1MIX_INPUT_1_SOURCE 0x660
  188. #define WM2200_LHPF1MIX_INPUT_1_VOLUME 0x661
  189. #define WM2200_LHPF1MIX_INPUT_2_SOURCE 0x662
  190. #define WM2200_LHPF1MIX_INPUT_2_VOLUME 0x663
  191. #define WM2200_LHPF1MIX_INPUT_3_SOURCE 0x664
  192. #define WM2200_LHPF1MIX_INPUT_3_VOLUME 0x665
  193. #define WM2200_LHPF1MIX_INPUT_4_SOURCE 0x666
  194. #define WM2200_LHPF1MIX_INPUT_4_VOLUME 0x667
  195. #define WM2200_LHPF2MIX_INPUT_1_SOURCE 0x668
  196. #define WM2200_LHPF2MIX_INPUT_1_VOLUME 0x669
  197. #define WM2200_LHPF2MIX_INPUT_2_SOURCE 0x66A
  198. #define WM2200_LHPF2MIX_INPUT_2_VOLUME 0x66B
  199. #define WM2200_LHPF2MIX_INPUT_3_SOURCE 0x66C
  200. #define WM2200_LHPF2MIX_INPUT_3_VOLUME 0x66D
  201. #define WM2200_LHPF2MIX_INPUT_4_SOURCE 0x66E
  202. #define WM2200_LHPF2MIX_INPUT_4_VOLUME 0x66F
  203. #define WM2200_DSP1LMIX_INPUT_1_SOURCE 0x670
  204. #define WM2200_DSP1LMIX_INPUT_1_VOLUME 0x671
  205. #define WM2200_DSP1LMIX_INPUT_2_SOURCE 0x672
  206. #define WM2200_DSP1LMIX_INPUT_2_VOLUME 0x673
  207. #define WM2200_DSP1LMIX_INPUT_3_SOURCE 0x674
  208. #define WM2200_DSP1LMIX_INPUT_3_VOLUME 0x675
  209. #define WM2200_DSP1LMIX_INPUT_4_SOURCE 0x676
  210. #define WM2200_DSP1LMIX_INPUT_4_VOLUME 0x677
  211. #define WM2200_DSP1RMIX_INPUT_1_SOURCE 0x678
  212. #define WM2200_DSP1RMIX_INPUT_1_VOLUME 0x679
  213. #define WM2200_DSP1RMIX_INPUT_2_SOURCE 0x67A
  214. #define WM2200_DSP1RMIX_INPUT_2_VOLUME 0x67B
  215. #define WM2200_DSP1RMIX_INPUT_3_SOURCE 0x67C
  216. #define WM2200_DSP1RMIX_INPUT_3_VOLUME 0x67D
  217. #define WM2200_DSP1RMIX_INPUT_4_SOURCE 0x67E
  218. #define WM2200_DSP1RMIX_INPUT_4_VOLUME 0x67F
  219. #define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0x680
  220. #define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0x681
  221. #define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0x682
  222. #define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0x683
  223. #define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0x684
  224. #define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0x685
  225. #define WM2200_DSP2LMIX_INPUT_1_SOURCE 0x686
  226. #define WM2200_DSP2LMIX_INPUT_1_VOLUME 0x687
  227. #define WM2200_DSP2LMIX_INPUT_2_SOURCE 0x688
  228. #define WM2200_DSP2LMIX_INPUT_2_VOLUME 0x689
  229. #define WM2200_DSP2LMIX_INPUT_3_SOURCE 0x68A
  230. #define WM2200_DSP2LMIX_INPUT_3_VOLUME 0x68B
  231. #define WM2200_DSP2LMIX_INPUT_4_SOURCE 0x68C
  232. #define WM2200_DSP2LMIX_INPUT_4_VOLUME 0x68D
  233. #define WM2200_DSP2RMIX_INPUT_1_SOURCE 0x68E
  234. #define WM2200_DSP2RMIX_INPUT_1_VOLUME 0x68F
  235. #define WM2200_DSP2RMIX_INPUT_2_SOURCE 0x690
  236. #define WM2200_DSP2RMIX_INPUT_2_VOLUME 0x691
  237. #define WM2200_DSP2RMIX_INPUT_3_SOURCE 0x692
  238. #define WM2200_DSP2RMIX_INPUT_3_VOLUME 0x693
  239. #define WM2200_DSP2RMIX_INPUT_4_SOURCE 0x694
  240. #define WM2200_DSP2RMIX_INPUT_4_VOLUME 0x695
  241. #define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0x696
  242. #define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0x697
  243. #define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0x698
  244. #define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0x699
  245. #define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0x69A
  246. #define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0x69B
  247. #define WM2200_GPIO_CTRL_1 0x700
  248. #define WM2200_GPIO_CTRL_2 0x701
  249. #define WM2200_GPIO_CTRL_3 0x702
  250. #define WM2200_GPIO_CTRL_4 0x703
  251. #define WM2200_ADPS1_IRQ0 0x707
  252. #define WM2200_ADPS1_IRQ1 0x708
  253. #define WM2200_MISC_PAD_CTRL_1 0x709
  254. #define WM2200_INTERRUPT_STATUS_1 0x800
  255. #define WM2200_INTERRUPT_STATUS_1_MASK 0x801
  256. #define WM2200_INTERRUPT_STATUS_2 0x802
  257. #define WM2200_INTERRUPT_RAW_STATUS_2 0x803
  258. #define WM2200_INTERRUPT_STATUS_2_MASK 0x804
  259. #define WM2200_INTERRUPT_CONTROL 0x808
  260. #define WM2200_EQL_1 0x900
  261. #define WM2200_EQL_2 0x901
  262. #define WM2200_EQL_3 0x902
  263. #define WM2200_EQL_4 0x903
  264. #define WM2200_EQL_5 0x904
  265. #define WM2200_EQL_6 0x905
  266. #define WM2200_EQL_7 0x906
  267. #define WM2200_EQL_8 0x907
  268. #define WM2200_EQL_9 0x908
  269. #define WM2200_EQL_10 0x909
  270. #define WM2200_EQL_11 0x90A
  271. #define WM2200_EQL_12 0x90B
  272. #define WM2200_EQL_13 0x90C
  273. #define WM2200_EQL_14 0x90D
  274. #define WM2200_EQL_15 0x90E
  275. #define WM2200_EQL_16 0x90F
  276. #define WM2200_EQL_17 0x910
  277. #define WM2200_EQL_18 0x911
  278. #define WM2200_EQL_19 0x912
  279. #define WM2200_EQL_20 0x913
  280. #define WM2200_EQR_1 0x916
  281. #define WM2200_EQR_2 0x917
  282. #define WM2200_EQR_3 0x918
  283. #define WM2200_EQR_4 0x919
  284. #define WM2200_EQR_5 0x91A
  285. #define WM2200_EQR_6 0x91B
  286. #define WM2200_EQR_7 0x91C
  287. #define WM2200_EQR_8 0x91D
  288. #define WM2200_EQR_9 0x91E
  289. #define WM2200_EQR_10 0x91F
  290. #define WM2200_EQR_11 0x920
  291. #define WM2200_EQR_12 0x921
  292. #define WM2200_EQR_13 0x922
  293. #define WM2200_EQR_14 0x923
  294. #define WM2200_EQR_15 0x924
  295. #define WM2200_EQR_16 0x925
  296. #define WM2200_EQR_17 0x926
  297. #define WM2200_EQR_18 0x927
  298. #define WM2200_EQR_19 0x928
  299. #define WM2200_EQR_20 0x929
  300. #define WM2200_HPLPF1_1 0x93E
  301. #define WM2200_HPLPF1_2 0x93F
  302. #define WM2200_HPLPF2_1 0x942
  303. #define WM2200_HPLPF2_2 0x943
  304. #define WM2200_DSP1_CONTROL_1 0xA00
  305. #define WM2200_DSP1_CONTROL_2 0xA02
  306. #define WM2200_DSP1_CONTROL_3 0xA03
  307. #define WM2200_DSP1_CONTROL_4 0xA04
  308. #define WM2200_DSP1_CONTROL_5 0xA06
  309. #define WM2200_DSP1_CONTROL_6 0xA07
  310. #define WM2200_DSP1_CONTROL_7 0xA08
  311. #define WM2200_DSP1_CONTROL_8 0xA09
  312. #define WM2200_DSP1_CONTROL_9 0xA0A
  313. #define WM2200_DSP1_CONTROL_10 0xA0B
  314. #define WM2200_DSP1_CONTROL_11 0xA0C
  315. #define WM2200_DSP1_CONTROL_12 0xA0D
  316. #define WM2200_DSP1_CONTROL_13 0xA0F
  317. #define WM2200_DSP1_CONTROL_14 0xA10
  318. #define WM2200_DSP1_CONTROL_15 0xA11
  319. #define WM2200_DSP1_CONTROL_16 0xA12
  320. #define WM2200_DSP1_CONTROL_17 0xA13
  321. #define WM2200_DSP1_CONTROL_18 0xA14
  322. #define WM2200_DSP1_CONTROL_19 0xA16
  323. #define WM2200_DSP1_CONTROL_20 0xA17
  324. #define WM2200_DSP1_CONTROL_21 0xA18
  325. #define WM2200_DSP1_CONTROL_22 0xA1A
  326. #define WM2200_DSP1_CONTROL_23 0xA1B
  327. #define WM2200_DSP1_CONTROL_24 0xA1C
  328. #define WM2200_DSP1_CONTROL_25 0xA1E
  329. #define WM2200_DSP1_CONTROL_26 0xA20
  330. #define WM2200_DSP1_CONTROL_27 0xA21
  331. #define WM2200_DSP1_CONTROL_28 0xA22
  332. #define WM2200_DSP1_CONTROL_29 0xA23
  333. #define WM2200_DSP1_CONTROL_30 0xA24
  334. #define WM2200_DSP1_CONTROL_31 0xA26
  335. #define WM2200_DSP2_CONTROL_1 0xB00
  336. #define WM2200_DSP2_CONTROL_2 0xB02
  337. #define WM2200_DSP2_CONTROL_3 0xB03
  338. #define WM2200_DSP2_CONTROL_4 0xB04
  339. #define WM2200_DSP2_CONTROL_5 0xB06
  340. #define WM2200_DSP2_CONTROL_6 0xB07
  341. #define WM2200_DSP2_CONTROL_7 0xB08
  342. #define WM2200_DSP2_CONTROL_8 0xB09
  343. #define WM2200_DSP2_CONTROL_9 0xB0A
  344. #define WM2200_DSP2_CONTROL_10 0xB0B
  345. #define WM2200_DSP2_CONTROL_11 0xB0C
  346. #define WM2200_DSP2_CONTROL_12 0xB0D
  347. #define WM2200_DSP2_CONTROL_13 0xB0F
  348. #define WM2200_DSP2_CONTROL_14 0xB10
  349. #define WM2200_DSP2_CONTROL_15 0xB11
  350. #define WM2200_DSP2_CONTROL_16 0xB12
  351. #define WM2200_DSP2_CONTROL_17 0xB13
  352. #define WM2200_DSP2_CONTROL_18 0xB14
  353. #define WM2200_DSP2_CONTROL_19 0xB16
  354. #define WM2200_DSP2_CONTROL_20 0xB17
  355. #define WM2200_DSP2_CONTROL_21 0xB18
  356. #define WM2200_DSP2_CONTROL_22 0xB1A
  357. #define WM2200_DSP2_CONTROL_23 0xB1B
  358. #define WM2200_DSP2_CONTROL_24 0xB1C
  359. #define WM2200_DSP2_CONTROL_25 0xB1E
  360. #define WM2200_DSP2_CONTROL_26 0xB20
  361. #define WM2200_DSP2_CONTROL_27 0xB21
  362. #define WM2200_DSP2_CONTROL_28 0xB22
  363. #define WM2200_DSP2_CONTROL_29 0xB23
  364. #define WM2200_DSP2_CONTROL_30 0xB24
  365. #define WM2200_DSP2_CONTROL_31 0xB26
  366. #define WM2200_ANC_CTRL1 0xD00
  367. #define WM2200_ANC_CTRL2 0xD01
  368. #define WM2200_ANC_CTRL3 0xD02
  369. #define WM2200_ANC_CTRL7 0xD08
  370. #define WM2200_ANC_CTRL8 0xD09
  371. #define WM2200_ANC_CTRL9 0xD0A
  372. #define WM2200_ANC_CTRL10 0xD0B
  373. #define WM2200_ANC_CTRL11 0xD0C
  374. #define WM2200_ANC_CTRL12 0xD0D
  375. #define WM2200_ANC_CTRL13 0xD0E
  376. #define WM2200_ANC_CTRL14 0xD0F
  377. #define WM2200_ANC_CTRL15 0xD10
  378. #define WM2200_ANC_CTRL16 0xD11
  379. #define WM2200_ANC_CTRL17 0xD12
  380. #define WM2200_ANC_CTRL18 0xD15
  381. #define WM2200_ANC_CTRL19 0xD16
  382. #define WM2200_ANC_CTRL20 0xD17
  383. #define WM2200_ANC_CTRL21 0xD18
  384. #define WM2200_ANC_CTRL22 0xD19
  385. #define WM2200_ANC_CTRL23 0xD1A
  386. #define WM2200_ANC_CTRL24 0xD1B
  387. #define WM2200_ANC_CTRL25 0xD1C
  388. #define WM2200_ANC_CTRL26 0xD1D
  389. #define WM2200_ANC_CTRL27 0xD1E
  390. #define WM2200_ANC_CTRL28 0xD1F
  391. #define WM2200_ANC_CTRL29 0xD20
  392. #define WM2200_ANC_CTRL30 0xD21
  393. #define WM2200_ANC_CTRL31 0xD23
  394. #define WM2200_ANC_CTRL32 0xD24
  395. #define WM2200_ANC_CTRL33 0xD25
  396. #define WM2200_ANC_CTRL34 0xD27
  397. #define WM2200_ANC_CTRL35 0xD28
  398. #define WM2200_ANC_CTRL36 0xD29
  399. #define WM2200_ANC_CTRL37 0xD2A
  400. #define WM2200_ANC_CTRL38 0xD2B
  401. #define WM2200_ANC_CTRL39 0xD2C
  402. #define WM2200_ANC_CTRL40 0xD2D
  403. #define WM2200_ANC_CTRL41 0xD2E
  404. #define WM2200_ANC_CTRL42 0xD2F
  405. #define WM2200_ANC_CTRL43 0xD30
  406. #define WM2200_ANC_CTRL44 0xD31
  407. #define WM2200_ANC_CTRL45 0xD32
  408. #define WM2200_ANC_CTRL46 0xD33
  409. #define WM2200_ANC_CTRL47 0xD34
  410. #define WM2200_ANC_CTRL48 0xD35
  411. #define WM2200_ANC_CTRL49 0xD36
  412. #define WM2200_ANC_CTRL50 0xD37
  413. #define WM2200_ANC_CTRL51 0xD38
  414. #define WM2200_ANC_CTRL52 0xD39
  415. #define WM2200_ANC_CTRL53 0xD3A
  416. #define WM2200_ANC_CTRL54 0xD3B
  417. #define WM2200_ANC_CTRL55 0xD3C
  418. #define WM2200_ANC_CTRL56 0xD3D
  419. #define WM2200_ANC_CTRL57 0xD3E
  420. #define WM2200_ANC_CTRL58 0xD3F
  421. #define WM2200_ANC_CTRL59 0xD40
  422. #define WM2200_ANC_CTRL60 0xD41
  423. #define WM2200_ANC_CTRL61 0xD42
  424. #define WM2200_ANC_CTRL62 0xD43
  425. #define WM2200_ANC_CTRL63 0xD44
  426. #define WM2200_ANC_CTRL64 0xD45
  427. #define WM2200_ANC_CTRL65 0xD46
  428. #define WM2200_ANC_CTRL66 0xD47
  429. #define WM2200_ANC_CTRL67 0xD48
  430. #define WM2200_ANC_CTRL68 0xD49
  431. #define WM2200_ANC_CTRL69 0xD4A
  432. #define WM2200_ANC_CTRL70 0xD4B
  433. #define WM2200_ANC_CTRL71 0xD4C
  434. #define WM2200_ANC_CTRL72 0xD4D
  435. #define WM2200_ANC_CTRL73 0xD4E
  436. #define WM2200_ANC_CTRL74 0xD4F
  437. #define WM2200_ANC_CTRL75 0xD50
  438. #define WM2200_ANC_CTRL76 0xD51
  439. #define WM2200_ANC_CTRL77 0xD52
  440. #define WM2200_ANC_CTRL78 0xD53
  441. #define WM2200_ANC_CTRL79 0xD54
  442. #define WM2200_ANC_CTRL80 0xD55
  443. #define WM2200_ANC_CTRL81 0xD56
  444. #define WM2200_ANC_CTRL82 0xD57
  445. #define WM2200_ANC_CTRL83 0xD58
  446. #define WM2200_ANC_CTRL84 0xD5B
  447. #define WM2200_ANC_CTRL85 0xD5C
  448. #define WM2200_ANC_CTRL86 0xD5F
  449. #define WM2200_ANC_CTRL87 0xD60
  450. #define WM2200_ANC_CTRL88 0xD61
  451. #define WM2200_ANC_CTRL89 0xD62
  452. #define WM2200_ANC_CTRL90 0xD63
  453. #define WM2200_ANC_CTRL91 0xD64
  454. #define WM2200_ANC_CTRL92 0xD65
  455. #define WM2200_ANC_CTRL93 0xD66
  456. #define WM2200_ANC_CTRL94 0xD67
  457. #define WM2200_ANC_CTRL95 0xD68
  458. #define WM2200_ANC_CTRL96 0xD69
  459. #define WM2200_DSP1_DM_0 0x3000
  460. #define WM2200_DSP1_DM_1 0x3001
  461. #define WM2200_DSP1_DM_2 0x3002
  462. #define WM2200_DSP1_DM_3 0x3003
  463. #define WM2200_DSP1_DM_2044 0x37FC
  464. #define WM2200_DSP1_DM_2045 0x37FD
  465. #define WM2200_DSP1_DM_2046 0x37FE
  466. #define WM2200_DSP1_DM_2047 0x37FF
  467. #define WM2200_DSP1_PM_0 0x3800
  468. #define WM2200_DSP1_PM_1 0x3801
  469. #define WM2200_DSP1_PM_2 0x3802
  470. #define WM2200_DSP1_PM_3 0x3803
  471. #define WM2200_DSP1_PM_4 0x3804
  472. #define WM2200_DSP1_PM_5 0x3805
  473. #define WM2200_DSP1_PM_762 0x3AFA
  474. #define WM2200_DSP1_PM_763 0x3AFB
  475. #define WM2200_DSP1_PM_764 0x3AFC
  476. #define WM2200_DSP1_PM_765 0x3AFD
  477. #define WM2200_DSP1_PM_766 0x3AFE
  478. #define WM2200_DSP1_PM_767 0x3AFF
  479. #define WM2200_DSP1_ZM_0 0x3C00
  480. #define WM2200_DSP1_ZM_1 0x3C01
  481. #define WM2200_DSP1_ZM_2 0x3C02
  482. #define WM2200_DSP1_ZM_3 0x3C03
  483. #define WM2200_DSP1_ZM_1020 0x3FFC
  484. #define WM2200_DSP1_ZM_1021 0x3FFD
  485. #define WM2200_DSP1_ZM_1022 0x3FFE
  486. #define WM2200_DSP1_ZM_1023 0x3FFF
  487. #define WM2200_DSP2_DM_0 0x4000
  488. #define WM2200_DSP2_DM_1 0x4001
  489. #define WM2200_DSP2_DM_2 0x4002
  490. #define WM2200_DSP2_DM_3 0x4003
  491. #define WM2200_DSP2_DM_2044 0x47FC
  492. #define WM2200_DSP2_DM_2045 0x47FD
  493. #define WM2200_DSP2_DM_2046 0x47FE
  494. #define WM2200_DSP2_DM_2047 0x47FF
  495. #define WM2200_DSP2_PM_0 0x4800
  496. #define WM2200_DSP2_PM_1 0x4801
  497. #define WM2200_DSP2_PM_2 0x4802
  498. #define WM2200_DSP2_PM_3 0x4803
  499. #define WM2200_DSP2_PM_4 0x4804
  500. #define WM2200_DSP2_PM_5 0x4805
  501. #define WM2200_DSP2_PM_762 0x4AFA
  502. #define WM2200_DSP2_PM_763 0x4AFB
  503. #define WM2200_DSP2_PM_764 0x4AFC
  504. #define WM2200_DSP2_PM_765 0x4AFD
  505. #define WM2200_DSP2_PM_766 0x4AFE
  506. #define WM2200_DSP2_PM_767 0x4AFF
  507. #define WM2200_DSP2_ZM_0 0x4C00
  508. #define WM2200_DSP2_ZM_1 0x4C01
  509. #define WM2200_DSP2_ZM_2 0x4C02
  510. #define WM2200_DSP2_ZM_3 0x4C03
  511. #define WM2200_DSP2_ZM_1020 0x4FFC
  512. #define WM2200_DSP2_ZM_1021 0x4FFD
  513. #define WM2200_DSP2_ZM_1022 0x4FFE
  514. #define WM2200_DSP2_ZM_1023 0x4FFF
  515. #define WM2200_REGISTER_COUNT 494
  516. #define WM2200_MAX_REGISTER 0x4FFF
  517. /*
  518. * Field Definitions.
  519. */
  520. /*
  521. * R0 (0x00) - software reset
  522. */
  523. #define WM2200_SW_RESET_CHIP_ID1_MASK 0xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */
  524. #define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */
  525. #define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */
  526. /*
  527. * R1 (0x01) - Device Revision
  528. */
  529. #define WM2200_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */
  530. #define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */
  531. #define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */
  532. /*
  533. * R11 (0x0B) - Tone Generator 1
  534. */
  535. #define WM2200_TONE_ENA 0x0001 /* TONE_ENA */
  536. #define WM2200_TONE_ENA_MASK 0x0001 /* TONE_ENA */
  537. #define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */
  538. #define WM2200_TONE_ENA_WIDTH 1 /* TONE_ENA */
  539. /*
  540. * R258 (0x102) - Clocking 3
  541. */
  542. #define WM2200_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
  543. #define WM2200_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
  544. #define WM2200_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
  545. #define WM2200_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
  546. #define WM2200_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
  547. #define WM2200_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
  548. #define WM2200_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
  549. #define WM2200_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
  550. #define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
  551. #define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
  552. /*
  553. * R259 (0x103) - Clocking 4
  554. */
  555. #define WM2200_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
  556. #define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
  557. #define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
  558. /*
  559. * R273 (0x111) - FLL Control 1
  560. */
  561. #define WM2200_FLL_ENA 0x0001 /* FLL_ENA */
  562. #define WM2200_FLL_ENA_MASK 0x0001 /* FLL_ENA */
  563. #define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */
  564. #define WM2200_FLL_ENA_WIDTH 1 /* FLL_ENA */
  565. /*
  566. * R274 (0x112) - FLL Control 2
  567. */
  568. #define WM2200_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
  569. #define WM2200_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
  570. #define WM2200_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
  571. #define WM2200_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
  572. #define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
  573. #define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
  574. /*
  575. * R275 (0x113) - FLL Control 3
  576. */
  577. #define WM2200_FLL_FRACN_ENA 0x0001 /* FLL_FRACN_ENA */
  578. #define WM2200_FLL_FRACN_ENA_MASK 0x0001 /* FLL_FRACN_ENA */
  579. #define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */
  580. #define WM2200_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */
  581. /*
  582. * R276 (0x114) - FLL Control 4
  583. */
  584. #define WM2200_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */
  585. #define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */
  586. #define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */
  587. /*
  588. * R278 (0x116) - FLL Control 6
  589. */
  590. #define WM2200_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
  591. #define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
  592. #define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
  593. /*
  594. * R279 (0x117) - FLL Control 7
  595. */
  596. #define WM2200_FLL_CLK_REF_DIV_MASK 0x0030 /* FLL_CLK_REF_DIV - [5:4] */
  597. #define WM2200_FLL_CLK_REF_DIV_SHIFT 4 /* FLL_CLK_REF_DIV - [5:4] */
  598. #define WM2200_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [5:4] */
  599. #define WM2200_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */
  600. #define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
  601. #define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
  602. /*
  603. * R281 (0x119) - FLL EFS 1
  604. */
  605. #define WM2200_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */
  606. #define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */
  607. #define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */
  608. /*
  609. * R282 (0x11A) - FLL EFS 2
  610. */
  611. #define WM2200_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */
  612. #define WM2200_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */
  613. #define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */
  614. #define WM2200_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */
  615. /*
  616. * R512 (0x200) - Mic Charge Pump 1
  617. */
  618. #define WM2200_CPMIC_BYPASS_MODE 0x0020 /* CPMIC_BYPASS_MODE */
  619. #define WM2200_CPMIC_BYPASS_MODE_MASK 0x0020 /* CPMIC_BYPASS_MODE */
  620. #define WM2200_CPMIC_BYPASS_MODE_SHIFT 5 /* CPMIC_BYPASS_MODE */
  621. #define WM2200_CPMIC_BYPASS_MODE_WIDTH 1 /* CPMIC_BYPASS_MODE */
  622. #define WM2200_CPMIC_ENA 0x0001 /* CPMIC_ENA */
  623. #define WM2200_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
  624. #define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
  625. #define WM2200_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */
  626. /*
  627. * R513 (0x201) - Mic Charge Pump 2
  628. */
  629. #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
  630. #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT 11 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
  631. #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH 5 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
  632. /*
  633. * R514 (0x202) - DM Charge Pump 1
  634. */
  635. #define WM2200_CPDM_ENA 0x0001 /* CPDM_ENA */
  636. #define WM2200_CPDM_ENA_MASK 0x0001 /* CPDM_ENA */
  637. #define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */
  638. #define WM2200_CPDM_ENA_WIDTH 1 /* CPDM_ENA */
  639. /*
  640. * R524 (0x20C) - Mic Bias Ctrl 1
  641. */
  642. #define WM2200_MICB1_DISCH 0x0040 /* MICB1_DISCH */
  643. #define WM2200_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */
  644. #define WM2200_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */
  645. #define WM2200_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
  646. #define WM2200_MICB1_RATE 0x0020 /* MICB1_RATE */
  647. #define WM2200_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
  648. #define WM2200_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
  649. #define WM2200_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
  650. #define WM2200_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */
  651. #define WM2200_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */
  652. #define WM2200_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */
  653. #define WM2200_MICB1_MODE 0x0002 /* MICB1_MODE */
  654. #define WM2200_MICB1_MODE_MASK 0x0002 /* MICB1_MODE */
  655. #define WM2200_MICB1_MODE_SHIFT 1 /* MICB1_MODE */
  656. #define WM2200_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
  657. #define WM2200_MICB1_ENA 0x0001 /* MICB1_ENA */
  658. #define WM2200_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
  659. #define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
  660. #define WM2200_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
  661. /*
  662. * R525 (0x20D) - Mic Bias Ctrl 2
  663. */
  664. #define WM2200_MICB2_DISCH 0x0040 /* MICB2_DISCH */
  665. #define WM2200_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */
  666. #define WM2200_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */
  667. #define WM2200_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
  668. #define WM2200_MICB2_RATE 0x0020 /* MICB2_RATE */
  669. #define WM2200_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
  670. #define WM2200_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
  671. #define WM2200_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
  672. #define WM2200_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */
  673. #define WM2200_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */
  674. #define WM2200_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */
  675. #define WM2200_MICB2_MODE 0x0002 /* MICB2_MODE */
  676. #define WM2200_MICB2_MODE_MASK 0x0002 /* MICB2_MODE */
  677. #define WM2200_MICB2_MODE_SHIFT 1 /* MICB2_MODE */
  678. #define WM2200_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
  679. #define WM2200_MICB2_ENA 0x0001 /* MICB2_ENA */
  680. #define WM2200_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
  681. #define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
  682. #define WM2200_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
  683. /*
  684. * R527 (0x20F) - Ear Piece Ctrl 1
  685. */
  686. #define WM2200_EPD_LP_ENA 0x4000 /* EPD_LP_ENA */
  687. #define WM2200_EPD_LP_ENA_MASK 0x4000 /* EPD_LP_ENA */
  688. #define WM2200_EPD_LP_ENA_SHIFT 14 /* EPD_LP_ENA */
  689. #define WM2200_EPD_LP_ENA_WIDTH 1 /* EPD_LP_ENA */
  690. #define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */
  691. #define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */
  692. #define WM2200_EPD_OUTP_LP_ENA_SHIFT 13 /* EPD_OUTP_LP_ENA */
  693. #define WM2200_EPD_OUTP_LP_ENA_WIDTH 1 /* EPD_OUTP_LP_ENA */
  694. #define WM2200_EPD_RMV_SHRT_LP 0x1000 /* EPD_RMV_SHRT_LP */
  695. #define WM2200_EPD_RMV_SHRT_LP_MASK 0x1000 /* EPD_RMV_SHRT_LP */
  696. #define WM2200_EPD_RMV_SHRT_LP_SHIFT 12 /* EPD_RMV_SHRT_LP */
  697. #define WM2200_EPD_RMV_SHRT_LP_WIDTH 1 /* EPD_RMV_SHRT_LP */
  698. #define WM2200_EPD_LN_ENA 0x0800 /* EPD_LN_ENA */
  699. #define WM2200_EPD_LN_ENA_MASK 0x0800 /* EPD_LN_ENA */
  700. #define WM2200_EPD_LN_ENA_SHIFT 11 /* EPD_LN_ENA */
  701. #define WM2200_EPD_LN_ENA_WIDTH 1 /* EPD_LN_ENA */
  702. #define WM2200_EPD_OUTP_LN_ENA 0x0400 /* EPD_OUTP_LN_ENA */
  703. #define WM2200_EPD_OUTP_LN_ENA_MASK 0x0400 /* EPD_OUTP_LN_ENA */
  704. #define WM2200_EPD_OUTP_LN_ENA_SHIFT 10 /* EPD_OUTP_LN_ENA */
  705. #define WM2200_EPD_OUTP_LN_ENA_WIDTH 1 /* EPD_OUTP_LN_ENA */
  706. #define WM2200_EPD_RMV_SHRT_LN 0x0200 /* EPD_RMV_SHRT_LN */
  707. #define WM2200_EPD_RMV_SHRT_LN_MASK 0x0200 /* EPD_RMV_SHRT_LN */
  708. #define WM2200_EPD_RMV_SHRT_LN_SHIFT 9 /* EPD_RMV_SHRT_LN */
  709. #define WM2200_EPD_RMV_SHRT_LN_WIDTH 1 /* EPD_RMV_SHRT_LN */
  710. /*
  711. * R528 (0x210) - Ear Piece Ctrl 2
  712. */
  713. #define WM2200_EPD_RP_ENA 0x4000 /* EPD_RP_ENA */
  714. #define WM2200_EPD_RP_ENA_MASK 0x4000 /* EPD_RP_ENA */
  715. #define WM2200_EPD_RP_ENA_SHIFT 14 /* EPD_RP_ENA */
  716. #define WM2200_EPD_RP_ENA_WIDTH 1 /* EPD_RP_ENA */
  717. #define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */
  718. #define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */
  719. #define WM2200_EPD_OUTP_RP_ENA_SHIFT 13 /* EPD_OUTP_RP_ENA */
  720. #define WM2200_EPD_OUTP_RP_ENA_WIDTH 1 /* EPD_OUTP_RP_ENA */
  721. #define WM2200_EPD_RMV_SHRT_RP 0x1000 /* EPD_RMV_SHRT_RP */
  722. #define WM2200_EPD_RMV_SHRT_RP_MASK 0x1000 /* EPD_RMV_SHRT_RP */
  723. #define WM2200_EPD_RMV_SHRT_RP_SHIFT 12 /* EPD_RMV_SHRT_RP */
  724. #define WM2200_EPD_RMV_SHRT_RP_WIDTH 1 /* EPD_RMV_SHRT_RP */
  725. #define WM2200_EPD_RN_ENA 0x0800 /* EPD_RN_ENA */
  726. #define WM2200_EPD_RN_ENA_MASK 0x0800 /* EPD_RN_ENA */
  727. #define WM2200_EPD_RN_ENA_SHIFT 11 /* EPD_RN_ENA */
  728. #define WM2200_EPD_RN_ENA_WIDTH 1 /* EPD_RN_ENA */
  729. #define WM2200_EPD_OUTP_RN_ENA 0x0400 /* EPD_OUTP_RN_ENA */
  730. #define WM2200_EPD_OUTP_RN_ENA_MASK 0x0400 /* EPD_OUTP_RN_ENA */
  731. #define WM2200_EPD_OUTP_RN_ENA_SHIFT 10 /* EPD_OUTP_RN_ENA */
  732. #define WM2200_EPD_OUTP_RN_ENA_WIDTH 1 /* EPD_OUTP_RN_ENA */
  733. #define WM2200_EPD_RMV_SHRT_RN 0x0200 /* EPD_RMV_SHRT_RN */
  734. #define WM2200_EPD_RMV_SHRT_RN_MASK 0x0200 /* EPD_RMV_SHRT_RN */
  735. #define WM2200_EPD_RMV_SHRT_RN_SHIFT 9 /* EPD_RMV_SHRT_RN */
  736. #define WM2200_EPD_RMV_SHRT_RN_WIDTH 1 /* EPD_RMV_SHRT_RN */
  737. /*
  738. * R769 (0x301) - Input Enables
  739. */
  740. #define WM2200_IN3L_ENA 0x0020 /* IN3L_ENA */
  741. #define WM2200_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
  742. #define WM2200_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
  743. #define WM2200_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
  744. #define WM2200_IN3R_ENA 0x0010 /* IN3R_ENA */
  745. #define WM2200_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
  746. #define WM2200_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
  747. #define WM2200_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
  748. #define WM2200_IN2L_ENA 0x0008 /* IN2L_ENA */
  749. #define WM2200_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
  750. #define WM2200_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
  751. #define WM2200_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
  752. #define WM2200_IN2R_ENA 0x0004 /* IN2R_ENA */
  753. #define WM2200_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
  754. #define WM2200_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
  755. #define WM2200_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
  756. #define WM2200_IN1L_ENA 0x0002 /* IN1L_ENA */
  757. #define WM2200_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
  758. #define WM2200_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
  759. #define WM2200_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
  760. #define WM2200_IN1R_ENA 0x0001 /* IN1R_ENA */
  761. #define WM2200_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
  762. #define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
  763. #define WM2200_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
  764. /*
  765. * R770 (0x302) - IN1L Control
  766. */
  767. #define WM2200_IN1_OSR 0x2000 /* IN1_OSR */
  768. #define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */
  769. #define WM2200_IN1_OSR_SHIFT 13 /* IN1_OSR */
  770. #define WM2200_IN1_OSR_WIDTH 1 /* IN1_OSR */
  771. #define WM2200_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
  772. #define WM2200_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
  773. #define WM2200_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
  774. #define WM2200_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
  775. #define WM2200_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
  776. #define WM2200_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
  777. #define WM2200_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
  778. #define WM2200_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
  779. #define WM2200_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
  780. /*
  781. * R771 (0x303) - IN1R Control
  782. */
  783. #define WM2200_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
  784. #define WM2200_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
  785. #define WM2200_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
  786. /*
  787. * R772 (0x304) - IN2L Control
  788. */
  789. #define WM2200_IN2_OSR 0x2000 /* IN2_OSR */
  790. #define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */
  791. #define WM2200_IN2_OSR_SHIFT 13 /* IN2_OSR */
  792. #define WM2200_IN2_OSR_WIDTH 1 /* IN2_OSR */
  793. #define WM2200_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
  794. #define WM2200_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
  795. #define WM2200_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
  796. #define WM2200_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
  797. #define WM2200_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
  798. #define WM2200_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
  799. #define WM2200_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
  800. #define WM2200_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
  801. #define WM2200_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
  802. /*
  803. * R773 (0x305) - IN2R Control
  804. */
  805. #define WM2200_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
  806. #define WM2200_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
  807. #define WM2200_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
  808. /*
  809. * R774 (0x306) - IN3L Control
  810. */
  811. #define WM2200_IN3_OSR 0x2000 /* IN3_OSR */
  812. #define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */
  813. #define WM2200_IN3_OSR_SHIFT 13 /* IN3_OSR */
  814. #define WM2200_IN3_OSR_WIDTH 1 /* IN3_OSR */
  815. #define WM2200_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
  816. #define WM2200_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
  817. #define WM2200_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
  818. #define WM2200_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
  819. #define WM2200_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
  820. #define WM2200_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
  821. #define WM2200_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
  822. #define WM2200_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
  823. #define WM2200_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
  824. /*
  825. * R775 (0x307) - IN3R Control
  826. */
  827. #define WM2200_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
  828. #define WM2200_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
  829. #define WM2200_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
  830. /*
  831. * R778 (0x30A) - RXANC_SRC
  832. */
  833. #define WM2200_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */
  834. #define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */
  835. #define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */
  836. /*
  837. * R779 (0x30B) - Input Volume Ramp
  838. */
  839. #define WM2200_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
  840. #define WM2200_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
  841. #define WM2200_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
  842. #define WM2200_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
  843. #define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
  844. #define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
  845. /*
  846. * R780 (0x30C) - ADC Digital Volume 1L
  847. */
  848. #define WM2200_IN_VU 0x0200 /* IN_VU */
  849. #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
  850. #define WM2200_IN_VU_SHIFT 9 /* IN_VU */
  851. #define WM2200_IN_VU_WIDTH 1 /* IN_VU */
  852. #define WM2200_IN1L_MUTE 0x0100 /* IN1L_MUTE */
  853. #define WM2200_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
  854. #define WM2200_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
  855. #define WM2200_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
  856. #define WM2200_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
  857. #define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
  858. #define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
  859. /*
  860. * R781 (0x30D) - ADC Digital Volume 1R
  861. */
  862. #define WM2200_IN_VU 0x0200 /* IN_VU */
  863. #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
  864. #define WM2200_IN_VU_SHIFT 9 /* IN_VU */
  865. #define WM2200_IN_VU_WIDTH 1 /* IN_VU */
  866. #define WM2200_IN1R_MUTE 0x0100 /* IN1R_MUTE */
  867. #define WM2200_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
  868. #define WM2200_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
  869. #define WM2200_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
  870. #define WM2200_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
  871. #define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
  872. #define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
  873. /*
  874. * R782 (0x30E) - ADC Digital Volume 2L
  875. */
  876. #define WM2200_IN_VU 0x0200 /* IN_VU */
  877. #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
  878. #define WM2200_IN_VU_SHIFT 9 /* IN_VU */
  879. #define WM2200_IN_VU_WIDTH 1 /* IN_VU */
  880. #define WM2200_IN2L_MUTE 0x0100 /* IN2L_MUTE */
  881. #define WM2200_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
  882. #define WM2200_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
  883. #define WM2200_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
  884. #define WM2200_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
  885. #define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
  886. #define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
  887. /*
  888. * R783 (0x30F) - ADC Digital Volume 2R
  889. */
  890. #define WM2200_IN_VU 0x0200 /* IN_VU */
  891. #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
  892. #define WM2200_IN_VU_SHIFT 9 /* IN_VU */
  893. #define WM2200_IN_VU_WIDTH 1 /* IN_VU */
  894. #define WM2200_IN2R_MUTE 0x0100 /* IN2R_MUTE */
  895. #define WM2200_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
  896. #define WM2200_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
  897. #define WM2200_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
  898. #define WM2200_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
  899. #define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
  900. #define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
  901. /*
  902. * R784 (0x310) - ADC Digital Volume 3L
  903. */
  904. #define WM2200_IN_VU 0x0200 /* IN_VU */
  905. #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
  906. #define WM2200_IN_VU_SHIFT 9 /* IN_VU */
  907. #define WM2200_IN_VU_WIDTH 1 /* IN_VU */
  908. #define WM2200_IN3L_MUTE 0x0100 /* IN3L_MUTE */
  909. #define WM2200_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
  910. #define WM2200_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
  911. #define WM2200_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
  912. #define WM2200_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
  913. #define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
  914. #define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
  915. /*
  916. * R785 (0x311) - ADC Digital Volume 3R
  917. */
  918. #define WM2200_IN_VU 0x0200 /* IN_VU */
  919. #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
  920. #define WM2200_IN_VU_SHIFT 9 /* IN_VU */
  921. #define WM2200_IN_VU_WIDTH 1 /* IN_VU */
  922. #define WM2200_IN3R_MUTE 0x0100 /* IN3R_MUTE */
  923. #define WM2200_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
  924. #define WM2200_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
  925. #define WM2200_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
  926. #define WM2200_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
  927. #define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
  928. #define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
  929. /*
  930. * R1024 (0x400) - Output Enables
  931. */
  932. #define WM2200_OUT2L_ENA 0x0008 /* OUT2L_ENA */
  933. #define WM2200_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
  934. #define WM2200_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */
  935. #define WM2200_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */
  936. #define WM2200_OUT2R_ENA 0x0004 /* OUT2R_ENA */
  937. #define WM2200_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
  938. #define WM2200_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */
  939. #define WM2200_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */
  940. #define WM2200_OUT1L_ENA 0x0002 /* OUT1L_ENA */
  941. #define WM2200_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
  942. #define WM2200_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */
  943. #define WM2200_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */
  944. #define WM2200_OUT1R_ENA 0x0001 /* OUT1R_ENA */
  945. #define WM2200_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
  946. #define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
  947. #define WM2200_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */
  948. /*
  949. * R1025 (0x401) - DAC Volume Limit 1L
  950. */
  951. #define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */
  952. #define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
  953. #define WM2200_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
  954. #define WM2200_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
  955. #define WM2200_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */
  956. #define WM2200_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */
  957. #define WM2200_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */
  958. #define WM2200_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */
  959. #define WM2200_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
  960. #define WM2200_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
  961. #define WM2200_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
  962. /*
  963. * R1026 (0x402) - DAC Volume Limit 1R
  964. */
  965. #define WM2200_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */
  966. #define WM2200_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */
  967. #define WM2200_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */
  968. #define WM2200_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */
  969. #define WM2200_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
  970. #define WM2200_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
  971. #define WM2200_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
  972. /*
  973. * R1027 (0x403) - DAC Volume Limit 2L
  974. */
  975. #define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */
  976. #define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
  977. #define WM2200_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
  978. #define WM2200_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
  979. #define WM2200_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */
  980. #define WM2200_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */
  981. #define WM2200_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */
  982. #define WM2200_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */
  983. /*
  984. * R1028 (0x404) - DAC Volume Limit 2R
  985. */
  986. #define WM2200_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */
  987. #define WM2200_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */
  988. #define WM2200_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */
  989. #define WM2200_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */
  990. /*
  991. * R1033 (0x409) - DAC AEC Control 1
  992. */
  993. #define WM2200_AEC_LOOPBACK_ENA 0x0004 /* AEC_LOOPBACK_ENA */
  994. #define WM2200_AEC_LOOPBACK_ENA_MASK 0x0004 /* AEC_LOOPBACK_ENA */
  995. #define WM2200_AEC_LOOPBACK_ENA_SHIFT 2 /* AEC_LOOPBACK_ENA */
  996. #define WM2200_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
  997. #define WM2200_AEC_LOOPBACK_SRC_MASK 0x0003 /* AEC_LOOPBACK_SRC - [1:0] */
  998. #define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */
  999. #define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */
  1000. /*
  1001. * R1034 (0x40A) - Output Volume Ramp
  1002. */
  1003. #define WM2200_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
  1004. #define WM2200_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
  1005. #define WM2200_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
  1006. #define WM2200_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
  1007. #define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
  1008. #define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
  1009. /*
  1010. * R1035 (0x40B) - DAC Digital Volume 1L
  1011. */
  1012. #define WM2200_OUT_VU 0x0200 /* OUT_VU */
  1013. #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
  1014. #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
  1015. #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
  1016. #define WM2200_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
  1017. #define WM2200_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
  1018. #define WM2200_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
  1019. #define WM2200_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
  1020. #define WM2200_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
  1021. #define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
  1022. #define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
  1023. /*
  1024. * R1036 (0x40C) - DAC Digital Volume 1R
  1025. */
  1026. #define WM2200_OUT_VU 0x0200 /* OUT_VU */
  1027. #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
  1028. #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
  1029. #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
  1030. #define WM2200_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
  1031. #define WM2200_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
  1032. #define WM2200_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
  1033. #define WM2200_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
  1034. #define WM2200_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
  1035. #define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
  1036. #define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
  1037. /*
  1038. * R1037 (0x40D) - DAC Digital Volume 2L
  1039. */
  1040. #define WM2200_OUT_VU 0x0200 /* OUT_VU */
  1041. #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
  1042. #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
  1043. #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
  1044. #define WM2200_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
  1045. #define WM2200_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
  1046. #define WM2200_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
  1047. #define WM2200_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
  1048. #define WM2200_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
  1049. #define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
  1050. #define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
  1051. /*
  1052. * R1038 (0x40E) - DAC Digital Volume 2R
  1053. */
  1054. #define WM2200_OUT_VU 0x0200 /* OUT_VU */
  1055. #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
  1056. #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
  1057. #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
  1058. #define WM2200_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
  1059. #define WM2200_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
  1060. #define WM2200_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
  1061. #define WM2200_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
  1062. #define WM2200_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
  1063. #define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
  1064. #define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
  1065. /*
  1066. * R1047 (0x417) - PDM 1
  1067. */
  1068. #define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
  1069. #define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
  1070. #define WM2200_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
  1071. #define WM2200_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
  1072. #define WM2200_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
  1073. #define WM2200_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
  1074. #define WM2200_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
  1075. #define WM2200_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
  1076. #define WM2200_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
  1077. #define WM2200_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
  1078. #define WM2200_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
  1079. #define WM2200_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
  1080. #define WM2200_SPK1_MUTE_SEQL_MASK 0x00FF /* SPK1_MUTE_SEQL - [7:0] */
  1081. #define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */
  1082. #define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */
  1083. /*
  1084. * R1048 (0x418) - PDM 2
  1085. */
  1086. #define WM2200_SPK1_FMT 0x0001 /* SPK1_FMT */
  1087. #define WM2200_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
  1088. #define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
  1089. #define WM2200_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
  1090. /*
  1091. * R1280 (0x500) - Audio IF 1_1
  1092. */
  1093. #define WM2200_AIF1_BCLK_INV 0x0040 /* AIF1_BCLK_INV */
  1094. #define WM2200_AIF1_BCLK_INV_MASK 0x0040 /* AIF1_BCLK_INV */
  1095. #define WM2200_AIF1_BCLK_INV_SHIFT 6 /* AIF1_BCLK_INV */
  1096. #define WM2200_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
  1097. #define WM2200_AIF1_BCLK_FRC 0x0020 /* AIF1_BCLK_FRC */
  1098. #define WM2200_AIF1_BCLK_FRC_MASK 0x0020 /* AIF1_BCLK_FRC */
  1099. #define WM2200_AIF1_BCLK_FRC_SHIFT 5 /* AIF1_BCLK_FRC */
  1100. #define WM2200_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
  1101. #define WM2200_AIF1_BCLK_MSTR 0x0010 /* AIF1_BCLK_MSTR */
  1102. #define WM2200_AIF1_BCLK_MSTR_MASK 0x0010 /* AIF1_BCLK_MSTR */
  1103. #define WM2200_AIF1_BCLK_MSTR_SHIFT 4 /* AIF1_BCLK_MSTR */
  1104. #define WM2200_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
  1105. #define WM2200_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */
  1106. #define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */
  1107. #define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */
  1108. /*
  1109. * R1281 (0x501) - Audio IF 1_2
  1110. */
  1111. #define WM2200_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
  1112. #define WM2200_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
  1113. #define WM2200_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
  1114. #define WM2200_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
  1115. #define WM2200_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
  1116. #define WM2200_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
  1117. #define WM2200_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
  1118. #define WM2200_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
  1119. #define WM2200_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
  1120. #define WM2200_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
  1121. #define WM2200_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
  1122. #define WM2200_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
  1123. #define WM2200_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
  1124. #define WM2200_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
  1125. #define WM2200_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
  1126. #define WM2200_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
  1127. #define WM2200_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
  1128. #define WM2200_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
  1129. #define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
  1130. #define WM2200_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
  1131. /*
  1132. * R1282 (0x502) - Audio IF 1_3
  1133. */
  1134. #define WM2200_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
  1135. #define WM2200_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
  1136. #define WM2200_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
  1137. #define WM2200_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
  1138. #define WM2200_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
  1139. #define WM2200_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
  1140. #define WM2200_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
  1141. #define WM2200_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
  1142. #define WM2200_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
  1143. #define WM2200_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
  1144. #define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
  1145. #define WM2200_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
  1146. /*
  1147. * R1283 (0x503) - Audio IF 1_4
  1148. */
  1149. #define WM2200_AIF1_TRI 0x0040 /* AIF1_TRI */
  1150. #define WM2200_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
  1151. #define WM2200_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
  1152. #define WM2200_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
  1153. /*
  1154. * R1284 (0x504) - Audio IF 1_5
  1155. */
  1156. #define WM2200_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
  1157. #define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
  1158. #define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
  1159. /*
  1160. * R1285 (0x505) - Audio IF 1_6
  1161. */
  1162. #define WM2200_AIF1TX_BCPF_MASK 0x07FF /* AIF1TX_BCPF - [10:0] */
  1163. #define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */
  1164. #define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */
  1165. /*
  1166. * R1286 (0x506) - Audio IF 1_7
  1167. */
  1168. #define WM2200_AIF1RX_BCPF_MASK 0x07FF /* AIF1RX_BCPF - [10:0] */
  1169. #define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */
  1170. #define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */
  1171. /*
  1172. * R1287 (0x507) - Audio IF 1_8
  1173. */
  1174. #define WM2200_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
  1175. #define WM2200_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
  1176. #define WM2200_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
  1177. #define WM2200_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
  1178. #define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
  1179. #define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
  1180. /*
  1181. * R1288 (0x508) - Audio IF 1_9
  1182. */
  1183. #define WM2200_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
  1184. #define WM2200_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
  1185. #define WM2200_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
  1186. #define WM2200_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
  1187. #define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
  1188. #define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
  1189. /*
  1190. * R1289 (0x509) - Audio IF 1_10
  1191. */
  1192. #define WM2200_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
  1193. #define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
  1194. #define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
  1195. /*
  1196. * R1290 (0x50A) - Audio IF 1_11
  1197. */
  1198. #define WM2200_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
  1199. #define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
  1200. #define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
  1201. /*
  1202. * R1291 (0x50B) - Audio IF 1_12
  1203. */
  1204. #define WM2200_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
  1205. #define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
  1206. #define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
  1207. /*
  1208. * R1292 (0x50C) - Audio IF 1_13
  1209. */
  1210. #define WM2200_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
  1211. #define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
  1212. #define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
  1213. /*
  1214. * R1293 (0x50D) - Audio IF 1_14
  1215. */
  1216. #define WM2200_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
  1217. #define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
  1218. #define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
  1219. /*
  1220. * R1294 (0x50E) - Audio IF 1_15
  1221. */
  1222. #define WM2200_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
  1223. #define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
  1224. #define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
  1225. /*
  1226. * R1295 (0x50F) - Audio IF 1_16
  1227. */
  1228. #define WM2200_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
  1229. #define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
  1230. #define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
  1231. /*
  1232. * R1296 (0x510) - Audio IF 1_17
  1233. */
  1234. #define WM2200_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
  1235. #define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
  1236. #define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
  1237. /*
  1238. * R1297 (0x511) - Audio IF 1_18
  1239. */
  1240. #define WM2200_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
  1241. #define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
  1242. #define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
  1243. /*
  1244. * R1298 (0x512) - Audio IF 1_19
  1245. */
  1246. #define WM2200_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
  1247. #define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
  1248. #define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
  1249. /*
  1250. * R1299 (0x513) - Audio IF 1_20
  1251. */
  1252. #define WM2200_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
  1253. #define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
  1254. #define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
  1255. /*
  1256. * R1300 (0x514) - Audio IF 1_21
  1257. */
  1258. #define WM2200_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
  1259. #define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
  1260. #define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
  1261. /*
  1262. * R1301 (0x515) - Audio IF 1_22
  1263. */
  1264. #define WM2200_AIF1RX6_ENA 0x0800 /* AIF1RX6_ENA */
  1265. #define WM2200_AIF1RX6_ENA_MASK 0x0800 /* AIF1RX6_ENA */
  1266. #define WM2200_AIF1RX6_ENA_SHIFT 11 /* AIF1RX6_ENA */
  1267. #define WM2200_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
  1268. #define WM2200_AIF1RX5_ENA 0x0400 /* AIF1RX5_ENA */
  1269. #define WM2200_AIF1RX5_ENA_MASK 0x0400 /* AIF1RX5_ENA */
  1270. #define WM2200_AIF1RX5_ENA_SHIFT 10 /* AIF1RX5_ENA */
  1271. #define WM2200_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
  1272. #define WM2200_AIF1RX4_ENA 0x0200 /* AIF1RX4_ENA */
  1273. #define WM2200_AIF1RX4_ENA_MASK 0x0200 /* AIF1RX4_ENA */
  1274. #define WM2200_AIF1RX4_ENA_SHIFT 9 /* AIF1RX4_ENA */
  1275. #define WM2200_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
  1276. #define WM2200_AIF1RX3_ENA 0x0100 /* AIF1RX3_ENA */
  1277. #define WM2200_AIF1RX3_ENA_MASK 0x0100 /* AIF1RX3_ENA */
  1278. #define WM2200_AIF1RX3_ENA_SHIFT 8 /* AIF1RX3_ENA */
  1279. #define WM2200_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
  1280. #define WM2200_AIF1RX2_ENA 0x0080 /* AIF1RX2_ENA */
  1281. #define WM2200_AIF1RX2_ENA_MASK 0x0080 /* AIF1RX2_ENA */
  1282. #define WM2200_AIF1RX2_ENA_SHIFT 7 /* AIF1RX2_ENA */
  1283. #define WM2200_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
  1284. #define WM2200_AIF1RX1_ENA 0x0040 /* AIF1RX1_ENA */
  1285. #define WM2200_AIF1RX1_ENA_MASK 0x0040 /* AIF1RX1_ENA */
  1286. #define WM2200_AIF1RX1_ENA_SHIFT 6 /* AIF1RX1_ENA */
  1287. #define WM2200_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
  1288. #define WM2200_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
  1289. #define WM2200_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
  1290. #define WM2200_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
  1291. #define WM2200_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
  1292. #define WM2200_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
  1293. #define WM2200_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
  1294. #define WM2200_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
  1295. #define WM2200_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
  1296. #define WM2200_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
  1297. #define WM2200_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
  1298. #define WM2200_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
  1299. #define WM2200_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
  1300. #define WM2200_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
  1301. #define WM2200_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
  1302. #define WM2200_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
  1303. #define WM2200_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
  1304. #define WM2200_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
  1305. #define WM2200_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
  1306. #define WM2200_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
  1307. #define WM2200_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
  1308. #define WM2200_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
  1309. #define WM2200_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
  1310. #define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
  1311. #define WM2200_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
  1312. /*
  1313. * R1536 (0x600) - OUT1LMIX Input 1 Source
  1314. */
  1315. #define WM2200_OUT1LMIX_SRC1_MASK 0x007F /* OUT1LMIX_SRC1 - [6:0] */
  1316. #define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */
  1317. #define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */
  1318. /*
  1319. * R1537 (0x601) - OUT1LMIX Input 1 Volume
  1320. */
  1321. #define WM2200_OUT1LMIX_VOL1_MASK 0x00FE /* OUT1LMIX_VOL1 - [7:1] */
  1322. #define WM2200_OUT1LMIX_VOL1_SHIFT 1 /* OUT1LMIX_VOL1 - [7:1] */
  1323. #define WM2200_OUT1LMIX_VOL1_WIDTH 7 /* OUT1LMIX_VOL1 - [7:1] */
  1324. /*
  1325. * R1538 (0x602) - OUT1LMIX Input 2 Source
  1326. */
  1327. #define WM2200_OUT1LMIX_SRC2_MASK 0x007F /* OUT1LMIX_SRC2 - [6:0] */
  1328. #define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */
  1329. #define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */
  1330. /*
  1331. * R1539 (0x603) - OUT1LMIX Input 2 Volume
  1332. */
  1333. #define WM2200_OUT1LMIX_VOL2_MASK 0x00FE /* OUT1LMIX_VOL2 - [7:1] */
  1334. #define WM2200_OUT1LMIX_VOL2_SHIFT 1 /* OUT1LMIX_VOL2 - [7:1] */
  1335. #define WM2200_OUT1LMIX_VOL2_WIDTH 7 /* OUT1LMIX_VOL2 - [7:1] */
  1336. /*
  1337. * R1540 (0x604) - OUT1LMIX Input 3 Source
  1338. */
  1339. #define WM2200_OUT1LMIX_SRC3_MASK 0x007F /* OUT1LMIX_SRC3 - [6:0] */
  1340. #define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */
  1341. #define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */
  1342. /*
  1343. * R1541 (0x605) - OUT1LMIX Input 3 Volume
  1344. */
  1345. #define WM2200_OUT1LMIX_VOL3_MASK 0x00FE /* OUT1LMIX_VOL3 - [7:1] */
  1346. #define WM2200_OUT1LMIX_VOL3_SHIFT 1 /* OUT1LMIX_VOL3 - [7:1] */
  1347. #define WM2200_OUT1LMIX_VOL3_WIDTH 7 /* OUT1LMIX_VOL3 - [7:1] */
  1348. /*
  1349. * R1542 (0x606) - OUT1LMIX Input 4 Source
  1350. */
  1351. #define WM2200_OUT1LMIX_SRC4_MASK 0x007F /* OUT1LMIX_SRC4 - [6:0] */
  1352. #define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */
  1353. #define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */
  1354. /*
  1355. * R1543 (0x607) - OUT1LMIX Input 4 Volume
  1356. */
  1357. #define WM2200_OUT1LMIX_VOL4_MASK 0x00FE /* OUT1LMIX_VOL4 - [7:1] */
  1358. #define WM2200_OUT1LMIX_VOL4_SHIFT 1 /* OUT1LMIX_VOL4 - [7:1] */
  1359. #define WM2200_OUT1LMIX_VOL4_WIDTH 7 /* OUT1LMIX_VOL4 - [7:1] */
  1360. /*
  1361. * R1544 (0x608) - OUT1RMIX Input 1 Source
  1362. */
  1363. #define WM2200_OUT1RMIX_SRC1_MASK 0x007F /* OUT1RMIX_SRC1 - [6:0] */
  1364. #define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */
  1365. #define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */
  1366. /*
  1367. * R1545 (0x609) - OUT1RMIX Input 1 Volume
  1368. */
  1369. #define WM2200_OUT1RMIX_VOL1_MASK 0x00FE /* OUT1RMIX_VOL1 - [7:1] */
  1370. #define WM2200_OUT1RMIX_VOL1_SHIFT 1 /* OUT1RMIX_VOL1 - [7:1] */
  1371. #define WM2200_OUT1RMIX_VOL1_WIDTH 7 /* OUT1RMIX_VOL1 - [7:1] */
  1372. /*
  1373. * R1546 (0x60A) - OUT1RMIX Input 2 Source
  1374. */
  1375. #define WM2200_OUT1RMIX_SRC2_MASK 0x007F /* OUT1RMIX_SRC2 - [6:0] */
  1376. #define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */
  1377. #define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */
  1378. /*
  1379. * R1547 (0x60B) - OUT1RMIX Input 2 Volume
  1380. */
  1381. #define WM2200_OUT1RMIX_VOL2_MASK 0x00FE /* OUT1RMIX_VOL2 - [7:1] */
  1382. #define WM2200_OUT1RMIX_VOL2_SHIFT 1 /* OUT1RMIX_VOL2 - [7:1] */
  1383. #define WM2200_OUT1RMIX_VOL2_WIDTH 7 /* OUT1RMIX_VOL2 - [7:1] */
  1384. /*
  1385. * R1548 (0x60C) - OUT1RMIX Input 3 Source
  1386. */
  1387. #define WM2200_OUT1RMIX_SRC3_MASK 0x007F /* OUT1RMIX_SRC3 - [6:0] */
  1388. #define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */
  1389. #define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */
  1390. /*
  1391. * R1549 (0x60D) - OUT1RMIX Input 3 Volume
  1392. */
  1393. #define WM2200_OUT1RMIX_VOL3_MASK 0x00FE /* OUT1RMIX_VOL3 - [7:1] */
  1394. #define WM2200_OUT1RMIX_VOL3_SHIFT 1 /* OUT1RMIX_VOL3 - [7:1] */
  1395. #define WM2200_OUT1RMIX_VOL3_WIDTH 7 /* OUT1RMIX_VOL3 - [7:1] */
  1396. /*
  1397. * R1550 (0x60E) - OUT1RMIX Input 4 Source
  1398. */
  1399. #define WM2200_OUT1RMIX_SRC4_MASK 0x007F /* OUT1RMIX_SRC4 - [6:0] */
  1400. #define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */
  1401. #define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */
  1402. /*
  1403. * R1551 (0x60F) - OUT1RMIX Input 4 Volume
  1404. */
  1405. #define WM2200_OUT1RMIX_VOL4_MASK 0x00FE /* OUT1RMIX_VOL4 - [7:1] */
  1406. #define WM2200_OUT1RMIX_VOL4_SHIFT 1 /* OUT1RMIX_VOL4 - [7:1] */
  1407. #define WM2200_OUT1RMIX_VOL4_WIDTH 7 /* OUT1RMIX_VOL4 - [7:1] */
  1408. /*
  1409. * R1552 (0x610) - OUT2LMIX Input 1 Source
  1410. */
  1411. #define WM2200_OUT2LMIX_SRC1_MASK 0x007F /* OUT2LMIX_SRC1 - [6:0] */
  1412. #define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */
  1413. #define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */
  1414. /*
  1415. * R1553 (0x611) - OUT2LMIX Input 1 Volume
  1416. */
  1417. #define WM2200_OUT2LMIX_VOL1_MASK 0x00FE /* OUT2LMIX_VOL1 - [7:1] */
  1418. #define WM2200_OUT2LMIX_VOL1_SHIFT 1 /* OUT2LMIX_VOL1 - [7:1] */
  1419. #define WM2200_OUT2LMIX_VOL1_WIDTH 7 /* OUT2LMIX_VOL1 - [7:1] */
  1420. /*
  1421. * R1554 (0x612) - OUT2LMIX Input 2 Source
  1422. */
  1423. #define WM2200_OUT2LMIX_SRC2_MASK 0x007F /* OUT2LMIX_SRC2 - [6:0] */
  1424. #define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */
  1425. #define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */
  1426. /*
  1427. * R1555 (0x613) - OUT2LMIX Input 2 Volume
  1428. */
  1429. #define WM2200_OUT2LMIX_VOL2_MASK 0x00FE /* OUT2LMIX_VOL2 - [7:1] */
  1430. #define WM2200_OUT2LMIX_VOL2_SHIFT 1 /* OUT2LMIX_VOL2 - [7:1] */
  1431. #define WM2200_OUT2LMIX_VOL2_WIDTH 7 /* OUT2LMIX_VOL2 - [7:1] */
  1432. /*
  1433. * R1556 (0x614) - OUT2LMIX Input 3 Source
  1434. */
  1435. #define WM2200_OUT2LMIX_SRC3_MASK 0x007F /* OUT2LMIX_SRC3 - [6:0] */
  1436. #define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */
  1437. #define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */
  1438. /*
  1439. * R1557 (0x615) - OUT2LMIX Input 3 Volume
  1440. */
  1441. #define WM2200_OUT2LMIX_VOL3_MASK 0x00FE /* OUT2LMIX_VOL3 - [7:1] */
  1442. #define WM2200_OUT2LMIX_VOL3_SHIFT 1 /* OUT2LMIX_VOL3 - [7:1] */
  1443. #define WM2200_OUT2LMIX_VOL3_WIDTH 7 /* OUT2LMIX_VOL3 - [7:1] */
  1444. /*
  1445. * R1558 (0x616) - OUT2LMIX Input 4 Source
  1446. */
  1447. #define WM2200_OUT2LMIX_SRC4_MASK 0x007F /* OUT2LMIX_SRC4 - [6:0] */
  1448. #define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */
  1449. #define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */
  1450. /*
  1451. * R1559 (0x617) - OUT2LMIX Input 4 Volume
  1452. */
  1453. #define WM2200_OUT2LMIX_VOL4_MASK 0x00FE /* OUT2LMIX_VOL4 - [7:1] */
  1454. #define WM2200_OUT2LMIX_VOL4_SHIFT 1 /* OUT2LMIX_VOL4 - [7:1] */
  1455. #define WM2200_OUT2LMIX_VOL4_WIDTH 7 /* OUT2LMIX_VOL4 - [7:1] */
  1456. /*
  1457. * R1560 (0x618) - OUT2RMIX Input 1 Source
  1458. */
  1459. #define WM2200_OUT2RMIX_SRC1_MASK 0x007F /* OUT2RMIX_SRC1 - [6:0] */
  1460. #define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */
  1461. #define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */
  1462. /*
  1463. * R1561 (0x619) - OUT2RMIX Input 1 Volume
  1464. */
  1465. #define WM2200_OUT2RMIX_VOL1_MASK 0x00FE /* OUT2RMIX_VOL1 - [7:1] */
  1466. #define WM2200_OUT2RMIX_VOL1_SHIFT 1 /* OUT2RMIX_VOL1 - [7:1] */
  1467. #define WM2200_OUT2RMIX_VOL1_WIDTH 7 /* OUT2RMIX_VOL1 - [7:1] */
  1468. /*
  1469. * R1562 (0x61A) - OUT2RMIX Input 2 Source
  1470. */
  1471. #define WM2200_OUT2RMIX_SRC2_MASK 0x007F /* OUT2RMIX_SRC2 - [6:0] */
  1472. #define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */
  1473. #define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */
  1474. /*
  1475. * R1563 (0x61B) - OUT2RMIX Input 2 Volume
  1476. */
  1477. #define WM2200_OUT2RMIX_VOL2_MASK 0x00FE /* OUT2RMIX_VOL2 - [7:1] */
  1478. #define WM2200_OUT2RMIX_VOL2_SHIFT 1 /* OUT2RMIX_VOL2 - [7:1] */
  1479. #define WM2200_OUT2RMIX_VOL2_WIDTH 7 /* OUT2RMIX_VOL2 - [7:1] */
  1480. /*
  1481. * R1564 (0x61C) - OUT2RMIX Input 3 Source
  1482. */
  1483. #define WM2200_OUT2RMIX_SRC3_MASK 0x007F /* OUT2RMIX_SRC3 - [6:0] */
  1484. #define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */
  1485. #define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */
  1486. /*
  1487. * R1565 (0x61D) - OUT2RMIX Input 3 Volume
  1488. */
  1489. #define WM2200_OUT2RMIX_VOL3_MASK 0x00FE /* OUT2RMIX_VOL3 - [7:1] */
  1490. #define WM2200_OUT2RMIX_VOL3_SHIFT 1 /* OUT2RMIX_VOL3 - [7:1] */
  1491. #define WM2200_OUT2RMIX_VOL3_WIDTH 7 /* OUT2RMIX_VOL3 - [7:1] */
  1492. /*
  1493. * R1566 (0x61E) - OUT2RMIX Input 4 Source
  1494. */
  1495. #define WM2200_OUT2RMIX_SRC4_MASK 0x007F /* OUT2RMIX_SRC4 - [6:0] */
  1496. #define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */
  1497. #define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */
  1498. /*
  1499. * R1567 (0x61F) - OUT2RMIX Input 4 Volume
  1500. */
  1501. #define WM2200_OUT2RMIX_VOL4_MASK 0x00FE /* OUT2RMIX_VOL4 - [7:1] */
  1502. #define WM2200_OUT2RMIX_VOL4_SHIFT 1 /* OUT2RMIX_VOL4 - [7:1] */
  1503. #define WM2200_OUT2RMIX_VOL4_WIDTH 7 /* OUT2RMIX_VOL4 - [7:1] */
  1504. /*
  1505. * R1568 (0x620) - AIF1TX1MIX Input 1 Source
  1506. */
  1507. #define WM2200_AIF1TX1MIX_SRC1_MASK 0x007F /* AIF1TX1MIX_SRC1 - [6:0] */
  1508. #define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */
  1509. #define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */
  1510. /*
  1511. * R1569 (0x621) - AIF1TX1MIX Input 1 Volume
  1512. */
  1513. #define WM2200_AIF1TX1MIX_VOL1_MASK 0x00FE /* AIF1TX1MIX_VOL1 - [7:1] */
  1514. #define WM2200_AIF1TX1MIX_VOL1_SHIFT 1 /* AIF1TX1MIX_VOL1 - [7:1] */
  1515. #define WM2200_AIF1TX1MIX_VOL1_WIDTH 7 /* AIF1TX1MIX_VOL1 - [7:1] */
  1516. /*
  1517. * R1570 (0x622) - AIF1TX1MIX Input 2 Source
  1518. */
  1519. #define WM2200_AIF1TX1MIX_SRC2_MASK 0x007F /* AIF1TX1MIX_SRC2 - [6:0] */
  1520. #define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */
  1521. #define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */
  1522. /*
  1523. * R1571 (0x623) - AIF1TX1MIX Input 2 Volume
  1524. */
  1525. #define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */
  1526. #define WM2200_AIF1TX1MIX_VOL2_SHIFT 1 /* AIF1TX1MIX_VOL2 - [7:1] */
  1527. #define WM2200_AIF1TX1MIX_VOL2_WIDTH 7 /* AIF1TX1MIX_VOL2 - [7:1] */
  1528. /*
  1529. * R1572 (0x624) - AIF1TX1MIX Input 3 Source
  1530. */
  1531. #define WM2200_AIF1TX1MIX_SRC3_MASK 0x007F /* AIF1TX1MIX_SRC3 - [6:0] */
  1532. #define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */
  1533. #define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */
  1534. /*
  1535. * R1573 (0x625) - AIF1TX1MIX Input 3 Volume
  1536. */
  1537. #define WM2200_AIF1TX1MIX_VOL3_MASK 0x00FE /* AIF1TX1MIX_VOL3 - [7:1] */
  1538. #define WM2200_AIF1TX1MIX_VOL3_SHIFT 1 /* AIF1TX1MIX_VOL3 - [7:1] */
  1539. #define WM2200_AIF1TX1MIX_VOL3_WIDTH 7 /* AIF1TX1MIX_VOL3 - [7:1] */
  1540. /*
  1541. * R1574 (0x626) - AIF1TX1MIX Input 4 Source
  1542. */
  1543. #define WM2200_AIF1TX1MIX_SRC4_MASK 0x007F /* AIF1TX1MIX_SRC4 - [6:0] */
  1544. #define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */
  1545. #define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */
  1546. /*
  1547. * R1575 (0x627) - AIF1TX1MIX Input 4 Volume
  1548. */
  1549. #define WM2200_AIF1TX1MIX_VOL4_MASK 0x00FE /* AIF1TX1MIX_VOL4 - [7:1] */
  1550. #define WM2200_AIF1TX1MIX_VOL4_SHIFT 1 /* AIF1TX1MIX_VOL4 - [7:1] */
  1551. #define WM2200_AIF1TX1MIX_VOL4_WIDTH 7 /* AIF1TX1MIX_VOL4 - [7:1] */
  1552. /*
  1553. * R1576 (0x628) - AIF1TX2MIX Input 1 Source
  1554. */
  1555. #define WM2200_AIF1TX2MIX_SRC1_MASK 0x007F /* AIF1TX2MIX_SRC1 - [6:0] */
  1556. #define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */
  1557. #define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */
  1558. /*
  1559. * R1577 (0x629) - AIF1TX2MIX Input 1 Volume
  1560. */
  1561. #define WM2200_AIF1TX2MIX_VOL1_MASK 0x00FE /* AIF1TX2MIX_VOL1 - [7:1] */
  1562. #define WM2200_AIF1TX2MIX_VOL1_SHIFT 1 /* AIF1TX2MIX_VOL1 - [7:1] */
  1563. #define WM2200_AIF1TX2MIX_VOL1_WIDTH 7 /* AIF1TX2MIX_VOL1 - [7:1] */
  1564. /*
  1565. * R1578 (0x62A) - AIF1TX2MIX Input 2 Source
  1566. */
  1567. #define WM2200_AIF1TX2MIX_SRC2_MASK 0x007F /* AIF1TX2MIX_SRC2 - [6:0] */
  1568. #define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */
  1569. #define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */
  1570. /*
  1571. * R1579 (0x62B) - AIF1TX2MIX Input 2 Volume
  1572. */
  1573. #define WM2200_AIF1TX2MIX_VOL2_MASK 0x00FE /* AIF1TX2MIX_VOL2 - [7:1] */
  1574. #define WM2200_AIF1TX2MIX_VOL2_SHIFT 1 /* AIF1TX2MIX_VOL2 - [7:1] */
  1575. #define WM2200_AIF1TX2MIX_VOL2_WIDTH 7 /* AIF1TX2MIX_VOL2 - [7:1] */
  1576. /*
  1577. * R1580 (0x62C) - AIF1TX2MIX Input 3 Source
  1578. */
  1579. #define WM2200_AIF1TX2MIX_SRC3_MASK 0x007F /* AIF1TX2MIX_SRC3 - [6:0] */
  1580. #define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */
  1581. #define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */
  1582. /*
  1583. * R1581 (0x62D) - AIF1TX2MIX Input 3 Volume
  1584. */
  1585. #define WM2200_AIF1TX2MIX_VOL3_MASK 0x00FE /* AIF1TX2MIX_VOL3 - [7:1] */
  1586. #define WM2200_AIF1TX2MIX_VOL3_SHIFT 1 /* AIF1TX2MIX_VOL3 - [7:1] */
  1587. #define WM2200_AIF1TX2MIX_VOL3_WIDTH 7 /* AIF1TX2MIX_VOL3 - [7:1] */
  1588. /*
  1589. * R1582 (0x62E) - AIF1TX2MIX Input 4 Source
  1590. */
  1591. #define WM2200_AIF1TX2MIX_SRC4_MASK 0x007F /* AIF1TX2MIX_SRC4 - [6:0] */
  1592. #define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */
  1593. #define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */
  1594. /*
  1595. * R1583 (0x62F) - AIF1TX2MIX Input 4 Volume
  1596. */
  1597. #define WM2200_AIF1TX2MIX_VOL4_MASK 0x00FE /* AIF1TX2MIX_VOL4 - [7:1] */
  1598. #define WM2200_AIF1TX2MIX_VOL4_SHIFT 1 /* AIF1TX2MIX_VOL4 - [7:1] */
  1599. #define WM2200_AIF1TX2MIX_VOL4_WIDTH 7 /* AIF1TX2MIX_VOL4 - [7:1] */
  1600. /*
  1601. * R1584 (0x630) - AIF1TX3MIX Input 1 Source
  1602. */
  1603. #define WM2200_AIF1TX3MIX_SRC1_MASK 0x007F /* AIF1TX3MIX_SRC1 - [6:0] */
  1604. #define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */
  1605. #define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */
  1606. /*
  1607. * R1585 (0x631) - AIF1TX3MIX Input 1 Volume
  1608. */
  1609. #define WM2200_AIF1TX3MIX_VOL1_MASK 0x00FE /* AIF1TX3MIX_VOL1 - [7:1] */
  1610. #define WM2200_AIF1TX3MIX_VOL1_SHIFT 1 /* AIF1TX3MIX_VOL1 - [7:1] */
  1611. #define WM2200_AIF1TX3MIX_VOL1_WIDTH 7 /* AIF1TX3MIX_VOL1 - [7:1] */
  1612. /*
  1613. * R1586 (0x632) - AIF1TX3MIX Input 2 Source
  1614. */
  1615. #define WM2200_AIF1TX3MIX_SRC2_MASK 0x007F /* AIF1TX3MIX_SRC2 - [6:0] */
  1616. #define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */
  1617. #define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */
  1618. /*
  1619. * R1587 (0x633) - AIF1TX3MIX Input 2 Volume
  1620. */
  1621. #define WM2200_AIF1TX3MIX_VOL2_MASK 0x00FE /* AIF1TX3MIX_VOL2 - [7:1] */
  1622. #define WM2200_AIF1TX3MIX_VOL2_SHIFT 1 /* AIF1TX3MIX_VOL2 - [7:1] */
  1623. #define WM2200_AIF1TX3MIX_VOL2_WIDTH 7 /* AIF1TX3MIX_VOL2 - [7:1] */
  1624. /*
  1625. * R1588 (0x634) - AIF1TX3MIX Input 3 Source
  1626. */
  1627. #define WM2200_AIF1TX3MIX_SRC3_MASK 0x007F /* AIF1TX3MIX_SRC3 - [6:0] */
  1628. #define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */
  1629. #define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */
  1630. /*
  1631. * R1589 (0x635) - AIF1TX3MIX Input 3 Volume
  1632. */
  1633. #define WM2200_AIF1TX3MIX_VOL3_MASK 0x00FE /* AIF1TX3MIX_VOL3 - [7:1] */
  1634. #define WM2200_AIF1TX3MIX_VOL3_SHIFT 1 /* AIF1TX3MIX_VOL3 - [7:1] */
  1635. #define WM2200_AIF1TX3MIX_VOL3_WIDTH 7 /* AIF1TX3MIX_VOL3 - [7:1] */
  1636. /*
  1637. * R1590 (0x636) - AIF1TX3MIX Input 4 Source
  1638. */
  1639. #define WM2200_AIF1TX3MIX_SRC4_MASK 0x007F /* AIF1TX3MIX_SRC4 - [6:0] */
  1640. #define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */
  1641. #define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */
  1642. /*
  1643. * R1591 (0x637) - AIF1TX3MIX Input 4 Volume
  1644. */
  1645. #define WM2200_AIF1TX3MIX_VOL4_MASK 0x00FE /* AIF1TX3MIX_VOL4 - [7:1] */
  1646. #define WM2200_AIF1TX3MIX_VOL4_SHIFT 1 /* AIF1TX3MIX_VOL4 - [7:1] */
  1647. #define WM2200_AIF1TX3MIX_VOL4_WIDTH 7 /* AIF1TX3MIX_VOL4 - [7:1] */
  1648. /*
  1649. * R1592 (0x638) - AIF1TX4MIX Input 1 Source
  1650. */
  1651. #define WM2200_AIF1TX4MIX_SRC1_MASK 0x007F /* AIF1TX4MIX_SRC1 - [6:0] */
  1652. #define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */
  1653. #define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */
  1654. /*
  1655. * R1593 (0x639) - AIF1TX4MIX Input 1 Volume
  1656. */
  1657. #define WM2200_AIF1TX4MIX_VOL1_MASK 0x00FE /* AIF1TX4MIX_VOL1 - [7:1] */
  1658. #define WM2200_AIF1TX4MIX_VOL1_SHIFT 1 /* AIF1TX4MIX_VOL1 - [7:1] */
  1659. #define WM2200_AIF1TX4MIX_VOL1_WIDTH 7 /* AIF1TX4MIX_VOL1 - [7:1] */
  1660. /*
  1661. * R1594 (0x63A) - AIF1TX4MIX Input 2 Source
  1662. */
  1663. #define WM2200_AIF1TX4MIX_SRC2_MASK 0x007F /* AIF1TX4MIX_SRC2 - [6:0] */
  1664. #define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */
  1665. #define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */
  1666. /*
  1667. * R1595 (0x63B) - AIF1TX4MIX Input 2 Volume
  1668. */
  1669. #define WM2200_AIF1TX4MIX_VOL2_MASK 0x00FE /* AIF1TX4MIX_VOL2 - [7:1] */
  1670. #define WM2200_AIF1TX4MIX_VOL2_SHIFT 1 /* AIF1TX4MIX_VOL2 - [7:1] */
  1671. #define WM2200_AIF1TX4MIX_VOL2_WIDTH 7 /* AIF1TX4MIX_VOL2 - [7:1] */
  1672. /*
  1673. * R1596 (0x63C) - AIF1TX4MIX Input 3 Source
  1674. */
  1675. #define WM2200_AIF1TX4MIX_SRC3_MASK 0x007F /* AIF1TX4MIX_SRC3 - [6:0] */
  1676. #define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */
  1677. #define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */
  1678. /*
  1679. * R1597 (0x63D) - AIF1TX4MIX Input 3 Volume
  1680. */
  1681. #define WM2200_AIF1TX4MIX_VOL3_MASK 0x00FE /* AIF1TX4MIX_VOL3 - [7:1] */
  1682. #define WM2200_AIF1TX4MIX_VOL3_SHIFT 1 /* AIF1TX4MIX_VOL3 - [7:1] */
  1683. #define WM2200_AIF1TX4MIX_VOL3_WIDTH 7 /* AIF1TX4MIX_VOL3 - [7:1] */
  1684. /*
  1685. * R1598 (0x63E) - AIF1TX4MIX Input 4 Source
  1686. */
  1687. #define WM2200_AIF1TX4MIX_SRC4_MASK 0x007F /* AIF1TX4MIX_SRC4 - [6:0] */
  1688. #define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */
  1689. #define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */
  1690. /*
  1691. * R1599 (0x63F) - AIF1TX4MIX Input 4 Volume
  1692. */
  1693. #define WM2200_AIF1TX4MIX_VOL4_MASK 0x00FE /* AIF1TX4MIX_VOL4 - [7:1] */
  1694. #define WM2200_AIF1TX4MIX_VOL4_SHIFT 1 /* AIF1TX4MIX_VOL4 - [7:1] */
  1695. #define WM2200_AIF1TX4MIX_VOL4_WIDTH 7 /* AIF1TX4MIX_VOL4 - [7:1] */
  1696. /*
  1697. * R1600 (0x640) - AIF1TX5MIX Input 1 Source
  1698. */
  1699. #define WM2200_AIF1TX5MIX_SRC1_MASK 0x007F /* AIF1TX5MIX_SRC1 - [6:0] */
  1700. #define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */
  1701. #define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */
  1702. /*
  1703. * R1601 (0x641) - AIF1TX5MIX Input 1 Volume
  1704. */
  1705. #define WM2200_AIF1TX5MIX_VOL1_MASK 0x00FE /* AIF1TX5MIX_VOL1 - [7:1] */
  1706. #define WM2200_AIF1TX5MIX_VOL1_SHIFT 1 /* AIF1TX5MIX_VOL1 - [7:1] */
  1707. #define WM2200_AIF1TX5MIX_VOL1_WIDTH 7 /* AIF1TX5MIX_VOL1 - [7:1] */
  1708. /*
  1709. * R1602 (0x642) - AIF1TX5MIX Input 2 Source
  1710. */
  1711. #define WM2200_AIF1TX5MIX_SRC2_MASK 0x007F /* AIF1TX5MIX_SRC2 - [6:0] */
  1712. #define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */
  1713. #define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */
  1714. /*
  1715. * R1603 (0x643) - AIF1TX5MIX Input 2 Volume
  1716. */
  1717. #define WM2200_AIF1TX5MIX_VOL2_MASK 0x00FE /* AIF1TX5MIX_VOL2 - [7:1] */
  1718. #define WM2200_AIF1TX5MIX_VOL2_SHIFT 1 /* AIF1TX5MIX_VOL2 - [7:1] */
  1719. #define WM2200_AIF1TX5MIX_VOL2_WIDTH 7 /* AIF1TX5MIX_VOL2 - [7:1] */
  1720. /*
  1721. * R1604 (0x644) - AIF1TX5MIX Input 3 Source
  1722. */
  1723. #define WM2200_AIF1TX5MIX_SRC3_MASK 0x007F /* AIF1TX5MIX_SRC3 - [6:0] */
  1724. #define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */
  1725. #define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */
  1726. /*
  1727. * R1605 (0x645) - AIF1TX5MIX Input 3 Volume
  1728. */
  1729. #define WM2200_AIF1TX5MIX_VOL3_MASK 0x00FE /* AIF1TX5MIX_VOL3 - [7:1] */
  1730. #define WM2200_AIF1TX5MIX_VOL3_SHIFT 1 /* AIF1TX5MIX_VOL3 - [7:1] */
  1731. #define WM2200_AIF1TX5MIX_VOL3_WIDTH 7 /* AIF1TX5MIX_VOL3 - [7:1] */
  1732. /*
  1733. * R1606 (0x646) - AIF1TX5MIX Input 4 Source
  1734. */
  1735. #define WM2200_AIF1TX5MIX_SRC4_MASK 0x007F /* AIF1TX5MIX_SRC4 - [6:0] */
  1736. #define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */
  1737. #define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */
  1738. /*
  1739. * R1607 (0x647) - AIF1TX5MIX Input 4 Volume
  1740. */
  1741. #define WM2200_AIF1TX5MIX_VOL4_MASK 0x00FE /* AIF1TX5MIX_VOL4 - [7:1] */
  1742. #define WM2200_AIF1TX5MIX_VOL4_SHIFT 1 /* AIF1TX5MIX_VOL4 - [7:1] */
  1743. #define WM2200_AIF1TX5MIX_VOL4_WIDTH 7 /* AIF1TX5MIX_VOL4 - [7:1] */
  1744. /*
  1745. * R1608 (0x648) - AIF1TX6MIX Input 1 Source
  1746. */
  1747. #define WM2200_AIF1TX6MIX_SRC1_MASK 0x007F /* AIF1TX6MIX_SRC1 - [6:0] */
  1748. #define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */
  1749. #define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */
  1750. /*
  1751. * R1609 (0x649) - AIF1TX6MIX Input 1 Volume
  1752. */
  1753. #define WM2200_AIF1TX6MIX_VOL1_MASK 0x00FE /* AIF1TX6MIX_VOL1 - [7:1] */
  1754. #define WM2200_AIF1TX6MIX_VOL1_SHIFT 1 /* AIF1TX6MIX_VOL1 - [7:1] */
  1755. #define WM2200_AIF1TX6MIX_VOL1_WIDTH 7 /* AIF1TX6MIX_VOL1 - [7:1] */
  1756. /*
  1757. * R1610 (0x64A) - AIF1TX6MIX Input 2 Source
  1758. */
  1759. #define WM2200_AIF1TX6MIX_SRC2_MASK 0x007F /* AIF1TX6MIX_SRC2 - [6:0] */
  1760. #define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */
  1761. #define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */
  1762. /*
  1763. * R1611 (0x64B) - AIF1TX6MIX Input 2 Volume
  1764. */
  1765. #define WM2200_AIF1TX6MIX_VOL2_MASK 0x00FE /* AIF1TX6MIX_VOL2 - [7:1] */
  1766. #define WM2200_AIF1TX6MIX_VOL2_SHIFT 1 /* AIF1TX6MIX_VOL2 - [7:1] */
  1767. #define WM2200_AIF1TX6MIX_VOL2_WIDTH 7 /* AIF1TX6MIX_VOL2 - [7:1] */
  1768. /*
  1769. * R1612 (0x64C) - AIF1TX6MIX Input 3 Source
  1770. */
  1771. #define WM2200_AIF1TX6MIX_SRC3_MASK 0x007F /* AIF1TX6MIX_SRC3 - [6:0] */
  1772. #define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */
  1773. #define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */
  1774. /*
  1775. * R1613 (0x64D) - AIF1TX6MIX Input 3 Volume
  1776. */
  1777. #define WM2200_AIF1TX6MIX_VOL3_MASK 0x00FE /* AIF1TX6MIX_VOL3 - [7:1] */
  1778. #define WM2200_AIF1TX6MIX_VOL3_SHIFT 1 /* AIF1TX6MIX_VOL3 - [7:1] */
  1779. #define WM2200_AIF1TX6MIX_VOL3_WIDTH 7 /* AIF1TX6MIX_VOL3 - [7:1] */
  1780. /*
  1781. * R1614 (0x64E) - AIF1TX6MIX Input 4 Source
  1782. */
  1783. #define WM2200_AIF1TX6MIX_SRC4_MASK 0x007F /* AIF1TX6MIX_SRC4 - [6:0] */
  1784. #define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */
  1785. #define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */
  1786. /*
  1787. * R1615 (0x64F) - AIF1TX6MIX Input 4 Volume
  1788. */
  1789. #define WM2200_AIF1TX6MIX_VOL4_MASK 0x00FE /* AIF1TX6MIX_VOL4 - [7:1] */
  1790. #define WM2200_AIF1TX6MIX_VOL4_SHIFT 1 /* AIF1TX6MIX_VOL4 - [7:1] */
  1791. #define WM2200_AIF1TX6MIX_VOL4_WIDTH 7 /* AIF1TX6MIX_VOL4 - [7:1] */
  1792. /*
  1793. * R1616 (0x650) - EQLMIX Input 1 Source
  1794. */
  1795. #define WM2200_EQLMIX_SRC1_MASK 0x007F /* EQLMIX_SRC1 - [6:0] */
  1796. #define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */
  1797. #define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */
  1798. /*
  1799. * R1617 (0x651) - EQLMIX Input 1 Volume
  1800. */
  1801. #define WM2200_EQLMIX_VOL1_MASK 0x00FE /* EQLMIX_VOL1 - [7:1] */
  1802. #define WM2200_EQLMIX_VOL1_SHIFT 1 /* EQLMIX_VOL1 - [7:1] */
  1803. #define WM2200_EQLMIX_VOL1_WIDTH 7 /* EQLMIX_VOL1 - [7:1] */
  1804. /*
  1805. * R1618 (0x652) - EQLMIX Input 2 Source
  1806. */
  1807. #define WM2200_EQLMIX_SRC2_MASK 0x007F /* EQLMIX_SRC2 - [6:0] */
  1808. #define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */
  1809. #define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */
  1810. /*
  1811. * R1619 (0x653) - EQLMIX Input 2 Volume
  1812. */
  1813. #define WM2200_EQLMIX_VOL2_MASK 0x00FE /* EQLMIX_VOL2 - [7:1] */
  1814. #define WM2200_EQLMIX_VOL2_SHIFT 1 /* EQLMIX_VOL2 - [7:1] */
  1815. #define WM2200_EQLMIX_VOL2_WIDTH 7 /* EQLMIX_VOL2 - [7:1] */
  1816. /*
  1817. * R1620 (0x654) - EQLMIX Input 3 Source
  1818. */
  1819. #define WM2200_EQLMIX_SRC3_MASK 0x007F /* EQLMIX_SRC3 - [6:0] */
  1820. #define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */
  1821. #define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */
  1822. /*
  1823. * R1621 (0x655) - EQLMIX Input 3 Volume
  1824. */
  1825. #define WM2200_EQLMIX_VOL3_MASK 0x00FE /* EQLMIX_VOL3 - [7:1] */
  1826. #define WM2200_EQLMIX_VOL3_SHIFT 1 /* EQLMIX_VOL3 - [7:1] */
  1827. #define WM2200_EQLMIX_VOL3_WIDTH 7 /* EQLMIX_VOL3 - [7:1] */
  1828. /*
  1829. * R1622 (0x656) - EQLMIX Input 4 Source
  1830. */
  1831. #define WM2200_EQLMIX_SRC4_MASK 0x007F /* EQLMIX_SRC4 - [6:0] */
  1832. #define WM2200_EQLMIX_SRC4_SHIFT 0 /* EQLMIX_SRC4 - [6:0] */
  1833. #define WM2200_EQLMIX_SRC4_WIDTH 7 /* EQLMIX_SRC4 - [6:0] */
  1834. /*
  1835. * R1623 (0x657) - EQLMIX Input 4 Volume
  1836. */
  1837. #define WM2200_EQLMIX_VOL4_MASK 0x00FE /* EQLMIX_VOL4 - [7:1] */
  1838. #define WM2200_EQLMIX_VOL4_SHIFT 1 /* EQLMIX_VOL4 - [7:1] */
  1839. #define WM2200_EQLMIX_VOL4_WIDTH 7 /* EQLMIX_VOL4 - [7:1] */
  1840. /*
  1841. * R1624 (0x658) - EQRMIX Input 1 Source
  1842. */
  1843. #define WM2200_EQRMIX_SRC1_MASK 0x007F /* EQRMIX_SRC1 - [6:0] */
  1844. #define WM2200_EQRMIX_SRC1_SHIFT 0 /* EQRMIX_SRC1 - [6:0] */
  1845. #define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */
  1846. /*
  1847. * R1625 (0x659) - EQRMIX Input 1 Volume
  1848. */
  1849. #define WM2200_EQRMIX_VOL1_MASK 0x00FE /* EQRMIX_VOL1 - [7:1] */
  1850. #define WM2200_EQRMIX_VOL1_SHIFT 1 /* EQRMIX_VOL1 - [7:1] */
  1851. #define WM2200_EQRMIX_VOL1_WIDTH 7 /* EQRMIX_VOL1 - [7:1] */
  1852. /*
  1853. * R1626 (0x65A) - EQRMIX Input 2 Source
  1854. */
  1855. #define WM2200_EQRMIX_SRC2_MASK 0x007F /* EQRMIX_SRC2 - [6:0] */
  1856. #define WM2200_EQRMIX_SRC2_SHIFT 0 /* EQRMIX_SRC2 - [6:0] */
  1857. #define WM2200_EQRMIX_SRC2_WIDTH 7 /* EQRMIX_SRC2 - [6:0] */
  1858. /*
  1859. * R1627 (0x65B) - EQRMIX Input 2 Volume
  1860. */
  1861. #define WM2200_EQRMIX_VOL2_MASK 0x00FE /* EQRMIX_VOL2 - [7:1] */
  1862. #define WM2200_EQRMIX_VOL2_SHIFT 1 /* EQRMIX_VOL2 - [7:1] */
  1863. #define WM2200_EQRMIX_VOL2_WIDTH 7 /* EQRMIX_VOL2 - [7:1] */
  1864. /*
  1865. * R1628 (0x65C) - EQRMIX Input 3 Source
  1866. */
  1867. #define WM2200_EQRMIX_SRC3_MASK 0x007F /* EQRMIX_SRC3 - [6:0] */
  1868. #define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */
  1869. #define WM2200_EQRMIX_SRC3_WIDTH 7 /* EQRMIX_SRC3 - [6:0] */
  1870. /*
  1871. * R1629 (0x65D) - EQRMIX Input 3 Volume
  1872. */
  1873. #define WM2200_EQRMIX_VOL3_MASK 0x00FE /* EQRMIX_VOL3 - [7:1] */
  1874. #define WM2200_EQRMIX_VOL3_SHIFT 1 /* EQRMIX_VOL3 - [7:1] */
  1875. #define WM2200_EQRMIX_VOL3_WIDTH 7 /* EQRMIX_VOL3 - [7:1] */
  1876. /*
  1877. * R1630 (0x65E) - EQRMIX Input 4 Source
  1878. */
  1879. #define WM2200_EQRMIX_SRC4_MASK 0x007F /* EQRMIX_SRC4 - [6:0] */
  1880. #define WM2200_EQRMIX_SRC4_SHIFT 0 /* EQRMIX_SRC4 - [6:0] */
  1881. #define WM2200_EQRMIX_SRC4_WIDTH 7 /* EQRMIX_SRC4 - [6:0] */
  1882. /*
  1883. * R1631 (0x65F) - EQRMIX Input 4 Volume
  1884. */
  1885. #define WM2200_EQRMIX_VOL4_MASK 0x00FE /* EQRMIX_VOL4 - [7:1] */
  1886. #define WM2200_EQRMIX_VOL4_SHIFT 1 /* EQRMIX_VOL4 - [7:1] */
  1887. #define WM2200_EQRMIX_VOL4_WIDTH 7 /* EQRMIX_VOL4 - [7:1] */
  1888. /*
  1889. * R1632 (0x660) - LHPF1MIX Input 1 Source
  1890. */
  1891. #define WM2200_LHPF1MIX_SRC1_MASK 0x007F /* LHPF1MIX_SRC1 - [6:0] */
  1892. #define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */
  1893. #define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */
  1894. /*
  1895. * R1633 (0x661) - LHPF1MIX Input 1 Volume
  1896. */
  1897. #define WM2200_LHPF1MIX_VOL1_MASK 0x00FE /* LHPF1MIX_VOL1 - [7:1] */
  1898. #define WM2200_LHPF1MIX_VOL1_SHIFT 1 /* LHPF1MIX_VOL1 - [7:1] */
  1899. #define WM2200_LHPF1MIX_VOL1_WIDTH 7 /* LHPF1MIX_VOL1 - [7:1] */
  1900. /*
  1901. * R1634 (0x662) - LHPF1MIX Input 2 Source
  1902. */
  1903. #define WM2200_LHPF1MIX_SRC2_MASK 0x007F /* LHPF1MIX_SRC2 - [6:0] */
  1904. #define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */
  1905. #define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */
  1906. /*
  1907. * R1635 (0x663) - LHPF1MIX Input 2 Volume
  1908. */
  1909. #define WM2200_LHPF1MIX_VOL2_MASK 0x00FE /* LHPF1MIX_VOL2 - [7:1] */
  1910. #define WM2200_LHPF1MIX_VOL2_SHIFT 1 /* LHPF1MIX_VOL2 - [7:1] */
  1911. #define WM2200_LHPF1MIX_VOL2_WIDTH 7 /* LHPF1MIX_VOL2 - [7:1] */
  1912. /*
  1913. * R1636 (0x664) - LHPF1MIX Input 3 Source
  1914. */
  1915. #define WM2200_LHPF1MIX_SRC3_MASK 0x007F /* LHPF1MIX_SRC3 - [6:0] */
  1916. #define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */
  1917. #define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */
  1918. /*
  1919. * R1637 (0x665) - LHPF1MIX Input 3 Volume
  1920. */
  1921. #define WM2200_LHPF1MIX_VOL3_MASK 0x00FE /* LHPF1MIX_VOL3 - [7:1] */
  1922. #define WM2200_LHPF1MIX_VOL3_SHIFT 1 /* LHPF1MIX_VOL3 - [7:1] */
  1923. #define WM2200_LHPF1MIX_VOL3_WIDTH 7 /* LHPF1MIX_VOL3 - [7:1] */
  1924. /*
  1925. * R1638 (0x666) - LHPF1MIX Input 4 Source
  1926. */
  1927. #define WM2200_LHPF1MIX_SRC4_MASK 0x007F /* LHPF1MIX_SRC4 - [6:0] */
  1928. #define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */
  1929. #define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */
  1930. /*
  1931. * R1639 (0x667) - LHPF1MIX Input 4 Volume
  1932. */
  1933. #define WM2200_LHPF1MIX_VOL4_MASK 0x00FE /* LHPF1MIX_VOL4 - [7:1] */
  1934. #define WM2200_LHPF1MIX_VOL4_SHIFT 1 /* LHPF1MIX_VOL4 - [7:1] */
  1935. #define WM2200_LHPF1MIX_VOL4_WIDTH 7 /* LHPF1MIX_VOL4 - [7:1] */
  1936. /*
  1937. * R1640 (0x668) - LHPF2MIX Input 1 Source
  1938. */
  1939. #define WM2200_LHPF2MIX_SRC1_MASK 0x007F /* LHPF2MIX_SRC1 - [6:0] */
  1940. #define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */
  1941. #define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */
  1942. /*
  1943. * R1641 (0x669) - LHPF2MIX Input 1 Volume
  1944. */
  1945. #define WM2200_LHPF2MIX_VOL1_MASK 0x00FE /* LHPF2MIX_VOL1 - [7:1] */
  1946. #define WM2200_LHPF2MIX_VOL1_SHIFT 1 /* LHPF2MIX_VOL1 - [7:1] */
  1947. #define WM2200_LHPF2MIX_VOL1_WIDTH 7 /* LHPF2MIX_VOL1 - [7:1] */
  1948. /*
  1949. * R1642 (0x66A) - LHPF2MIX Input 2 Source
  1950. */
  1951. #define WM2200_LHPF2MIX_SRC2_MASK 0x007F /* LHPF2MIX_SRC2 - [6:0] */
  1952. #define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */
  1953. #define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */
  1954. /*
  1955. * R1643 (0x66B) - LHPF2MIX Input 2 Volume
  1956. */
  1957. #define WM2200_LHPF2MIX_VOL2_MASK 0x00FE /* LHPF2MIX_VOL2 - [7:1] */
  1958. #define WM2200_LHPF2MIX_VOL2_SHIFT 1 /* LHPF2MIX_VOL2 - [7:1] */
  1959. #define WM2200_LHPF2MIX_VOL2_WIDTH 7 /* LHPF2MIX_VOL2 - [7:1] */
  1960. /*
  1961. * R1644 (0x66C) - LHPF2MIX Input 3 Source
  1962. */
  1963. #define WM2200_LHPF2MIX_SRC3_MASK 0x007F /* LHPF2MIX_SRC3 - [6:0] */
  1964. #define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */
  1965. #define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */
  1966. /*
  1967. * R1645 (0x66D) - LHPF2MIX Input 3 Volume
  1968. */
  1969. #define WM2200_LHPF2MIX_VOL3_MASK 0x00FE /* LHPF2MIX_VOL3 - [7:1] */
  1970. #define WM2200_LHPF2MIX_VOL3_SHIFT 1 /* LHPF2MIX_VOL3 - [7:1] */
  1971. #define WM2200_LHPF2MIX_VOL3_WIDTH 7 /* LHPF2MIX_VOL3 - [7:1] */
  1972. /*
  1973. * R1646 (0x66E) - LHPF2MIX Input 4 Source
  1974. */
  1975. #define WM2200_LHPF2MIX_SRC4_MASK 0x007F /* LHPF2MIX_SRC4 - [6:0] */
  1976. #define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */
  1977. #define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */
  1978. /*
  1979. * R1647 (0x66F) - LHPF2MIX Input 4 Volume
  1980. */
  1981. #define WM2200_LHPF2MIX_VOL4_MASK 0x00FE /* LHPF2MIX_VOL4 - [7:1] */
  1982. #define WM2200_LHPF2MIX_VOL4_SHIFT 1 /* LHPF2MIX_VOL4 - [7:1] */
  1983. #define WM2200_LHPF2MIX_VOL4_WIDTH 7 /* LHPF2MIX_VOL4 - [7:1] */
  1984. /*
  1985. * R1648 (0x670) - DSP1LMIX Input 1 Source
  1986. */
  1987. #define WM2200_DSP1LMIX_SRC1_MASK 0x007F /* DSP1LMIX_SRC1 - [6:0] */
  1988. #define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */
  1989. #define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */
  1990. /*
  1991. * R1649 (0x671) - DSP1LMIX Input 1 Volume
  1992. */
  1993. #define WM2200_DSP1LMIX_VOL1_MASK 0x00FE /* DSP1LMIX_VOL1 - [7:1] */
  1994. #define WM2200_DSP1LMIX_VOL1_SHIFT 1 /* DSP1LMIX_VOL1 - [7:1] */
  1995. #define WM2200_DSP1LMIX_VOL1_WIDTH 7 /* DSP1LMIX_VOL1 - [7:1] */
  1996. /*
  1997. * R1650 (0x672) - DSP1LMIX Input 2 Source
  1998. */
  1999. #define WM2200_DSP1LMIX_SRC2_MASK 0x007F /* DSP1LMIX_SRC2 - [6:0] */
  2000. #define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */
  2001. #define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */
  2002. /*
  2003. * R1651 (0x673) - DSP1LMIX Input 2 Volume
  2004. */
  2005. #define WM2200_DSP1LMIX_VOL2_MASK 0x00FE /* DSP1LMIX_VOL2 - [7:1] */
  2006. #define WM2200_DSP1LMIX_VOL2_SHIFT 1 /* DSP1LMIX_VOL2 - [7:1] */
  2007. #define WM2200_DSP1LMIX_VOL2_WIDTH 7 /* DSP1LMIX_VOL2 - [7:1] */
  2008. /*
  2009. * R1652 (0x674) - DSP1LMIX Input 3 Source
  2010. */
  2011. #define WM2200_DSP1LMIX_SRC3_MASK 0x007F /* DSP1LMIX_SRC3 - [6:0] */
  2012. #define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */
  2013. #define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */
  2014. /*
  2015. * R1653 (0x675) - DSP1LMIX Input 3 Volume
  2016. */
  2017. #define WM2200_DSP1LMIX_VOL3_MASK 0x00FE /* DSP1LMIX_VOL3 - [7:1] */
  2018. #define WM2200_DSP1LMIX_VOL3_SHIFT 1 /* DSP1LMIX_VOL3 - [7:1] */
  2019. #define WM2200_DSP1LMIX_VOL3_WIDTH 7 /* DSP1LMIX_VOL3 - [7:1] */
  2020. /*
  2021. * R1654 (0x676) - DSP1LMIX Input 4 Source
  2022. */
  2023. #define WM2200_DSP1LMIX_SRC4_MASK 0x007F /* DSP1LMIX_SRC4 - [6:0] */
  2024. #define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */
  2025. #define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */
  2026. /*
  2027. * R1655 (0x677) - DSP1LMIX Input 4 Volume
  2028. */
  2029. #define WM2200_DSP1LMIX_VOL4_MASK 0x00FE /* DSP1LMIX_VOL4 - [7:1] */
  2030. #define WM2200_DSP1LMIX_VOL4_SHIFT 1 /* DSP1LMIX_VOL4 - [7:1] */
  2031. #define WM2200_DSP1LMIX_VOL4_WIDTH 7 /* DSP1LMIX_VOL4 - [7:1] */
  2032. /*
  2033. * R1656 (0x678) - DSP1RMIX Input 1 Source
  2034. */
  2035. #define WM2200_DSP1RMIX_SRC1_MASK 0x007F /* DSP1RMIX_SRC1 - [6:0] */
  2036. #define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */
  2037. #define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */
  2038. /*
  2039. * R1657 (0x679) - DSP1RMIX Input 1 Volume
  2040. */
  2041. #define WM2200_DSP1RMIX_VOL1_MASK 0x00FE /* DSP1RMIX_VOL1 - [7:1] */
  2042. #define WM2200_DSP1RMIX_VOL1_SHIFT 1 /* DSP1RMIX_VOL1 - [7:1] */
  2043. #define WM2200_DSP1RMIX_VOL1_WIDTH 7 /* DSP1RMIX_VOL1 - [7:1] */
  2044. /*
  2045. * R1658 (0x67A) - DSP1RMIX Input 2 Source
  2046. */
  2047. #define WM2200_DSP1RMIX_SRC2_MASK 0x007F /* DSP1RMIX_SRC2 - [6:0] */
  2048. #define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */
  2049. #define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */
  2050. /*
  2051. * R1659 (0x67B) - DSP1RMIX Input 2 Volume
  2052. */
  2053. #define WM2200_DSP1RMIX_VOL2_MASK 0x00FE /* DSP1RMIX_VOL2 - [7:1] */
  2054. #define WM2200_DSP1RMIX_VOL2_SHIFT 1 /* DSP1RMIX_VOL2 - [7:1] */
  2055. #define WM2200_DSP1RMIX_VOL2_WIDTH 7 /* DSP1RMIX_VOL2 - [7:1] */
  2056. /*
  2057. * R1660 (0x67C) - DSP1RMIX Input 3 Source
  2058. */
  2059. #define WM2200_DSP1RMIX_SRC3_MASK 0x007F /* DSP1RMIX_SRC3 - [6:0] */
  2060. #define WM2200_DSP1RMIX_SRC3_SHIFT 0 /* DSP1RMIX_SRC3 - [6:0] */
  2061. #define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */
  2062. /*
  2063. * R1661 (0x67D) - DSP1RMIX Input 3 Volume
  2064. */
  2065. #define WM2200_DSP1RMIX_VOL3_MASK 0x00FE /* DSP1RMIX_VOL3 - [7:1] */
  2066. #define WM2200_DSP1RMIX_VOL3_SHIFT 1 /* DSP1RMIX_VOL3 - [7:1] */
  2067. #define WM2200_DSP1RMIX_VOL3_WIDTH 7 /* DSP1RMIX_VOL3 - [7:1] */
  2068. /*
  2069. * R1662 (0x67E) - DSP1RMIX Input 4 Source
  2070. */
  2071. #define WM2200_DSP1RMIX_SRC4_MASK 0x007F /* DSP1RMIX_SRC4 - [6:0] */
  2072. #define WM2200_DSP1RMIX_SRC4_SHIFT 0 /* DSP1RMIX_SRC4 - [6:0] */
  2073. #define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */
  2074. /*
  2075. * R1663 (0x67F) - DSP1RMIX Input 4 Volume
  2076. */
  2077. #define WM2200_DSP1RMIX_VOL4_MASK 0x00FE /* DSP1RMIX_VOL4 - [7:1] */
  2078. #define WM2200_DSP1RMIX_VOL4_SHIFT 1 /* DSP1RMIX_VOL4 - [7:1] */
  2079. #define WM2200_DSP1RMIX_VOL4_WIDTH 7 /* DSP1RMIX_VOL4 - [7:1] */
  2080. /*
  2081. * R1664 (0x680) - DSP1AUX1MIX Input 1 Source
  2082. */
  2083. #define WM2200_DSP1AUX1MIX_SRC1_MASK 0x007F /* DSP1AUX1MIX_SRC1 - [6:0] */
  2084. #define WM2200_DSP1AUX1MIX_SRC1_SHIFT 0 /* DSP1AUX1MIX_SRC1 - [6:0] */
  2085. #define WM2200_DSP1AUX1MIX_SRC1_WIDTH 7 /* DSP1AUX1MIX_SRC1 - [6:0] */
  2086. /*
  2087. * R1665 (0x681) - DSP1AUX2MIX Input 1 Source
  2088. */
  2089. #define WM2200_DSP1AUX2MIX_SRC1_MASK 0x007F /* DSP1AUX2MIX_SRC1 - [6:0] */
  2090. #define WM2200_DSP1AUX2MIX_SRC1_SHIFT 0 /* DSP1AUX2MIX_SRC1 - [6:0] */
  2091. #define WM2200_DSP1AUX2MIX_SRC1_WIDTH 7 /* DSP1AUX2MIX_SRC1 - [6:0] */
  2092. /*
  2093. * R1666 (0x682) - DSP1AUX3MIX Input 1 Source
  2094. */
  2095. #define WM2200_DSP1AUX3MIX_SRC1_MASK 0x007F /* DSP1AUX3MIX_SRC1 - [6:0] */
  2096. #define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */
  2097. #define WM2200_DSP1AUX3MIX_SRC1_WIDTH 7 /* DSP1AUX3MIX_SRC1 - [6:0] */
  2098. /*
  2099. * R1667 (0x683) - DSP1AUX4MIX Input 1 Source
  2100. */
  2101. #define WM2200_DSP1AUX4MIX_SRC1_MASK 0x007F /* DSP1AUX4MIX_SRC1 - [6:0] */
  2102. #define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */
  2103. #define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */
  2104. /*
  2105. * R1668 (0x684) - DSP1AUX5MIX Input 1 Source
  2106. */
  2107. #define WM2200_DSP1AUX5MIX_SRC1_MASK 0x007F /* DSP1AUX5MIX_SRC1 - [6:0] */
  2108. #define WM2200_DSP1AUX5MIX_SRC1_SHIFT 0 /* DSP1AUX5MIX_SRC1 - [6:0] */
  2109. #define WM2200_DSP1AUX5MIX_SRC1_WIDTH 7 /* DSP1AUX5MIX_SRC1 - [6:0] */
  2110. /*
  2111. * R1669 (0x685) - DSP1AUX6MIX Input 1 Source
  2112. */
  2113. #define WM2200_DSP1AUX6MIX_SRC1_MASK 0x007F /* DSP1AUX6MIX_SRC1 - [6:0] */
  2114. #define WM2200_DSP1AUX6MIX_SRC1_SHIFT 0 /* DSP1AUX6MIX_SRC1 - [6:0] */
  2115. #define WM2200_DSP1AUX6MIX_SRC1_WIDTH 7 /* DSP1AUX6MIX_SRC1 - [6:0] */
  2116. /*
  2117. * R1670 (0x686) - DSP2LMIX Input 1 Source
  2118. */
  2119. #define WM2200_DSP2LMIX_SRC1_MASK 0x007F /* DSP2LMIX_SRC1 - [6:0] */
  2120. #define WM2200_DSP2LMIX_SRC1_SHIFT 0 /* DSP2LMIX_SRC1 - [6:0] */
  2121. #define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */
  2122. /*
  2123. * R1671 (0x687) - DSP2LMIX Input 1 Volume
  2124. */
  2125. #define WM2200_DSP2LMIX_VOL1_MASK 0x00FE /* DSP2LMIX_VOL1 - [7:1] */
  2126. #define WM2200_DSP2LMIX_VOL1_SHIFT 1 /* DSP2LMIX_VOL1 - [7:1] */
  2127. #define WM2200_DSP2LMIX_VOL1_WIDTH 7 /* DSP2LMIX_VOL1 - [7:1] */
  2128. /*
  2129. * R1672 (0x688) - DSP2LMIX Input 2 Source
  2130. */
  2131. #define WM2200_DSP2LMIX_SRC2_MASK 0x007F /* DSP2LMIX_SRC2 - [6:0] */
  2132. #define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */
  2133. #define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */
  2134. /*
  2135. * R1673 (0x689) - DSP2LMIX Input 2 Volume
  2136. */
  2137. #define WM2200_DSP2LMIX_VOL2_MASK 0x00FE /* DSP2LMIX_VOL2 - [7:1] */
  2138. #define WM2200_DSP2LMIX_VOL2_SHIFT 1 /* DSP2LMIX_VOL2 - [7:1] */
  2139. #define WM2200_DSP2LMIX_VOL2_WIDTH 7 /* DSP2LMIX_VOL2 - [7:1] */
  2140. /*
  2141. * R1674 (0x68A) - DSP2LMIX Input 3 Source
  2142. */
  2143. #define WM2200_DSP2LMIX_SRC3_MASK 0x007F /* DSP2LMIX_SRC3 - [6:0] */
  2144. #define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */
  2145. #define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */
  2146. /*
  2147. * R1675 (0x68B) - DSP2LMIX Input 3 Volume
  2148. */
  2149. #define WM2200_DSP2LMIX_VOL3_MASK 0x00FE /* DSP2LMIX_VOL3 - [7:1] */
  2150. #define WM2200_DSP2LMIX_VOL3_SHIFT 1 /* DSP2LMIX_VOL3 - [7:1] */
  2151. #define WM2200_DSP2LMIX_VOL3_WIDTH 7 /* DSP2LMIX_VOL3 - [7:1] */
  2152. /*
  2153. * R1676 (0x68C) - DSP2LMIX Input 4 Source
  2154. */
  2155. #define WM2200_DSP2LMIX_SRC4_MASK 0x007F /* DSP2LMIX_SRC4 - [6:0] */
  2156. #define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */
  2157. #define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */
  2158. /*
  2159. * R1677 (0x68D) - DSP2LMIX Input 4 Volume
  2160. */
  2161. #define WM2200_DSP2LMIX_VOL4_MASK 0x00FE /* DSP2LMIX_VOL4 - [7:1] */
  2162. #define WM2200_DSP2LMIX_VOL4_SHIFT 1 /* DSP2LMIX_VOL4 - [7:1] */
  2163. #define WM2200_DSP2LMIX_VOL4_WIDTH 7 /* DSP2LMIX_VOL4 - [7:1] */
  2164. /*
  2165. * R1678 (0x68E) - DSP2RMIX Input 1 Source
  2166. */
  2167. #define WM2200_DSP2RMIX_SRC1_MASK 0x007F /* DSP2RMIX_SRC1 - [6:0] */
  2168. #define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */
  2169. #define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */
  2170. /*
  2171. * R1679 (0x68F) - DSP2RMIX Input 1 Volume
  2172. */
  2173. #define WM2200_DSP2RMIX_VOL1_MASK 0x00FE /* DSP2RMIX_VOL1 - [7:1] */
  2174. #define WM2200_DSP2RMIX_VOL1_SHIFT 1 /* DSP2RMIX_VOL1 - [7:1] */
  2175. #define WM2200_DSP2RMIX_VOL1_WIDTH 7 /* DSP2RMIX_VOL1 - [7:1] */
  2176. /*
  2177. * R1680 (0x690) - DSP2RMIX Input 2 Source
  2178. */
  2179. #define WM2200_DSP2RMIX_SRC2_MASK 0x007F /* DSP2RMIX_SRC2 - [6:0] */
  2180. #define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */
  2181. #define WM2200_DSP2RMIX_SRC2_WIDTH 7 /* DSP2RMIX_SRC2 - [6:0] */
  2182. /*
  2183. * R1681 (0x691) - DSP2RMIX Input 2 Volume
  2184. */
  2185. #define WM2200_DSP2RMIX_VOL2_MASK 0x00FE /* DSP2RMIX_VOL2 - [7:1] */
  2186. #define WM2200_DSP2RMIX_VOL2_SHIFT 1 /* DSP2RMIX_VOL2 - [7:1] */
  2187. #define WM2200_DSP2RMIX_VOL2_WIDTH 7 /* DSP2RMIX_VOL2 - [7:1] */
  2188. /*
  2189. * R1682 (0x692) - DSP2RMIX Input 3 Source
  2190. */
  2191. #define WM2200_DSP2RMIX_SRC3_MASK 0x007F /* DSP2RMIX_SRC3 - [6:0] */
  2192. #define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */
  2193. #define WM2200_DSP2RMIX_SRC3_WIDTH 7 /* DSP2RMIX_SRC3 - [6:0] */
  2194. /*
  2195. * R1683 (0x693) - DSP2RMIX Input 3 Volume
  2196. */
  2197. #define WM2200_DSP2RMIX_VOL3_MASK 0x00FE /* DSP2RMIX_VOL3 - [7:1] */
  2198. #define WM2200_DSP2RMIX_VOL3_SHIFT 1 /* DSP2RMIX_VOL3 - [7:1] */
  2199. #define WM2200_DSP2RMIX_VOL3_WIDTH 7 /* DSP2RMIX_VOL3 - [7:1] */
  2200. /*
  2201. * R1684 (0x694) - DSP2RMIX Input 4 Source
  2202. */
  2203. #define WM2200_DSP2RMIX_SRC4_MASK 0x007F /* DSP2RMIX_SRC4 - [6:0] */
  2204. #define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */
  2205. #define WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 - [6:0] */
  2206. /*
  2207. * R1685 (0x695) - DSP2RMIX Input 4 Volume
  2208. */
  2209. #define WM2200_DSP2RMIX_VOL4_MASK 0x00FE /* DSP2RMIX_VOL4 - [7:1] */
  2210. #define WM2200_DSP2RMIX_VOL4_SHIFT 1 /* DSP2RMIX_VOL4 - [7:1] */
  2211. #define WM2200_DSP2RMIX_VOL4_WIDTH 7 /* DSP2RMIX_VOL4 - [7:1] */
  2212. /*
  2213. * R1686 (0x696) - DSP2AUX1MIX Input 1 Source
  2214. */
  2215. #define WM2200_DSP2AUX1MIX_SRC1_MASK 0x007F /* DSP2AUX1MIX_SRC1 - [6:0] */
  2216. #define WM2200_DSP2AUX1MIX_SRC1_SHIFT 0 /* DSP2AUX1MIX_SRC1 - [6:0] */
  2217. #define WM2200_DSP2AUX1MIX_SRC1_WIDTH 7 /* DSP2AUX1MIX_SRC1 - [6:0] */
  2218. /*
  2219. * R1687 (0x697) - DSP2AUX2MIX Input 1 Source
  2220. */
  2221. #define WM2200_DSP2AUX2MIX_SRC1_MASK 0x007F /* DSP2AUX2MIX_SRC1 - [6:0] */
  2222. #define WM2200_DSP2AUX2MIX_SRC1_SHIFT 0 /* DSP2AUX2MIX_SRC1 - [6:0] */
  2223. #define WM2200_DSP2AUX2MIX_SRC1_WIDTH 7 /* DSP2AUX2MIX_SRC1 - [6:0] */
  2224. /*
  2225. * R1688 (0x698) - DSP2AUX3MIX Input 1 Source
  2226. */
  2227. #define WM2200_DSP2AUX3MIX_SRC1_MASK 0x007F /* DSP2AUX3MIX_SRC1 - [6:0] */
  2228. #define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */
  2229. #define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */
  2230. /*
  2231. * R1689 (0x699) - DSP2AUX4MIX Input 1 Source
  2232. */
  2233. #define WM2200_DSP2AUX4MIX_SRC1_MASK 0x007F /* DSP2AUX4MIX_SRC1 - [6:0] */
  2234. #define WM2200_DSP2AUX4MIX_SRC1_SHIFT 0 /* DSP2AUX4MIX_SRC1 - [6:0] */
  2235. #define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */
  2236. /*
  2237. * R1690 (0x69A) - DSP2AUX5MIX Input 1 Source
  2238. */
  2239. #define WM2200_DSP2AUX5MIX_SRC1_MASK 0x007F /* DSP2AUX5MIX_SRC1 - [6:0] */
  2240. #define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */
  2241. #define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */
  2242. /*
  2243. * R1691 (0x69B) - DSP2AUX6MIX Input 1 Source
  2244. */
  2245. #define WM2200_DSP2AUX6MIX_SRC1_MASK 0x007F /* DSP2AUX6MIX_SRC1 - [6:0] */
  2246. #define WM2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */
  2247. #define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */
  2248. /*
  2249. * R1792 (0x700) - GPIO CTRL 1
  2250. */
  2251. #define WM2200_GP1_DIR 0x8000 /* GP1_DIR */
  2252. #define WM2200_GP1_DIR_MASK 0x8000 /* GP1_DIR */
  2253. #define WM2200_GP1_DIR_SHIFT 15 /* GP1_DIR */
  2254. #define WM2200_GP1_DIR_WIDTH 1 /* GP1_DIR */
  2255. #define WM2200_GP1_PU 0x4000 /* GP1_PU */
  2256. #define WM2200_GP1_PU_MASK 0x4000 /* GP1_PU */
  2257. #define WM2200_GP1_PU_SHIFT 14 /* GP1_PU */
  2258. #define WM2200_GP1_PU_WIDTH 1 /* GP1_PU */
  2259. #define WM2200_GP1_PD 0x2000 /* GP1_PD */
  2260. #define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */
  2261. #define WM2200_GP1_PD_SHIFT 13 /* GP1_PD */
  2262. #define WM2200_GP1_PD_WIDTH 1 /* GP1_PD */
  2263. #define WM2200_GP1_POL 0x0400 /* GP1_POL */
  2264. #define WM2200_GP1_POL_MASK 0x0400 /* GP1_POL */
  2265. #define WM2200_GP1_POL_SHIFT 10 /* GP1_POL */
  2266. #define WM2200_GP1_POL_WIDTH 1 /* GP1_POL */
  2267. #define WM2200_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
  2268. #define WM2200_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
  2269. #define WM2200_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
  2270. #define WM2200_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
  2271. #define WM2200_GP1_DB 0x0100 /* GP1_DB */
  2272. #define WM2200_GP1_DB_MASK 0x0100 /* GP1_DB */
  2273. #define WM2200_GP1_DB_SHIFT 8 /* GP1_DB */
  2274. #define WM2200_GP1_DB_WIDTH 1 /* GP1_DB */
  2275. #define WM2200_GP1_LVL 0x0040 /* GP1_LVL */
  2276. #define WM2200_GP1_LVL_MASK 0x0040 /* GP1_LVL */
  2277. #define WM2200_GP1_LVL_SHIFT 6 /* GP1_LVL */
  2278. #define WM2200_GP1_LVL_WIDTH 1 /* GP1_LVL */
  2279. #define WM2200_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */
  2280. #define WM2200_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */
  2281. #define WM2200_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */
  2282. /*
  2283. * R1793 (0x701) - GPIO CTRL 2
  2284. */
  2285. #define WM2200_GP2_DIR 0x8000 /* GP2_DIR */
  2286. #define WM2200_GP2_DIR_MASK 0x8000 /* GP2_DIR */
  2287. #define WM2200_GP2_DIR_SHIFT 15 /* GP2_DIR */
  2288. #define WM2200_GP2_DIR_WIDTH 1 /* GP2_DIR */
  2289. #define WM2200_GP2_PU 0x4000 /* GP2_PU */
  2290. #define WM2200_GP2_PU_MASK 0x4000 /* GP2_PU */
  2291. #define WM2200_GP2_PU_SHIFT 14 /* GP2_PU */
  2292. #define WM2200_GP2_PU_WIDTH 1 /* GP2_PU */
  2293. #define WM2200_GP2_PD 0x2000 /* GP2_PD */
  2294. #define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */
  2295. #define WM2200_GP2_PD_SHIFT 13 /* GP2_PD */
  2296. #define WM2200_GP2_PD_WIDTH 1 /* GP2_PD */
  2297. #define WM2200_GP2_POL 0x0400 /* GP2_POL */
  2298. #define WM2200_GP2_POL_MASK 0x0400 /* GP2_POL */
  2299. #define WM2200_GP2_POL_SHIFT 10 /* GP2_POL */
  2300. #define WM2200_GP2_POL_WIDTH 1 /* GP2_POL */
  2301. #define WM2200_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
  2302. #define WM2200_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
  2303. #define WM2200_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
  2304. #define WM2200_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
  2305. #define WM2200_GP2_DB 0x0100 /* GP2_DB */
  2306. #define WM2200_GP2_DB_MASK 0x0100 /* GP2_DB */
  2307. #define WM2200_GP2_DB_SHIFT 8 /* GP2_DB */
  2308. #define WM2200_GP2_DB_WIDTH 1 /* GP2_DB */
  2309. #define WM2200_GP2_LVL 0x0040 /* GP2_LVL */
  2310. #define WM2200_GP2_LVL_MASK 0x0040 /* GP2_LVL */
  2311. #define WM2200_GP2_LVL_SHIFT 6 /* GP2_LVL */
  2312. #define WM2200_GP2_LVL_WIDTH 1 /* GP2_LVL */
  2313. #define WM2200_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */
  2314. #define WM2200_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */
  2315. #define WM2200_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */
  2316. /*
  2317. * R1794 (0x702) - GPIO CTRL 3
  2318. */
  2319. #define WM2200_GP3_DIR 0x8000 /* GP3_DIR */
  2320. #define WM2200_GP3_DIR_MASK 0x8000 /* GP3_DIR */
  2321. #define WM2200_GP3_DIR_SHIFT 15 /* GP3_DIR */
  2322. #define WM2200_GP3_DIR_WIDTH 1 /* GP3_DIR */
  2323. #define WM2200_GP3_PU 0x4000 /* GP3_PU */
  2324. #define WM2200_GP3_PU_MASK 0x4000 /* GP3_PU */
  2325. #define WM2200_GP3_PU_SHIFT 14 /* GP3_PU */
  2326. #define WM2200_GP3_PU_WIDTH 1 /* GP3_PU */
  2327. #define WM2200_GP3_PD 0x2000 /* GP3_PD */
  2328. #define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */
  2329. #define WM2200_GP3_PD_SHIFT 13 /* GP3_PD */
  2330. #define WM2200_GP3_PD_WIDTH 1 /* GP3_PD */
  2331. #define WM2200_GP3_POL 0x0400 /* GP3_POL */
  2332. #define WM2200_GP3_POL_MASK 0x0400 /* GP3_POL */
  2333. #define WM2200_GP3_POL_SHIFT 10 /* GP3_POL */
  2334. #define WM2200_GP3_POL_WIDTH 1 /* GP3_POL */
  2335. #define WM2200_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
  2336. #define WM2200_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
  2337. #define WM2200_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
  2338. #define WM2200_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
  2339. #define WM2200_GP3_DB 0x0100 /* GP3_DB */
  2340. #define WM2200_GP3_DB_MASK 0x0100 /* GP3_DB */
  2341. #define WM2200_GP3_DB_SHIFT 8 /* GP3_DB */
  2342. #define WM2200_GP3_DB_WIDTH 1 /* GP3_DB */
  2343. #define WM2200_GP3_LVL 0x0040 /* GP3_LVL */
  2344. #define WM2200_GP3_LVL_MASK 0x0040 /* GP3_LVL */
  2345. #define WM2200_GP3_LVL_SHIFT 6 /* GP3_LVL */
  2346. #define WM2200_GP3_LVL_WIDTH 1 /* GP3_LVL */
  2347. #define WM2200_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */
  2348. #define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */
  2349. #define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */
  2350. /*
  2351. * R1795 (0x703) - GPIO CTRL 4
  2352. */
  2353. #define WM2200_GP4_DIR 0x8000 /* GP4_DIR */
  2354. #define WM2200_GP4_DIR_MASK 0x8000 /* GP4_DIR */
  2355. #define WM2200_GP4_DIR_SHIFT 15 /* GP4_DIR */
  2356. #define WM2200_GP4_DIR_WIDTH 1 /* GP4_DIR */
  2357. #define WM2200_GP4_PU 0x4000 /* GP4_PU */
  2358. #define WM2200_GP4_PU_MASK 0x4000 /* GP4_PU */
  2359. #define WM2200_GP4_PU_SHIFT 14 /* GP4_PU */
  2360. #define WM2200_GP4_PU_WIDTH 1 /* GP4_PU */
  2361. #define WM2200_GP4_PD 0x2000 /* GP4_PD */
  2362. #define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */
  2363. #define WM2200_GP4_PD_SHIFT 13 /* GP4_PD */
  2364. #define WM2200_GP4_PD_WIDTH 1 /* GP4_PD */
  2365. #define WM2200_GP4_POL 0x0400 /* GP4_POL */
  2366. #define WM2200_GP4_POL_MASK 0x0400 /* GP4_POL */
  2367. #define WM2200_GP4_POL_SHIFT 10 /* GP4_POL */
  2368. #define WM2200_GP4_POL_WIDTH 1 /* GP4_POL */
  2369. #define WM2200_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
  2370. #define WM2200_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
  2371. #define WM2200_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
  2372. #define WM2200_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
  2373. #define WM2200_GP4_DB 0x0100 /* GP4_DB */
  2374. #define WM2200_GP4_DB_MASK 0x0100 /* GP4_DB */
  2375. #define WM2200_GP4_DB_SHIFT 8 /* GP4_DB */
  2376. #define WM2200_GP4_DB_WIDTH 1 /* GP4_DB */
  2377. #define WM2200_GP4_LVL 0x0040 /* GP4_LVL */
  2378. #define WM2200_GP4_LVL_MASK 0x0040 /* GP4_LVL */
  2379. #define WM2200_GP4_LVL_SHIFT 6 /* GP4_LVL */
  2380. #define WM2200_GP4_LVL_WIDTH 1 /* GP4_LVL */
  2381. #define WM2200_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */
  2382. #define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */
  2383. #define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */
  2384. /*
  2385. * R1799 (0x707) - ADPS1 IRQ0
  2386. */
  2387. #define WM2200_DSP_IRQ1 0x0002 /* DSP_IRQ1 */
  2388. #define WM2200_DSP_IRQ1_MASK 0x0002 /* DSP_IRQ1 */
  2389. #define WM2200_DSP_IRQ1_SHIFT 1 /* DSP_IRQ1 */
  2390. #define WM2200_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */
  2391. #define WM2200_DSP_IRQ0 0x0001 /* DSP_IRQ0 */
  2392. #define WM2200_DSP_IRQ0_MASK 0x0001 /* DSP_IRQ0 */
  2393. #define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */
  2394. #define WM2200_DSP_IRQ0_WIDTH 1 /* DSP_IRQ0 */
  2395. /*
  2396. * R1800 (0x708) - ADPS1 IRQ1
  2397. */
  2398. #define WM2200_DSP_IRQ3 0x0002 /* DSP_IRQ3 */
  2399. #define WM2200_DSP_IRQ3_MASK 0x0002 /* DSP_IRQ3 */
  2400. #define WM2200_DSP_IRQ3_SHIFT 1 /* DSP_IRQ3 */
  2401. #define WM2200_DSP_IRQ3_WIDTH 1 /* DSP_IRQ3 */
  2402. #define WM2200_DSP_IRQ2 0x0001 /* DSP_IRQ2 */
  2403. #define WM2200_DSP_IRQ2_MASK 0x0001 /* DSP_IRQ2 */
  2404. #define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */
  2405. #define WM2200_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */
  2406. /*
  2407. * R1801 (0x709) - Misc Pad Ctrl 1
  2408. */
  2409. #define WM2200_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
  2410. #define WM2200_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
  2411. #define WM2200_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
  2412. #define WM2200_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
  2413. #define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */
  2414. #define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
  2415. #define WM2200_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
  2416. #define WM2200_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
  2417. #define WM2200_MCLK1_PD 0x1000 /* MCLK1_PD */
  2418. #define WM2200_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
  2419. #define WM2200_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
  2420. #define WM2200_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
  2421. #define WM2200_DACLRCLK1_PU 0x0400 /* DACLRCLK1_PU */
  2422. #define WM2200_DACLRCLK1_PU_MASK 0x0400 /* DACLRCLK1_PU */
  2423. #define WM2200_DACLRCLK1_PU_SHIFT 10 /* DACLRCLK1_PU */
  2424. #define WM2200_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
  2425. #define WM2200_DACLRCLK1_PD 0x0200 /* DACLRCLK1_PD */
  2426. #define WM2200_DACLRCLK1_PD_MASK 0x0200 /* DACLRCLK1_PD */
  2427. #define WM2200_DACLRCLK1_PD_SHIFT 9 /* DACLRCLK1_PD */
  2428. #define WM2200_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
  2429. #define WM2200_BCLK1_PU 0x0100 /* BCLK1_PU */
  2430. #define WM2200_BCLK1_PU_MASK 0x0100 /* BCLK1_PU */
  2431. #define WM2200_BCLK1_PU_SHIFT 8 /* BCLK1_PU */
  2432. #define WM2200_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
  2433. #define WM2200_BCLK1_PD 0x0080 /* BCLK1_PD */
  2434. #define WM2200_BCLK1_PD_MASK 0x0080 /* BCLK1_PD */
  2435. #define WM2200_BCLK1_PD_SHIFT 7 /* BCLK1_PD */
  2436. #define WM2200_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
  2437. #define WM2200_DACDAT1_PU 0x0040 /* DACDAT1_PU */
  2438. #define WM2200_DACDAT1_PU_MASK 0x0040 /* DACDAT1_PU */
  2439. #define WM2200_DACDAT1_PU_SHIFT 6 /* DACDAT1_PU */
  2440. #define WM2200_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
  2441. #define WM2200_DACDAT1_PD 0x0020 /* DACDAT1_PD */
  2442. #define WM2200_DACDAT1_PD_MASK 0x0020 /* DACDAT1_PD */
  2443. #define WM2200_DACDAT1_PD_SHIFT 5 /* DACDAT1_PD */
  2444. #define WM2200_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
  2445. #define WM2200_DMICDAT3_PD 0x0010 /* DMICDAT3_PD */
  2446. #define WM2200_DMICDAT3_PD_MASK 0x0010 /* DMICDAT3_PD */
  2447. #define WM2200_DMICDAT3_PD_SHIFT 4 /* DMICDAT3_PD */
  2448. #define WM2200_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
  2449. #define WM2200_DMICDAT2_PD 0x0008 /* DMICDAT2_PD */
  2450. #define WM2200_DMICDAT2_PD_MASK 0x0008 /* DMICDAT2_PD */
  2451. #define WM2200_DMICDAT2_PD_SHIFT 3 /* DMICDAT2_PD */
  2452. #define WM2200_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
  2453. #define WM2200_DMICDAT1_PD 0x0004 /* DMICDAT1_PD */
  2454. #define WM2200_DMICDAT1_PD_MASK 0x0004 /* DMICDAT1_PD */
  2455. #define WM2200_DMICDAT1_PD_SHIFT 2 /* DMICDAT1_PD */
  2456. #define WM2200_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
  2457. #define WM2200_RSTB_PU 0x0002 /* RSTB_PU */
  2458. #define WM2200_RSTB_PU_MASK 0x0002 /* RSTB_PU */
  2459. #define WM2200_RSTB_PU_SHIFT 1 /* RSTB_PU */
  2460. #define WM2200_RSTB_PU_WIDTH 1 /* RSTB_PU */
  2461. #define WM2200_ADDR_PD 0x0001 /* ADDR_PD */
  2462. #define WM2200_ADDR_PD_MASK 0x0001 /* ADDR_PD */
  2463. #define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */
  2464. #define WM2200_ADDR_PD_WIDTH 1 /* ADDR_PD */
  2465. /*
  2466. * R2048 (0x800) - Interrupt Status 1
  2467. */
  2468. #define WM2200_DSP_IRQ0_EINT 0x0080 /* DSP_IRQ0_EINT */
  2469. #define WM2200_DSP_IRQ0_EINT_MASK 0x0080 /* DSP_IRQ0_EINT */
  2470. #define WM2200_DSP_IRQ0_EINT_SHIFT 7 /* DSP_IRQ0_EINT */
  2471. #define WM2200_DSP_IRQ0_EINT_WIDTH 1 /* DSP_IRQ0_EINT */
  2472. #define WM2200_DSP_IRQ1_EINT 0x0040 /* DSP_IRQ1_EINT */
  2473. #define WM2200_DSP_IRQ1_EINT_MASK 0x0040 /* DSP_IRQ1_EINT */
  2474. #define WM2200_DSP_IRQ1_EINT_SHIFT 6 /* DSP_IRQ1_EINT */
  2475. #define WM2200_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */
  2476. #define WM2200_DSP_IRQ2_EINT 0x0020 /* DSP_IRQ2_EINT */
  2477. #define WM2200_DSP_IRQ2_EINT_MASK 0x0020 /* DSP_IRQ2_EINT */
  2478. #define WM2200_DSP_IRQ2_EINT_SHIFT 5 /* DSP_IRQ2_EINT */
  2479. #define WM2200_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */
  2480. #define WM2200_DSP_IRQ3_EINT 0x0010 /* DSP_IRQ3_EINT */
  2481. #define WM2200_DSP_IRQ3_EINT_MASK 0x0010 /* DSP_IRQ3_EINT */
  2482. #define WM2200_DSP_IRQ3_EINT_SHIFT 4 /* DSP_IRQ3_EINT */
  2483. #define WM2200_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */
  2484. #define WM2200_GP4_EINT 0x0008 /* GP4_EINT */
  2485. #define WM2200_GP4_EINT_MASK 0x0008 /* GP4_EINT */
  2486. #define WM2200_GP4_EINT_SHIFT 3 /* GP4_EINT */
  2487. #define WM2200_GP4_EINT_WIDTH 1 /* GP4_EINT */
  2488. #define WM2200_GP3_EINT 0x0004 /* GP3_EINT */
  2489. #define WM2200_GP3_EINT_MASK 0x0004 /* GP3_EINT */
  2490. #define WM2200_GP3_EINT_SHIFT 2 /* GP3_EINT */
  2491. #define WM2200_GP3_EINT_WIDTH 1 /* GP3_EINT */
  2492. #define WM2200_GP2_EINT 0x0002 /* GP2_EINT */
  2493. #define WM2200_GP2_EINT_MASK 0x0002 /* GP2_EINT */
  2494. #define WM2200_GP2_EINT_SHIFT 1 /* GP2_EINT */
  2495. #define WM2200_GP2_EINT_WIDTH 1 /* GP2_EINT */
  2496. #define WM2200_GP1_EINT 0x0001 /* GP1_EINT */
  2497. #define WM2200_GP1_EINT_MASK 0x0001 /* GP1_EINT */
  2498. #define WM2200_GP1_EINT_SHIFT 0 /* GP1_EINT */
  2499. #define WM2200_GP1_EINT_WIDTH 1 /* GP1_EINT */
  2500. /*
  2501. * R2049 (0x801) - Interrupt Status 1 Mask
  2502. */
  2503. #define WM2200_IM_DSP_IRQ0_EINT 0x0080 /* IM_DSP_IRQ0_EINT */
  2504. #define WM2200_IM_DSP_IRQ0_EINT_MASK 0x0080 /* IM_DSP_IRQ0_EINT */
  2505. #define WM2200_IM_DSP_IRQ0_EINT_SHIFT 7 /* IM_DSP_IRQ0_EINT */
  2506. #define WM2200_IM_DSP_IRQ0_EINT_WIDTH 1 /* IM_DSP_IRQ0_EINT */
  2507. #define WM2200_IM_DSP_IRQ1_EINT 0x0040 /* IM_DSP_IRQ1_EINT */
  2508. #define WM2200_IM_DSP_IRQ1_EINT_MASK 0x0040 /* IM_DSP_IRQ1_EINT */
  2509. #define WM2200_IM_DSP_IRQ1_EINT_SHIFT 6 /* IM_DSP_IRQ1_EINT */
  2510. #define WM2200_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */
  2511. #define WM2200_IM_DSP_IRQ2_EINT 0x0020 /* IM_DSP_IRQ2_EINT */
  2512. #define WM2200_IM_DSP_IRQ2_EINT_MASK 0x0020 /* IM_DSP_IRQ2_EINT */
  2513. #define WM2200_IM_DSP_IRQ2_EINT_SHIFT 5 /* IM_DSP_IRQ2_EINT */
  2514. #define WM2200_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */
  2515. #define WM2200_IM_DSP_IRQ3_EINT 0x0010 /* IM_DSP_IRQ3_EINT */
  2516. #define WM2200_IM_DSP_IRQ3_EINT_MASK 0x0010 /* IM_DSP_IRQ3_EINT */
  2517. #define WM2200_IM_DSP_IRQ3_EINT_SHIFT 4 /* IM_DSP_IRQ3_EINT */
  2518. #define WM2200_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */
  2519. #define WM2200_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
  2520. #define WM2200_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
  2521. #define WM2200_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
  2522. #define WM2200_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
  2523. #define WM2200_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
  2524. #define WM2200_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
  2525. #define WM2200_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
  2526. #define WM2200_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
  2527. #define WM2200_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
  2528. #define WM2200_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
  2529. #define WM2200_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
  2530. #define WM2200_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
  2531. #define WM2200_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
  2532. #define WM2200_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
  2533. #define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
  2534. #define WM2200_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
  2535. /*
  2536. * R2050 (0x802) - Interrupt Status 2
  2537. */
  2538. #define WM2200_WSEQ_BUSY_EINT 0x0100 /* WSEQ_BUSY_EINT */
  2539. #define WM2200_WSEQ_BUSY_EINT_MASK 0x0100 /* WSEQ_BUSY_EINT */
  2540. #define WM2200_WSEQ_BUSY_EINT_SHIFT 8 /* WSEQ_BUSY_EINT */
  2541. #define WM2200_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
  2542. #define WM2200_FLL_LOCK_EINT 0x0002 /* FLL_LOCK_EINT */
  2543. #define WM2200_FLL_LOCK_EINT_MASK 0x0002 /* FLL_LOCK_EINT */
  2544. #define WM2200_FLL_LOCK_EINT_SHIFT 1 /* FLL_LOCK_EINT */
  2545. #define WM2200_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */
  2546. #define WM2200_CLKGEN_EINT 0x0001 /* CLKGEN_EINT */
  2547. #define WM2200_CLKGEN_EINT_MASK 0x0001 /* CLKGEN_EINT */
  2548. #define WM2200_CLKGEN_EINT_SHIFT 0 /* CLKGEN_EINT */
  2549. #define WM2200_CLKGEN_EINT_WIDTH 1 /* CLKGEN_EINT */
  2550. /*
  2551. * R2051 (0x803) - Interrupt Raw Status 2
  2552. */
  2553. #define WM2200_WSEQ_BUSY_STS 0x0100 /* WSEQ_BUSY_STS */
  2554. #define WM2200_WSEQ_BUSY_STS_MASK 0x0100 /* WSEQ_BUSY_STS */
  2555. #define WM2200_WSEQ_BUSY_STS_SHIFT 8 /* WSEQ_BUSY_STS */
  2556. #define WM2200_WSEQ_BUSY_STS_WIDTH 1 /* WSEQ_BUSY_STS */
  2557. #define WM2200_FLL_LOCK_STS 0x0002 /* FLL_LOCK_STS */
  2558. #define WM2200_FLL_LOCK_STS_MASK 0x0002 /* FLL_LOCK_STS */
  2559. #define WM2200_FLL_LOCK_STS_SHIFT 1 /* FLL_LOCK_STS */
  2560. #define WM2200_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */
  2561. #define WM2200_CLKGEN_STS 0x0001 /* CLKGEN_STS */
  2562. #define WM2200_CLKGEN_STS_MASK 0x0001 /* CLKGEN_STS */
  2563. #define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */
  2564. #define WM2200_CLKGEN_STS_WIDTH 1 /* CLKGEN_STS */
  2565. /*
  2566. * R2052 (0x804) - Interrupt Status 2 Mask
  2567. */
  2568. #define WM2200_IM_WSEQ_BUSY_EINT 0x0100 /* IM_WSEQ_BUSY_EINT */
  2569. #define WM2200_IM_WSEQ_BUSY_EINT_MASK 0x0100 /* IM_WSEQ_BUSY_EINT */
  2570. #define WM2200_IM_WSEQ_BUSY_EINT_SHIFT 8 /* IM_WSEQ_BUSY_EINT */
  2571. #define WM2200_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
  2572. #define WM2200_IM_FLL_LOCK_EINT 0x0002 /* IM_FLL_LOCK_EINT */
  2573. #define WM2200_IM_FLL_LOCK_EINT_MASK 0x0002 /* IM_FLL_LOCK_EINT */
  2574. #define WM2200_IM_FLL_LOCK_EINT_SHIFT 1 /* IM_FLL_LOCK_EINT */
  2575. #define WM2200_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */
  2576. #define WM2200_IM_CLKGEN_EINT 0x0001 /* IM_CLKGEN_EINT */
  2577. #define WM2200_IM_CLKGEN_EINT_MASK 0x0001 /* IM_CLKGEN_EINT */
  2578. #define WM2200_IM_CLKGEN_EINT_SHIFT 0 /* IM_CLKGEN_EINT */
  2579. #define WM2200_IM_CLKGEN_EINT_WIDTH 1 /* IM_CLKGEN_EINT */
  2580. /*
  2581. * R2056 (0x808) - Interrupt Control
  2582. */
  2583. #define WM2200_IM_IRQ 0x0001 /* IM_IRQ */
  2584. #define WM2200_IM_IRQ_MASK 0x0001 /* IM_IRQ */
  2585. #define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */
  2586. #define WM2200_IM_IRQ_WIDTH 1 /* IM_IRQ */
  2587. /*
  2588. * R2304 (0x900) - EQL_1
  2589. */
  2590. #define WM2200_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */
  2591. #define WM2200_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */
  2592. #define WM2200_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */
  2593. #define WM2200_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */
  2594. #define WM2200_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */
  2595. #define WM2200_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */
  2596. #define WM2200_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */
  2597. #define WM2200_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */
  2598. #define WM2200_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */
  2599. #define WM2200_EQL_ENA 0x0001 /* EQL_ENA */
  2600. #define WM2200_EQL_ENA_MASK 0x0001 /* EQL_ENA */
  2601. #define WM2200_EQL_ENA_SHIFT 0 /* EQL_ENA */
  2602. #define WM2200_EQL_ENA_WIDTH 1 /* EQL_ENA */
  2603. /*
  2604. * R2305 (0x901) - EQL_2
  2605. */
  2606. #define WM2200_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */
  2607. #define WM2200_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */
  2608. #define WM2200_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */
  2609. #define WM2200_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */
  2610. #define WM2200_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */
  2611. #define WM2200_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */
  2612. /*
  2613. * R2306 (0x902) - EQL_3
  2614. */
  2615. #define WM2200_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */
  2616. #define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */
  2617. #define WM2200_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */
  2618. /*
  2619. * R2307 (0x903) - EQL_4
  2620. */
  2621. #define WM2200_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */
  2622. #define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */
  2623. #define WM2200_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */
  2624. /*
  2625. * R2308 (0x904) - EQL_5
  2626. */
  2627. #define WM2200_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */
  2628. #define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */
  2629. #define WM2200_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */
  2630. /*
  2631. * R2309 (0x905) - EQL_6
  2632. */
  2633. #define WM2200_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */
  2634. #define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */
  2635. #define WM2200_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */
  2636. /*
  2637. * R2310 (0x906) - EQL_7
  2638. */
  2639. #define WM2200_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */
  2640. #define WM2200_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */
  2641. #define WM2200_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */
  2642. /*
  2643. * R2311 (0x907) - EQL_8
  2644. */
  2645. #define WM2200_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */
  2646. #define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */
  2647. #define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */
  2648. /*
  2649. * R2312 (0x908) - EQL_9
  2650. */
  2651. #define WM2200_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */
  2652. #define WM2200_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */
  2653. #define WM2200_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */
  2654. /*
  2655. * R2313 (0x909) - EQL_10
  2656. */
  2657. #define WM2200_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */
  2658. #define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */
  2659. #define WM2200_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */
  2660. /*
  2661. * R2314 (0x90A) - EQL_11
  2662. */
  2663. #define WM2200_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */
  2664. #define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */
  2665. #define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */
  2666. /*
  2667. * R2315 (0x90B) - EQL_12
  2668. */
  2669. #define WM2200_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */
  2670. #define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */
  2671. #define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */
  2672. /*
  2673. * R2316 (0x90C) - EQL_13
  2674. */
  2675. #define WM2200_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */
  2676. #define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */
  2677. #define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */
  2678. /*
  2679. * R2317 (0x90D) - EQL_14
  2680. */
  2681. #define WM2200_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */
  2682. #define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */
  2683. #define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */
  2684. /*
  2685. * R2318 (0x90E) - EQL_15
  2686. */
  2687. #define WM2200_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */
  2688. #define WM2200_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */
  2689. #define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */
  2690. /*
  2691. * R2319 (0x90F) - EQL_16
  2692. */
  2693. #define WM2200_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */
  2694. #define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */
  2695. #define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */
  2696. /*
  2697. * R2320 (0x910) - EQL_17
  2698. */
  2699. #define WM2200_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */
  2700. #define WM2200_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */
  2701. #define WM2200_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */
  2702. /*
  2703. * R2321 (0x911) - EQL_18
  2704. */
  2705. #define WM2200_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */
  2706. #define WM2200_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */
  2707. #define WM2200_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */
  2708. /*
  2709. * R2322 (0x912) - EQL_19
  2710. */
  2711. #define WM2200_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */
  2712. #define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */
  2713. #define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */
  2714. /*
  2715. * R2323 (0x913) - EQL_20
  2716. */
  2717. #define WM2200_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */
  2718. #define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */
  2719. #define WM2200_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */
  2720. /*
  2721. * R2326 (0x916) - EQR_1
  2722. */
  2723. #define WM2200_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */
  2724. #define WM2200_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */
  2725. #define WM2200_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */
  2726. #define WM2200_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */
  2727. #define WM2200_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */
  2728. #define WM2200_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */
  2729. #define WM2200_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */
  2730. #define WM2200_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */
  2731. #define WM2200_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */
  2732. #define WM2200_EQR_ENA 0x0001 /* EQR_ENA */
  2733. #define WM2200_EQR_ENA_MASK 0x0001 /* EQR_ENA */
  2734. #define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */
  2735. #define WM2200_EQR_ENA_WIDTH 1 /* EQR_ENA */
  2736. /*
  2737. * R2327 (0x917) - EQR_2
  2738. */
  2739. #define WM2200_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */
  2740. #define WM2200_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */
  2741. #define WM2200_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */
  2742. #define WM2200_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */
  2743. #define WM2200_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */
  2744. #define WM2200_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */
  2745. /*
  2746. * R2328 (0x918) - EQR_3
  2747. */
  2748. #define WM2200_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */
  2749. #define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */
  2750. #define WM2200_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */
  2751. /*
  2752. * R2329 (0x919) - EQR_4
  2753. */
  2754. #define WM2200_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */
  2755. #define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */
  2756. #define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */
  2757. /*
  2758. * R2330 (0x91A) - EQR_5
  2759. */
  2760. #define WM2200_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */
  2761. #define WM2200_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */
  2762. #define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */
  2763. /*
  2764. * R2331 (0x91B) - EQR_6
  2765. */
  2766. #define WM2200_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */
  2767. #define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */
  2768. #define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */
  2769. /*
  2770. * R2332 (0x91C) - EQR_7
  2771. */
  2772. #define WM2200_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */
  2773. #define WM2200_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */
  2774. #define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */
  2775. /*
  2776. * R2333 (0x91D) - EQR_8
  2777. */
  2778. #define WM2200_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */
  2779. #define WM2200_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */
  2780. #define WM2200_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */
  2781. /*
  2782. * R2334 (0x91E) - EQR_9
  2783. */
  2784. #define WM2200_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */
  2785. #define WM2200_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */
  2786. #define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */
  2787. /*
  2788. * R2335 (0x91F) - EQR_10
  2789. */
  2790. #define WM2200_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */
  2791. #define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */
  2792. #define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */
  2793. /*
  2794. * R2336 (0x920) - EQR_11
  2795. */
  2796. #define WM2200_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */
  2797. #define WM2200_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */
  2798. #define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */
  2799. /*
  2800. * R2337 (0x921) - EQR_12
  2801. */
  2802. #define WM2200_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */
  2803. #define WM2200_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */
  2804. #define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */
  2805. /*
  2806. * R2338 (0x922) - EQR_13
  2807. */
  2808. #define WM2200_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */
  2809. #define WM2200_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */
  2810. #define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */
  2811. /*
  2812. * R2339 (0x923) - EQR_14
  2813. */
  2814. #define WM2200_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */
  2815. #define WM2200_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */
  2816. #define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */
  2817. /*
  2818. * R2340 (0x924) - EQR_15
  2819. */
  2820. #define WM2200_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */
  2821. #define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */
  2822. #define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */
  2823. /*
  2824. * R2341 (0x925) - EQR_16
  2825. */
  2826. #define WM2200_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */
  2827. #define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */
  2828. #define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */
  2829. /*
  2830. * R2342 (0x926) - EQR_17
  2831. */
  2832. #define WM2200_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */
  2833. #define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */
  2834. #define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */
  2835. /*
  2836. * R2343 (0x927) - EQR_18
  2837. */
  2838. #define WM2200_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */
  2839. #define WM2200_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */
  2840. #define WM2200_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */
  2841. /*
  2842. * R2344 (0x928) - EQR_19
  2843. */
  2844. #define WM2200_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */
  2845. #define WM2200_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */
  2846. #define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */
  2847. /*
  2848. * R2345 (0x929) - EQR_20
  2849. */
  2850. #define WM2200_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */
  2851. #define WM2200_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */
  2852. #define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */
  2853. /*
  2854. * R2366 (0x93E) - HPLPF1_1
  2855. */
  2856. #define WM2200_LHPF1_MODE 0x0002 /* LHPF1_MODE */
  2857. #define WM2200_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
  2858. #define WM2200_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
  2859. #define WM2200_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
  2860. #define WM2200_LHPF1_ENA 0x0001 /* LHPF1_ENA */
  2861. #define WM2200_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
  2862. #define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
  2863. #define WM2200_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
  2864. /*
  2865. * R2367 (0x93F) - HPLPF1_2
  2866. */
  2867. #define WM2200_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
  2868. #define WM2200_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
  2869. #define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
  2870. /*
  2871. * R2370 (0x942) - HPLPF2_1
  2872. */
  2873. #define WM2200_LHPF2_MODE 0x0002 /* LHPF2_MODE */
  2874. #define WM2200_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
  2875. #define WM2200_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
  2876. #define WM2200_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
  2877. #define WM2200_LHPF2_ENA 0x0001 /* LHPF2_ENA */
  2878. #define WM2200_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
  2879. #define WM2200_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
  2880. #define WM2200_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
  2881. /*
  2882. * R2371 (0x943) - HPLPF2_2
  2883. */
  2884. #define WM2200_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
  2885. #define WM2200_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
  2886. #define WM2200_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
  2887. /*
  2888. * R2560 (0xA00) - DSP1 Control 1
  2889. */
  2890. #define WM2200_DSP1_RW_SEQUENCE_ENA 0x0001 /* DSP1_RW_SEQUENCE_ENA */
  2891. #define WM2200_DSP1_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP1_RW_SEQUENCE_ENA */
  2892. #define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */
  2893. #define WM2200_DSP1_RW_SEQUENCE_ENA_WIDTH 1 /* DSP1_RW_SEQUENCE_ENA */
  2894. /*
  2895. * R2562 (0xA02) - DSP1 Control 2
  2896. */
  2897. #define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */
  2898. #define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT 8 /* DSP1_PAGE_BASE_PM - [15:8] */
  2899. #define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH 8 /* DSP1_PAGE_BASE_PM - [15:8] */
  2900. /*
  2901. * R2563 (0xA03) - DSP1 Control 3
  2902. */
  2903. #define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */
  2904. #define WM2200_DSP1_PAGE_BASE_DM_0_SHIFT 8 /* DSP1_PAGE_BASE_DM - [15:8] */
  2905. #define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH 8 /* DSP1_PAGE_BASE_DM - [15:8] */
  2906. /*
  2907. * R2564 (0xA04) - DSP1 Control 4
  2908. */
  2909. #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */
  2910. #define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT 8 /* DSP1_PAGE_BASE_ZM - [15:8] */
  2911. #define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH 8 /* DSP1_PAGE_BASE_ZM - [15:8] */
  2912. /*
  2913. * R2566 (0xA06) - DSP1 Control 5
  2914. */
  2915. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
  2916. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
  2917. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
  2918. /*
  2919. * R2567 (0xA07) - DSP1 Control 6
  2920. */
  2921. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
  2922. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
  2923. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
  2924. /*
  2925. * R2568 (0xA08) - DSP1 Control 7
  2926. */
  2927. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
  2928. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
  2929. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
  2930. /*
  2931. * R2569 (0xA09) - DSP1 Control 8
  2932. */
  2933. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
  2934. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
  2935. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
  2936. /*
  2937. * R2570 (0xA0A) - DSP1 Control 9
  2938. */
  2939. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
  2940. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
  2941. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
  2942. /*
  2943. * R2571 (0xA0B) - DSP1 Control 10
  2944. */
  2945. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
  2946. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
  2947. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
  2948. /*
  2949. * R2572 (0xA0C) - DSP1 Control 11
  2950. */
  2951. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
  2952. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
  2953. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
  2954. /*
  2955. * R2573 (0xA0D) - DSP1 Control 12
  2956. */
  2957. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
  2958. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
  2959. #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
  2960. /*
  2961. * R2575 (0xA0F) - DSP1 Control 13
  2962. */
  2963. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
  2964. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
  2965. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
  2966. /*
  2967. * R2576 (0xA10) - DSP1 Control 14
  2968. */
  2969. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
  2970. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
  2971. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
  2972. /*
  2973. * R2577 (0xA11) - DSP1 Control 15
  2974. */
  2975. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
  2976. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
  2977. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
  2978. /*
  2979. * R2578 (0xA12) - DSP1 Control 16
  2980. */
  2981. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
  2982. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
  2983. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
  2984. /*
  2985. * R2579 (0xA13) - DSP1 Control 17
  2986. */
  2987. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
  2988. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
  2989. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
  2990. /*
  2991. * R2580 (0xA14) - DSP1 Control 18
  2992. */
  2993. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
  2994. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
  2995. #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
  2996. /*
  2997. * R2582 (0xA16) - DSP1 Control 19
  2998. */
  2999. #define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  3000. #define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  3001. #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  3002. /*
  3003. * R2583 (0xA17) - DSP1 Control 20
  3004. */
  3005. #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
  3006. #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
  3007. #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
  3008. /*
  3009. * R2584 (0xA18) - DSP1 Control 21
  3010. */
  3011. #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
  3012. #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
  3013. #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
  3014. /*
  3015. * R2586 (0xA1A) - DSP1 Control 22
  3016. */
  3017. #define WM2200_DSP1_DM_SIZE_MASK 0xFFFF /* DSP1_DM_SIZE - [15:0] */
  3018. #define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */
  3019. #define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */
  3020. /*
  3021. * R2587 (0xA1B) - DSP1 Control 23
  3022. */
  3023. #define WM2200_DSP1_PM_SIZE_MASK 0xFFFF /* DSP1_PM_SIZE - [15:0] */
  3024. #define WM2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE - [15:0] */
  3025. #define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */
  3026. /*
  3027. * R2588 (0xA1C) - DSP1 Control 24
  3028. */
  3029. #define WM2200_DSP1_ZM_SIZE_MASK 0xFFFF /* DSP1_ZM_SIZE - [15:0] */
  3030. #define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */
  3031. #define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */
  3032. /*
  3033. * R2590 (0xA1E) - DSP1 Control 25
  3034. */
  3035. #define WM2200_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
  3036. #define WM2200_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
  3037. #define WM2200_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */
  3038. #define WM2200_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */
  3039. #define WM2200_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
  3040. #define WM2200_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
  3041. #define WM2200_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */
  3042. #define WM2200_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */
  3043. #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  3044. #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  3045. #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  3046. /*
  3047. * R2592 (0xA20) - DSP1 Control 26
  3048. */
  3049. #define WM2200_DSP1_SCRATCH_0_MASK 0xFFFF /* DSP1_SCRATCH_0 - [15:0] */
  3050. #define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */
  3051. #define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */
  3052. /*
  3053. * R2593 (0xA21) - DSP1 Control 27
  3054. */
  3055. #define WM2200_DSP1_SCRATCH_1_MASK 0xFFFF /* DSP1_SCRATCH_1 - [15:0] */
  3056. #define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */
  3057. #define WM2200_DSP1_SCRATCH_1_WIDTH 16 /* DSP1_SCRATCH_1 - [15:0] */
  3058. /*
  3059. * R2594 (0xA22) - DSP1 Control 28
  3060. */
  3061. #define WM2200_DSP1_SCRATCH_2_MASK 0xFFFF /* DSP1_SCRATCH_2 - [15:0] */
  3062. #define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */
  3063. #define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */
  3064. /*
  3065. * R2595 (0xA23) - DSP1 Control 29
  3066. */
  3067. #define WM2200_DSP1_SCRATCH_3_MASK 0xFFFF /* DSP1_SCRATCH_3 - [15:0] */
  3068. #define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */
  3069. #define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */
  3070. /*
  3071. * R2596 (0xA24) - DSP1 Control 30
  3072. */
  3073. #define WM2200_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
  3074. #define WM2200_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
  3075. #define WM2200_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
  3076. #define WM2200_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
  3077. #define WM2200_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
  3078. #define WM2200_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
  3079. #define WM2200_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
  3080. #define WM2200_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
  3081. #define WM2200_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
  3082. #define WM2200_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
  3083. #define WM2200_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
  3084. #define WM2200_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
  3085. #define WM2200_DSP1_START 0x0001 /* DSP1_START */
  3086. #define WM2200_DSP1_START_MASK 0x0001 /* DSP1_START */
  3087. #define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */
  3088. #define WM2200_DSP1_START_WIDTH 1 /* DSP1_START */
  3089. /*
  3090. * R2598 (0xA26) - DSP1 Control 31
  3091. */
  3092. #define WM2200_DSP1_CLK_RATE_MASK 0x0018 /* DSP1_CLK_RATE - [4:3] */
  3093. #define WM2200_DSP1_CLK_RATE_SHIFT 3 /* DSP1_CLK_RATE - [4:3] */
  3094. #define WM2200_DSP1_CLK_RATE_WIDTH 2 /* DSP1_CLK_RATE - [4:3] */
  3095. #define WM2200_DSP1_CLK_AVAIL 0x0004 /* DSP1_CLK_AVAIL */
  3096. #define WM2200_DSP1_CLK_AVAIL_MASK 0x0004 /* DSP1_CLK_AVAIL */
  3097. #define WM2200_DSP1_CLK_AVAIL_SHIFT 2 /* DSP1_CLK_AVAIL */
  3098. #define WM2200_DSP1_CLK_AVAIL_WIDTH 1 /* DSP1_CLK_AVAIL */
  3099. #define WM2200_DSP1_CLK_REQ_MASK 0x0003 /* DSP1_CLK_REQ - [1:0] */
  3100. #define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */
  3101. #define WM2200_DSP1_CLK_REQ_WIDTH 2 /* DSP1_CLK_REQ - [1:0] */
  3102. /*
  3103. * R2816 (0xB00) - DSP2 Control 1
  3104. */
  3105. #define WM2200_DSP2_RW_SEQUENCE_ENA 0x0001 /* DSP2_RW_SEQUENCE_ENA */
  3106. #define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP2_RW_SEQUENCE_ENA */
  3107. #define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */
  3108. #define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH 1 /* DSP2_RW_SEQUENCE_ENA */
  3109. /*
  3110. * R2818 (0xB02) - DSP2 Control 2
  3111. */
  3112. #define WM2200_DSP2_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_PM - [15:8] */
  3113. #define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT 8 /* DSP2_PAGE_BASE_PM - [15:8] */
  3114. #define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH 8 /* DSP2_PAGE_BASE_PM - [15:8] */
  3115. /*
  3116. * R2819 (0xB03) - DSP2 Control 3
  3117. */
  3118. #define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */
  3119. #define WM2200_DSP2_PAGE_BASE_DM_0_SHIFT 8 /* DSP2_PAGE_BASE_DM - [15:8] */
  3120. #define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH 8 /* DSP2_PAGE_BASE_DM - [15:8] */
  3121. /*
  3122. * R2820 (0xB04) - DSP2 Control 4
  3123. */
  3124. #define WM2200_DSP2_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_ZM - [15:8] */
  3125. #define WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT 8 /* DSP2_PAGE_BASE_ZM - [15:8] */
  3126. #define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH 8 /* DSP2_PAGE_BASE_ZM - [15:8] */
  3127. /*
  3128. * R2822 (0xB06) - DSP2 Control 5
  3129. */
  3130. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
  3131. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
  3132. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
  3133. /*
  3134. * R2823 (0xB07) - DSP2 Control 6
  3135. */
  3136. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
  3137. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
  3138. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
  3139. /*
  3140. * R2824 (0xB08) - DSP2 Control 7
  3141. */
  3142. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
  3143. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
  3144. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
  3145. /*
  3146. * R2825 (0xB09) - DSP2 Control 8
  3147. */
  3148. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
  3149. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
  3150. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
  3151. /*
  3152. * R2826 (0xB0A) - DSP2 Control 9
  3153. */
  3154. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
  3155. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
  3156. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
  3157. /*
  3158. * R2827 (0xB0B) - DSP2 Control 10
  3159. */
  3160. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
  3161. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
  3162. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
  3163. /*
  3164. * R2828 (0xB0C) - DSP2 Control 11
  3165. */
  3166. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
  3167. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
  3168. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
  3169. /*
  3170. * R2829 (0xB0D) - DSP2 Control 12
  3171. */
  3172. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
  3173. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
  3174. #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
  3175. /*
  3176. * R2831 (0xB0F) - DSP2 Control 13
  3177. */
  3178. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
  3179. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
  3180. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
  3181. /*
  3182. * R2832 (0xB10) - DSP2 Control 14
  3183. */
  3184. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
  3185. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
  3186. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
  3187. /*
  3188. * R2833 (0xB11) - DSP2 Control 15
  3189. */
  3190. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
  3191. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
  3192. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
  3193. /*
  3194. * R2834 (0xB12) - DSP2 Control 16
  3195. */
  3196. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
  3197. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
  3198. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
  3199. /*
  3200. * R2835 (0xB13) - DSP2 Control 17
  3201. */
  3202. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
  3203. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
  3204. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
  3205. /*
  3206. * R2836 (0xB14) - DSP2 Control 18
  3207. */
  3208. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
  3209. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
  3210. #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
  3211. /*
  3212. * R2838 (0xB16) - DSP2 Control 19
  3213. */
  3214. #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
  3215. #define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
  3216. #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
  3217. /*
  3218. * R2839 (0xB17) - DSP2 Control 20
  3219. */
  3220. #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
  3221. #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
  3222. #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
  3223. /*
  3224. * R2840 (0xB18) - DSP2 Control 21
  3225. */
  3226. #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
  3227. #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
  3228. #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
  3229. /*
  3230. * R2842 (0xB1A) - DSP2 Control 22
  3231. */
  3232. #define WM2200_DSP2_DM_SIZE_MASK 0xFFFF /* DSP2_DM_SIZE - [15:0] */
  3233. #define WM2200_DSP2_DM_SIZE_SHIFT 0 /* DSP2_DM_SIZE - [15:0] */
  3234. #define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */
  3235. /*
  3236. * R2843 (0xB1B) - DSP2 Control 23
  3237. */
  3238. #define WM2200_DSP2_PM_SIZE_MASK 0xFFFF /* DSP2_PM_SIZE - [15:0] */
  3239. #define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */
  3240. #define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */
  3241. /*
  3242. * R2844 (0xB1C) - DSP2 Control 24
  3243. */
  3244. #define WM2200_DSP2_ZM_SIZE_MASK 0xFFFF /* DSP2_ZM_SIZE - [15:0] */
  3245. #define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */
  3246. #define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */
  3247. /*
  3248. * R2846 (0xB1E) - DSP2 Control 25
  3249. */
  3250. #define WM2200_DSP2_PING_FULL 0x8000 /* DSP2_PING_FULL */
  3251. #define WM2200_DSP2_PING_FULL_MASK 0x8000 /* DSP2_PING_FULL */
  3252. #define WM2200_DSP2_PING_FULL_SHIFT 15 /* DSP2_PING_FULL */
  3253. #define WM2200_DSP2_PING_FULL_WIDTH 1 /* DSP2_PING_FULL */
  3254. #define WM2200_DSP2_PONG_FULL 0x4000 /* DSP2_PONG_FULL */
  3255. #define WM2200_DSP2_PONG_FULL_MASK 0x4000 /* DSP2_PONG_FULL */
  3256. #define WM2200_DSP2_PONG_FULL_SHIFT 14 /* DSP2_PONG_FULL */
  3257. #define WM2200_DSP2_PONG_FULL_WIDTH 1 /* DSP2_PONG_FULL */
  3258. #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
  3259. #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
  3260. #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
  3261. /*
  3262. * R2848 (0xB20) - DSP2 Control 26
  3263. */
  3264. #define WM2200_DSP2_SCRATCH_0_MASK 0xFFFF /* DSP2_SCRATCH_0 - [15:0] */
  3265. #define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */
  3266. #define WM2200_DSP2_SCRATCH_0_WIDTH 16 /* DSP2_SCRATCH_0 - [15:0] */
  3267. /*
  3268. * R2849 (0xB21) - DSP2 Control 27
  3269. */
  3270. #define WM2200_DSP2_SCRATCH_1_MASK 0xFFFF /* DSP2_SCRATCH_1 - [15:0] */
  3271. #define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */
  3272. #define WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */
  3273. /*
  3274. * R2850 (0xB22) - DSP2 Control 28
  3275. */
  3276. #define WM2200_DSP2_SCRATCH_2_MASK 0xFFFF /* DSP2_SCRATCH_2 - [15:0] */
  3277. #define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */
  3278. #define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */
  3279. /*
  3280. * R2851 (0xB23) - DSP2 Control 29
  3281. */
  3282. #define WM2200_DSP2_SCRATCH_3_MASK 0xFFFF /* DSP2_SCRATCH_3 - [15:0] */
  3283. #define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */
  3284. #define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */
  3285. /*
  3286. * R2852 (0xB24) - DSP2 Control 30
  3287. */
  3288. #define WM2200_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */
  3289. #define WM2200_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */
  3290. #define WM2200_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */
  3291. #define WM2200_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */
  3292. #define WM2200_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */
  3293. #define WM2200_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */
  3294. #define WM2200_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */
  3295. #define WM2200_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */
  3296. #define WM2200_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */
  3297. #define WM2200_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */
  3298. #define WM2200_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */
  3299. #define WM2200_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */
  3300. #define WM2200_DSP2_START 0x0001 /* DSP2_START */
  3301. #define WM2200_DSP2_START_MASK 0x0001 /* DSP2_START */
  3302. #define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */
  3303. #define WM2200_DSP2_START_WIDTH 1 /* DSP2_START */
  3304. /*
  3305. * R2854 (0xB26) - DSP2 Control 31
  3306. */
  3307. #define WM2200_DSP2_CLK_RATE_MASK 0x0018 /* DSP2_CLK_RATE - [4:3] */
  3308. #define WM2200_DSP2_CLK_RATE_SHIFT 3 /* DSP2_CLK_RATE - [4:3] */
  3309. #define WM2200_DSP2_CLK_RATE_WIDTH 2 /* DSP2_CLK_RATE - [4:3] */
  3310. #define WM2200_DSP2_CLK_AVAIL 0x0004 /* DSP2_CLK_AVAIL */
  3311. #define WM2200_DSP2_CLK_AVAIL_MASK 0x0004 /* DSP2_CLK_AVAIL */
  3312. #define WM2200_DSP2_CLK_AVAIL_SHIFT 2 /* DSP2_CLK_AVAIL */
  3313. #define WM2200_DSP2_CLK_AVAIL_WIDTH 1 /* DSP2_CLK_AVAIL */
  3314. #define WM2200_DSP2_CLK_REQ_MASK 0x0003 /* DSP2_CLK_REQ - [1:0] */
  3315. #define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */
  3316. #define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */
  3317. #endif