wm0010.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wm0010.c -- WM0010 DSP Driver
  4. *
  5. * Copyright 2012 Wolfson Microelectronics PLC.
  6. *
  7. * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
  8. * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  9. * Scott Ling <sl@opensource.wolfsonmicro.com>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irqreturn.h>
  15. #include <linux/init.h>
  16. #include <linux/spi/spi.h>
  17. #include <linux/firmware.h>
  18. #include <linux/delay.h>
  19. #include <linux/fs.h>
  20. #include <linux/gpio.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/mutex.h>
  23. #include <linux/workqueue.h>
  24. #include <sound/soc.h>
  25. #include <sound/wm0010.h>
  26. #define DEVICE_ID_WM0010 10
  27. /* We only support v1 of the .dfw INFO record */
  28. #define INFO_VERSION 1
  29. enum dfw_cmd {
  30. DFW_CMD_FUSE = 0x01,
  31. DFW_CMD_CODE_HDR,
  32. DFW_CMD_CODE_DATA,
  33. DFW_CMD_PLL,
  34. DFW_CMD_INFO = 0xff
  35. };
  36. struct dfw_binrec {
  37. u8 command;
  38. u32 length:24;
  39. u32 address;
  40. uint8_t data[];
  41. } __packed;
  42. struct dfw_inforec {
  43. u8 info_version;
  44. u8 tool_major_version;
  45. u8 tool_minor_version;
  46. u8 dsp_target;
  47. };
  48. struct dfw_pllrec {
  49. u8 command;
  50. u32 length:24;
  51. u32 address;
  52. u32 clkctrl1;
  53. u32 clkctrl2;
  54. u32 clkctrl3;
  55. u32 ldetctrl;
  56. u32 uart_div;
  57. u32 spi_div;
  58. } __packed;
  59. static struct pll_clock_map {
  60. int max_sysclk;
  61. int max_pll_spi_speed;
  62. u32 pll_clkctrl1;
  63. } pll_clock_map[] = { /* Dividers */
  64. { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
  65. { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
  66. { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
  67. { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
  68. { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
  69. { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
  70. };
  71. enum wm0010_state {
  72. WM0010_POWER_OFF,
  73. WM0010_OUT_OF_RESET,
  74. WM0010_BOOTROM,
  75. WM0010_STAGE2,
  76. WM0010_FIRMWARE,
  77. };
  78. struct wm0010_priv {
  79. struct snd_soc_component *component;
  80. struct mutex lock;
  81. struct device *dev;
  82. struct wm0010_pdata pdata;
  83. int gpio_reset;
  84. int gpio_reset_value;
  85. struct regulator_bulk_data core_supplies[2];
  86. struct regulator *dbvdd;
  87. int sysclk;
  88. enum wm0010_state state;
  89. bool boot_failed;
  90. bool ready;
  91. bool pll_running;
  92. int max_spi_freq;
  93. int board_max_spi_speed;
  94. u32 pll_clkctrl1;
  95. spinlock_t irq_lock;
  96. int irq;
  97. struct completion boot_completion;
  98. };
  99. struct wm0010_spi_msg {
  100. struct spi_message m;
  101. struct spi_transfer t;
  102. u8 *tx_buf;
  103. u8 *rx_buf;
  104. size_t len;
  105. };
  106. static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
  107. SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
  108. };
  109. static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
  110. { "SDI2 Capture", NULL, "SDI1 Playback" },
  111. { "SDI1 Capture", NULL, "SDI2 Playback" },
  112. { "SDI1 Capture", NULL, "CLKIN" },
  113. { "SDI2 Capture", NULL, "CLKIN" },
  114. { "SDI1 Playback", NULL, "CLKIN" },
  115. { "SDI2 Playback", NULL, "CLKIN" },
  116. };
  117. static const char *wm0010_state_to_str(enum wm0010_state state)
  118. {
  119. static const char * const state_to_str[] = {
  120. "Power off",
  121. "Out of reset",
  122. "Boot ROM",
  123. "Stage2",
  124. "Firmware"
  125. };
  126. if (state < 0 || state >= ARRAY_SIZE(state_to_str))
  127. return "null";
  128. return state_to_str[state];
  129. }
  130. /* Called with wm0010->lock held */
  131. static void wm0010_halt(struct snd_soc_component *component)
  132. {
  133. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  134. unsigned long flags;
  135. enum wm0010_state state;
  136. /* Fetch the wm0010 state */
  137. spin_lock_irqsave(&wm0010->irq_lock, flags);
  138. state = wm0010->state;
  139. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  140. switch (state) {
  141. case WM0010_POWER_OFF:
  142. /* If there's nothing to do, bail out */
  143. return;
  144. case WM0010_OUT_OF_RESET:
  145. case WM0010_BOOTROM:
  146. case WM0010_STAGE2:
  147. case WM0010_FIRMWARE:
  148. /* Remember to put chip back into reset */
  149. gpio_set_value_cansleep(wm0010->gpio_reset,
  150. wm0010->gpio_reset_value);
  151. /* Disable the regulators */
  152. regulator_disable(wm0010->dbvdd);
  153. regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
  154. wm0010->core_supplies);
  155. break;
  156. }
  157. spin_lock_irqsave(&wm0010->irq_lock, flags);
  158. wm0010->state = WM0010_POWER_OFF;
  159. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  160. }
  161. struct wm0010_boot_xfer {
  162. struct list_head list;
  163. struct snd_soc_component *component;
  164. struct completion *done;
  165. struct spi_message m;
  166. struct spi_transfer t;
  167. };
  168. /* Called with wm0010->lock held */
  169. static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
  170. {
  171. enum wm0010_state state;
  172. unsigned long flags;
  173. spin_lock_irqsave(&wm0010->irq_lock, flags);
  174. state = wm0010->state;
  175. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  176. dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
  177. wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
  178. wm0010->boot_failed = true;
  179. }
  180. static void wm0010_boot_xfer_complete(void *data)
  181. {
  182. struct wm0010_boot_xfer *xfer = data;
  183. struct snd_soc_component *component = xfer->component;
  184. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  185. u32 *out32 = xfer->t.rx_buf;
  186. int i;
  187. if (xfer->m.status != 0) {
  188. dev_err(component->dev, "SPI transfer failed: %d\n",
  189. xfer->m.status);
  190. wm0010_mark_boot_failure(wm0010);
  191. if (xfer->done)
  192. complete(xfer->done);
  193. return;
  194. }
  195. for (i = 0; i < xfer->t.len / 4; i++) {
  196. dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
  197. switch (be32_to_cpu(out32[i])) {
  198. case 0xe0e0e0e0:
  199. dev_err(component->dev,
  200. "%d: ROM error reported in stage 2\n", i);
  201. wm0010_mark_boot_failure(wm0010);
  202. break;
  203. case 0x55555555:
  204. if (wm0010->state < WM0010_STAGE2)
  205. break;
  206. dev_err(component->dev,
  207. "%d: ROM bootloader running in stage 2\n", i);
  208. wm0010_mark_boot_failure(wm0010);
  209. break;
  210. case 0x0fed0000:
  211. dev_dbg(component->dev, "Stage2 loader running\n");
  212. break;
  213. case 0x0fed0007:
  214. dev_dbg(component->dev, "CODE_HDR packet received\n");
  215. break;
  216. case 0x0fed0008:
  217. dev_dbg(component->dev, "CODE_DATA packet received\n");
  218. break;
  219. case 0x0fed0009:
  220. dev_dbg(component->dev, "Download complete\n");
  221. break;
  222. case 0x0fed000c:
  223. dev_dbg(component->dev, "Application start\n");
  224. break;
  225. case 0x0fed000e:
  226. dev_dbg(component->dev, "PLL packet received\n");
  227. wm0010->pll_running = true;
  228. break;
  229. case 0x0fed0025:
  230. dev_err(component->dev, "Device reports image too long\n");
  231. wm0010_mark_boot_failure(wm0010);
  232. break;
  233. case 0x0fed002c:
  234. dev_err(component->dev, "Device reports bad SPI packet\n");
  235. wm0010_mark_boot_failure(wm0010);
  236. break;
  237. case 0x0fed0031:
  238. dev_err(component->dev, "Device reports SPI read overflow\n");
  239. wm0010_mark_boot_failure(wm0010);
  240. break;
  241. case 0x0fed0032:
  242. dev_err(component->dev, "Device reports SPI underclock\n");
  243. wm0010_mark_boot_failure(wm0010);
  244. break;
  245. case 0x0fed0033:
  246. dev_err(component->dev, "Device reports bad header packet\n");
  247. wm0010_mark_boot_failure(wm0010);
  248. break;
  249. case 0x0fed0034:
  250. dev_err(component->dev, "Device reports invalid packet type\n");
  251. wm0010_mark_boot_failure(wm0010);
  252. break;
  253. case 0x0fed0035:
  254. dev_err(component->dev, "Device reports data before header error\n");
  255. wm0010_mark_boot_failure(wm0010);
  256. break;
  257. case 0x0fed0038:
  258. dev_err(component->dev, "Device reports invalid PLL packet\n");
  259. break;
  260. case 0x0fed003a:
  261. dev_err(component->dev, "Device reports packet alignment error\n");
  262. wm0010_mark_boot_failure(wm0010);
  263. break;
  264. default:
  265. dev_err(component->dev, "Unrecognised return 0x%x\n",
  266. be32_to_cpu(out32[i]));
  267. wm0010_mark_boot_failure(wm0010);
  268. break;
  269. }
  270. if (wm0010->boot_failed)
  271. break;
  272. }
  273. if (xfer->done)
  274. complete(xfer->done);
  275. }
  276. static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
  277. {
  278. int i;
  279. for (i = 0; i < len / 8; i++)
  280. data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
  281. }
  282. static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
  283. {
  284. struct spi_device *spi = to_spi_device(component->dev);
  285. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  286. struct list_head xfer_list;
  287. struct wm0010_boot_xfer *xfer;
  288. int ret;
  289. DECLARE_COMPLETION_ONSTACK(done);
  290. const struct firmware *fw;
  291. const struct dfw_binrec *rec;
  292. const struct dfw_inforec *inforec;
  293. u64 *img;
  294. u8 *out, dsp;
  295. u32 len, offset;
  296. INIT_LIST_HEAD(&xfer_list);
  297. ret = request_firmware(&fw, name, component->dev);
  298. if (ret != 0) {
  299. dev_err(component->dev, "Failed to request application(%s): %d\n",
  300. name, ret);
  301. return ret;
  302. }
  303. rec = (const struct dfw_binrec *)fw->data;
  304. inforec = (const struct dfw_inforec *)rec->data;
  305. offset = 0;
  306. dsp = inforec->dsp_target;
  307. wm0010->boot_failed = false;
  308. if (WARN_ON(!list_empty(&xfer_list)))
  309. return -EINVAL;
  310. /* First record should be INFO */
  311. if (rec->command != DFW_CMD_INFO) {
  312. dev_err(component->dev, "First record not INFO\r\n");
  313. ret = -EINVAL;
  314. goto abort;
  315. }
  316. if (inforec->info_version != INFO_VERSION) {
  317. dev_err(component->dev,
  318. "Unsupported version (%02d) of INFO record\r\n",
  319. inforec->info_version);
  320. ret = -EINVAL;
  321. goto abort;
  322. }
  323. dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
  324. inforec->info_version);
  325. /* Check it's a DSP file */
  326. if (dsp != DEVICE_ID_WM0010) {
  327. dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
  328. ret = -EINVAL;
  329. goto abort;
  330. }
  331. /* Skip the info record as we don't need to send it */
  332. offset += ((rec->length) + 8);
  333. rec = (void *)&rec->data[rec->length];
  334. while (offset < fw->size) {
  335. dev_dbg(component->dev,
  336. "Packet: command %d, data length = 0x%x\r\n",
  337. rec->command, rec->length);
  338. len = rec->length + 8;
  339. xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
  340. if (!xfer) {
  341. ret = -ENOMEM;
  342. goto abort;
  343. }
  344. xfer->component = component;
  345. list_add_tail(&xfer->list, &xfer_list);
  346. out = kzalloc(len, GFP_KERNEL | GFP_DMA);
  347. if (!out) {
  348. ret = -ENOMEM;
  349. goto abort1;
  350. }
  351. xfer->t.rx_buf = out;
  352. img = kzalloc(len, GFP_KERNEL | GFP_DMA);
  353. if (!img) {
  354. ret = -ENOMEM;
  355. goto abort1;
  356. }
  357. xfer->t.tx_buf = img;
  358. byte_swap_64((u64 *)&rec->command, img, len);
  359. spi_message_init(&xfer->m);
  360. xfer->m.complete = wm0010_boot_xfer_complete;
  361. xfer->m.context = xfer;
  362. xfer->t.len = len;
  363. xfer->t.bits_per_word = 8;
  364. if (!wm0010->pll_running) {
  365. xfer->t.speed_hz = wm0010->sysclk / 6;
  366. } else {
  367. xfer->t.speed_hz = wm0010->max_spi_freq;
  368. if (wm0010->board_max_spi_speed &&
  369. (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
  370. xfer->t.speed_hz = wm0010->board_max_spi_speed;
  371. }
  372. /* Store max usable spi frequency for later use */
  373. wm0010->max_spi_freq = xfer->t.speed_hz;
  374. spi_message_add_tail(&xfer->t, &xfer->m);
  375. offset += ((rec->length) + 8);
  376. rec = (void *)&rec->data[rec->length];
  377. if (offset >= fw->size) {
  378. dev_dbg(component->dev, "All transfers scheduled\n");
  379. xfer->done = &done;
  380. }
  381. ret = spi_async(spi, &xfer->m);
  382. if (ret != 0) {
  383. dev_err(component->dev, "Write failed: %d\n", ret);
  384. goto abort1;
  385. }
  386. if (wm0010->boot_failed) {
  387. dev_dbg(component->dev, "Boot fail!\n");
  388. ret = -EINVAL;
  389. goto abort1;
  390. }
  391. }
  392. wait_for_completion(&done);
  393. ret = 0;
  394. abort1:
  395. while (!list_empty(&xfer_list)) {
  396. xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
  397. list);
  398. kfree(xfer->t.rx_buf);
  399. kfree(xfer->t.tx_buf);
  400. list_del(&xfer->list);
  401. kfree(xfer);
  402. }
  403. abort:
  404. release_firmware(fw);
  405. return ret;
  406. }
  407. static int wm0010_stage2_load(struct snd_soc_component *component)
  408. {
  409. struct spi_device *spi = to_spi_device(component->dev);
  410. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  411. const struct firmware *fw;
  412. struct spi_message m;
  413. struct spi_transfer t;
  414. u32 *img;
  415. u8 *out;
  416. int i;
  417. int ret = 0;
  418. ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev);
  419. if (ret != 0) {
  420. dev_err(component->dev, "Failed to request stage2 loader: %d\n",
  421. ret);
  422. return ret;
  423. }
  424. dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
  425. /* Copy to local buffer first as vmalloc causes problems for dma */
  426. img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA);
  427. if (!img) {
  428. ret = -ENOMEM;
  429. goto abort2;
  430. }
  431. out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
  432. if (!out) {
  433. ret = -ENOMEM;
  434. goto abort1;
  435. }
  436. spi_message_init(&m);
  437. memset(&t, 0, sizeof(t));
  438. t.rx_buf = out;
  439. t.tx_buf = img;
  440. t.len = fw->size;
  441. t.bits_per_word = 8;
  442. t.speed_hz = wm0010->sysclk / 10;
  443. spi_message_add_tail(&t, &m);
  444. dev_dbg(component->dev, "Starting initial download at %dHz\n",
  445. t.speed_hz);
  446. ret = spi_sync(spi, &m);
  447. if (ret != 0) {
  448. dev_err(component->dev, "Initial download failed: %d\n", ret);
  449. goto abort;
  450. }
  451. /* Look for errors from the boot ROM */
  452. for (i = 0; i < fw->size; i++) {
  453. if (out[i] != 0x55) {
  454. dev_err(component->dev, "Boot ROM error: %x in %d\n",
  455. out[i], i);
  456. wm0010_mark_boot_failure(wm0010);
  457. ret = -EBUSY;
  458. goto abort;
  459. }
  460. }
  461. abort:
  462. kfree(out);
  463. abort1:
  464. kfree(img);
  465. abort2:
  466. release_firmware(fw);
  467. return ret;
  468. }
  469. static int wm0010_boot(struct snd_soc_component *component)
  470. {
  471. struct spi_device *spi = to_spi_device(component->dev);
  472. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  473. unsigned long flags;
  474. int ret;
  475. struct spi_message m;
  476. struct spi_transfer t;
  477. struct dfw_pllrec pll_rec;
  478. u32 *p, len;
  479. u64 *img_swap;
  480. u8 *out;
  481. int i;
  482. spin_lock_irqsave(&wm0010->irq_lock, flags);
  483. if (wm0010->state != WM0010_POWER_OFF)
  484. dev_warn(wm0010->dev, "DSP already powered up!\n");
  485. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  486. if (wm0010->sysclk > 26000000) {
  487. dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
  488. ret = -ECANCELED;
  489. goto err;
  490. }
  491. mutex_lock(&wm0010->lock);
  492. wm0010->pll_running = false;
  493. dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
  494. ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
  495. wm0010->core_supplies);
  496. if (ret != 0) {
  497. dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
  498. ret);
  499. mutex_unlock(&wm0010->lock);
  500. goto err;
  501. }
  502. ret = regulator_enable(wm0010->dbvdd);
  503. if (ret != 0) {
  504. dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
  505. goto err_core;
  506. }
  507. /* Release reset */
  508. gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
  509. spin_lock_irqsave(&wm0010->irq_lock, flags);
  510. wm0010->state = WM0010_OUT_OF_RESET;
  511. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  512. if (!wait_for_completion_timeout(&wm0010->boot_completion,
  513. msecs_to_jiffies(20)))
  514. dev_err(component->dev, "Failed to get interrupt from DSP\n");
  515. spin_lock_irqsave(&wm0010->irq_lock, flags);
  516. wm0010->state = WM0010_BOOTROM;
  517. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  518. ret = wm0010_stage2_load(component);
  519. if (ret)
  520. goto abort;
  521. if (!wait_for_completion_timeout(&wm0010->boot_completion,
  522. msecs_to_jiffies(20)))
  523. dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
  524. spin_lock_irqsave(&wm0010->irq_lock, flags);
  525. wm0010->state = WM0010_STAGE2;
  526. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  527. /* Only initialise PLL if max_spi_freq initialised */
  528. if (wm0010->max_spi_freq) {
  529. /* Initialise a PLL record */
  530. memset(&pll_rec, 0, sizeof(pll_rec));
  531. pll_rec.command = DFW_CMD_PLL;
  532. pll_rec.length = (sizeof(pll_rec) - 8);
  533. /* On wm0010 only the CLKCTRL1 value is used */
  534. pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
  535. ret = -ENOMEM;
  536. len = pll_rec.length + 8;
  537. out = kzalloc(len, GFP_KERNEL | GFP_DMA);
  538. if (!out)
  539. goto abort;
  540. img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
  541. if (!img_swap)
  542. goto abort_out;
  543. /* We need to re-order for 0010 */
  544. byte_swap_64((u64 *)&pll_rec, img_swap, len);
  545. spi_message_init(&m);
  546. memset(&t, 0, sizeof(t));
  547. t.rx_buf = out;
  548. t.tx_buf = img_swap;
  549. t.len = len;
  550. t.bits_per_word = 8;
  551. t.speed_hz = wm0010->sysclk / 6;
  552. spi_message_add_tail(&t, &m);
  553. ret = spi_sync(spi, &m);
  554. if (ret) {
  555. dev_err(component->dev, "First PLL write failed: %d\n", ret);
  556. goto abort_swap;
  557. }
  558. /* Use a second send of the message to get the return status */
  559. ret = spi_sync(spi, &m);
  560. if (ret) {
  561. dev_err(component->dev, "Second PLL write failed: %d\n", ret);
  562. goto abort_swap;
  563. }
  564. p = (u32 *)out;
  565. /* Look for PLL active code from the DSP */
  566. for (i = 0; i < len / 4; i++) {
  567. if (*p == 0x0e00ed0f) {
  568. dev_dbg(component->dev, "PLL packet received\n");
  569. wm0010->pll_running = true;
  570. break;
  571. }
  572. p++;
  573. }
  574. kfree(img_swap);
  575. kfree(out);
  576. } else
  577. dev_dbg(component->dev, "Not enabling DSP PLL.");
  578. ret = wm0010_firmware_load("wm0010.dfw", component);
  579. if (ret != 0)
  580. goto abort;
  581. spin_lock_irqsave(&wm0010->irq_lock, flags);
  582. wm0010->state = WM0010_FIRMWARE;
  583. spin_unlock_irqrestore(&wm0010->irq_lock, flags);
  584. mutex_unlock(&wm0010->lock);
  585. return 0;
  586. abort_swap:
  587. kfree(img_swap);
  588. abort_out:
  589. kfree(out);
  590. abort:
  591. /* Put the chip back into reset */
  592. wm0010_halt(component);
  593. mutex_unlock(&wm0010->lock);
  594. return ret;
  595. err_core:
  596. mutex_unlock(&wm0010->lock);
  597. regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
  598. wm0010->core_supplies);
  599. err:
  600. return ret;
  601. }
  602. static int wm0010_set_bias_level(struct snd_soc_component *component,
  603. enum snd_soc_bias_level level)
  604. {
  605. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  606. switch (level) {
  607. case SND_SOC_BIAS_ON:
  608. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
  609. wm0010_boot(component);
  610. break;
  611. case SND_SOC_BIAS_PREPARE:
  612. break;
  613. case SND_SOC_BIAS_STANDBY:
  614. if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
  615. mutex_lock(&wm0010->lock);
  616. wm0010_halt(component);
  617. mutex_unlock(&wm0010->lock);
  618. }
  619. break;
  620. case SND_SOC_BIAS_OFF:
  621. break;
  622. }
  623. return 0;
  624. }
  625. static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
  626. int clk_id, unsigned int freq, int dir)
  627. {
  628. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  629. unsigned int i;
  630. wm0010->sysclk = freq;
  631. if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
  632. wm0010->max_spi_freq = 0;
  633. } else {
  634. for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
  635. if (freq >= pll_clock_map[i].max_sysclk) {
  636. wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
  637. wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
  638. break;
  639. }
  640. }
  641. return 0;
  642. }
  643. static int wm0010_probe(struct snd_soc_component *component);
  644. static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
  645. .probe = wm0010_probe,
  646. .set_bias_level = wm0010_set_bias_level,
  647. .set_sysclk = wm0010_set_sysclk,
  648. .dapm_widgets = wm0010_dapm_widgets,
  649. .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
  650. .dapm_routes = wm0010_dapm_routes,
  651. .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
  652. .use_pmdown_time = 1,
  653. .endianness = 1,
  654. .non_legacy_dai_naming = 1,
  655. };
  656. #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  657. #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
  658. SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
  659. SNDRV_PCM_FMTBIT_S32_LE)
  660. static struct snd_soc_dai_driver wm0010_dai[] = {
  661. {
  662. .name = "wm0010-sdi1",
  663. .playback = {
  664. .stream_name = "SDI1 Playback",
  665. .channels_min = 1,
  666. .channels_max = 2,
  667. .rates = WM0010_RATES,
  668. .formats = WM0010_FORMATS,
  669. },
  670. .capture = {
  671. .stream_name = "SDI1 Capture",
  672. .channels_min = 1,
  673. .channels_max = 2,
  674. .rates = WM0010_RATES,
  675. .formats = WM0010_FORMATS,
  676. },
  677. },
  678. {
  679. .name = "wm0010-sdi2",
  680. .playback = {
  681. .stream_name = "SDI2 Playback",
  682. .channels_min = 1,
  683. .channels_max = 2,
  684. .rates = WM0010_RATES,
  685. .formats = WM0010_FORMATS,
  686. },
  687. .capture = {
  688. .stream_name = "SDI2 Capture",
  689. .channels_min = 1,
  690. .channels_max = 2,
  691. .rates = WM0010_RATES,
  692. .formats = WM0010_FORMATS,
  693. },
  694. },
  695. };
  696. static irqreturn_t wm0010_irq(int irq, void *data)
  697. {
  698. struct wm0010_priv *wm0010 = data;
  699. switch (wm0010->state) {
  700. case WM0010_OUT_OF_RESET:
  701. case WM0010_BOOTROM:
  702. case WM0010_STAGE2:
  703. spin_lock(&wm0010->irq_lock);
  704. complete(&wm0010->boot_completion);
  705. spin_unlock(&wm0010->irq_lock);
  706. return IRQ_HANDLED;
  707. default:
  708. return IRQ_NONE;
  709. }
  710. return IRQ_NONE;
  711. }
  712. static int wm0010_probe(struct snd_soc_component *component)
  713. {
  714. struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
  715. wm0010->component = component;
  716. return 0;
  717. }
  718. static int wm0010_spi_probe(struct spi_device *spi)
  719. {
  720. unsigned long gpio_flags;
  721. int ret;
  722. int trigger;
  723. int irq;
  724. struct wm0010_priv *wm0010;
  725. wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
  726. GFP_KERNEL);
  727. if (!wm0010)
  728. return -ENOMEM;
  729. mutex_init(&wm0010->lock);
  730. spin_lock_init(&wm0010->irq_lock);
  731. spi_set_drvdata(spi, wm0010);
  732. wm0010->dev = &spi->dev;
  733. if (dev_get_platdata(&spi->dev))
  734. memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
  735. sizeof(wm0010->pdata));
  736. init_completion(&wm0010->boot_completion);
  737. wm0010->core_supplies[0].supply = "AVDD";
  738. wm0010->core_supplies[1].supply = "DCVDD";
  739. ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
  740. wm0010->core_supplies);
  741. if (ret != 0) {
  742. dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
  743. ret);
  744. return ret;
  745. }
  746. wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
  747. if (IS_ERR(wm0010->dbvdd)) {
  748. ret = PTR_ERR(wm0010->dbvdd);
  749. dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
  750. return ret;
  751. }
  752. if (wm0010->pdata.gpio_reset) {
  753. wm0010->gpio_reset = wm0010->pdata.gpio_reset;
  754. if (wm0010->pdata.reset_active_high)
  755. wm0010->gpio_reset_value = 1;
  756. else
  757. wm0010->gpio_reset_value = 0;
  758. if (wm0010->gpio_reset_value)
  759. gpio_flags = GPIOF_OUT_INIT_HIGH;
  760. else
  761. gpio_flags = GPIOF_OUT_INIT_LOW;
  762. ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
  763. gpio_flags, "wm0010 reset");
  764. if (ret < 0) {
  765. dev_err(wm0010->dev,
  766. "Failed to request GPIO for DSP reset: %d\n",
  767. ret);
  768. return ret;
  769. }
  770. } else {
  771. dev_err(wm0010->dev, "No reset GPIO configured\n");
  772. return -EINVAL;
  773. }
  774. wm0010->state = WM0010_POWER_OFF;
  775. irq = spi->irq;
  776. if (wm0010->pdata.irq_flags)
  777. trigger = wm0010->pdata.irq_flags;
  778. else
  779. trigger = IRQF_TRIGGER_FALLING;
  780. trigger |= IRQF_ONESHOT;
  781. ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
  782. "wm0010", wm0010);
  783. if (ret) {
  784. dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
  785. irq, ret);
  786. return ret;
  787. }
  788. wm0010->irq = irq;
  789. ret = irq_set_irq_wake(irq, 1);
  790. if (ret) {
  791. dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
  792. irq, ret);
  793. return ret;
  794. }
  795. if (spi->max_speed_hz)
  796. wm0010->board_max_spi_speed = spi->max_speed_hz;
  797. else
  798. wm0010->board_max_spi_speed = 0;
  799. ret = devm_snd_soc_register_component(&spi->dev,
  800. &soc_component_dev_wm0010, wm0010_dai,
  801. ARRAY_SIZE(wm0010_dai));
  802. if (ret < 0)
  803. return ret;
  804. return 0;
  805. }
  806. static int wm0010_spi_remove(struct spi_device *spi)
  807. {
  808. struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
  809. gpio_set_value_cansleep(wm0010->gpio_reset,
  810. wm0010->gpio_reset_value);
  811. irq_set_irq_wake(wm0010->irq, 0);
  812. if (wm0010->irq)
  813. free_irq(wm0010->irq, wm0010);
  814. return 0;
  815. }
  816. static struct spi_driver wm0010_spi_driver = {
  817. .driver = {
  818. .name = "wm0010",
  819. },
  820. .probe = wm0010_spi_probe,
  821. .remove = wm0010_spi_remove,
  822. };
  823. module_spi_driver(wm0010_spi_driver);
  824. MODULE_DESCRIPTION("ASoC WM0010 driver");
  825. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  826. MODULE_LICENSE("GPL");