wcd934x.c 162 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2019, Linaro Limited
  3. #include <linux/clk.h>
  4. #include <linux/clk-provider.h>
  5. #include <linux/interrupt.h>
  6. #include <linux/kernel.h>
  7. #include <linux/mfd/wcd934x/registers.h>
  8. #include <linux/mfd/wcd934x/wcd934x.h>
  9. #include <linux/module.h>
  10. #include <linux/mutex.h>
  11. #include <linux/of_clk.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/regmap.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/slab.h>
  17. #include <linux/slimbus.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/soc.h>
  20. #include <sound/soc-dapm.h>
  21. #include <sound/tlv.h>
  22. #include "wcd-clsh-v2.h"
  23. #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  24. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  25. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  26. /* Fractional Rates */
  27. #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  28. SNDRV_PCM_RATE_176400)
  29. #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  30. SNDRV_PCM_FMTBIT_S24_LE)
  31. /* slave port water mark level
  32. * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  33. */
  34. #define SLAVE_PORT_WATER_MARK_6BYTES 0
  35. #define SLAVE_PORT_WATER_MARK_9BYTES 1
  36. #define SLAVE_PORT_WATER_MARK_12BYTES 2
  37. #define SLAVE_PORT_WATER_MARK_15BYTES 3
  38. #define SLAVE_PORT_WATER_MARK_SHIFT 1
  39. #define SLAVE_PORT_ENABLE 1
  40. #define SLAVE_PORT_DISABLE 0
  41. #define WCD934X_SLIM_WATER_MARK_VAL \
  42. ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  43. (SLAVE_PORT_ENABLE))
  44. #define WCD934X_SLIM_NUM_PORT_REG 3
  45. #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  46. #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
  47. #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
  48. #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
  49. #define WCD934X_MCLK_CLK_12P288MHZ 12288000
  50. #define WCD934X_MCLK_CLK_9P6MHZ 9600000
  51. /* Only valid for 9.6 MHz mclk */
  52. #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  53. #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  54. /* Only valid for 12.288 MHz mclk */
  55. #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  56. #define WCD934X_DMIC_CLK_DIV_2 0x0
  57. #define WCD934X_DMIC_CLK_DIV_3 0x1
  58. #define WCD934X_DMIC_CLK_DIV_4 0x2
  59. #define WCD934X_DMIC_CLK_DIV_6 0x3
  60. #define WCD934X_DMIC_CLK_DIV_8 0x4
  61. #define WCD934X_DMIC_CLK_DIV_16 0x5
  62. #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  63. #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
  64. #define CF_MIN_3DB_4HZ 0x0
  65. #define CF_MIN_3DB_75HZ 0x1
  66. #define CF_MIN_3DB_150HZ 0x2
  67. #define WCD934X_RX_START 16
  68. #define WCD934X_NUM_INTERPOLATORS 9
  69. #define WCD934X_RX_PATH_CTL_OFFSET 20
  70. #define WCD934X_MAX_VALID_ADC_MUX 13
  71. #define WCD934X_INVALID_ADC_MUX 9
  72. #define WCD934X_SLIM_RX_CH(p) \
  73. {.port = p + WCD934X_RX_START, .shift = p,}
  74. #define WCD934X_SLIM_TX_CH(p) \
  75. {.port = p, .shift = p,}
  76. /* Feature masks to distinguish codec version */
  77. #define DSD_DISABLED_MASK 0
  78. #define SLNQ_DISABLED_MASK 1
  79. #define DSD_DISABLED BIT(DSD_DISABLED_MASK)
  80. #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
  81. /* As fine version info cannot be retrieved before wcd probe.
  82. * Define three coarse versions for possible future use before wcd probe.
  83. */
  84. #define WCD_VERSION_WCD9340_1_0 0x400
  85. #define WCD_VERSION_WCD9341_1_0 0x410
  86. #define WCD_VERSION_WCD9340_1_1 0x401
  87. #define WCD_VERSION_WCD9341_1_1 0x411
  88. #define WCD934X_AMIC_PWR_LEVEL_LP 0
  89. #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
  90. #define WCD934X_AMIC_PWR_LEVEL_HP 2
  91. #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
  92. #define WCD934X_AMIC_PWR_LVL_MASK 0x60
  93. #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
  94. #define WCD934X_DEC_PWR_LVL_MASK 0x06
  95. #define WCD934X_DEC_PWR_LVL_LP 0x02
  96. #define WCD934X_DEC_PWR_LVL_HP 0x04
  97. #define WCD934X_DEC_PWR_LVL_DF 0x00
  98. #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
  99. #define WCD934X_DEF_MICBIAS_MV 1800
  100. #define WCD934X_MAX_MICBIAS_MV 2850
  101. #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
  102. #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
  103. { \
  104. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  105. .info = wcd934x_iir_filter_info, \
  106. .get = wcd934x_get_iir_band_audio_mixer, \
  107. .put = wcd934x_put_iir_band_audio_mixer, \
  108. .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
  109. .iir_idx = iidx, \
  110. .band_idx = bidx, \
  111. .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
  112. } \
  113. }
  114. #define WCD934X_INTERPOLATOR_PATH(id) \
  115. {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
  116. {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
  117. {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
  118. {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
  119. {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
  120. {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
  121. {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
  122. {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
  123. {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
  124. {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
  125. {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
  126. {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
  127. {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
  128. {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
  129. {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
  130. {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
  131. {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
  132. {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
  133. {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
  134. {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
  135. {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
  136. {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
  137. {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
  138. {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
  139. {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
  140. {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
  141. {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
  142. {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
  143. {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
  144. {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
  145. {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
  146. {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
  147. {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
  148. {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
  149. {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
  150. {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
  151. {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
  152. {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
  153. {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
  154. {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
  155. {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
  156. {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
  157. {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
  158. {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
  159. {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
  160. {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
  161. {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
  162. {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
  163. {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
  164. #define WCD934X_INTERPOLATOR_MIX2(id) \
  165. {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
  166. {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
  167. #define WCD934X_SLIM_RX_AIF_PATH(id) \
  168. {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
  169. {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
  170. {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
  171. {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
  172. {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
  173. #define WCD934X_ADC_MUX(id) \
  174. {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
  175. {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
  176. {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
  177. {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
  178. {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
  179. {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
  180. {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
  181. {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
  182. {"AMIC MUX" #id, "ADC1", "ADC1"}, \
  183. {"AMIC MUX" #id, "ADC2", "ADC2"}, \
  184. {"AMIC MUX" #id, "ADC3", "ADC3"}, \
  185. {"AMIC MUX" #id, "ADC4", "ADC4"}
  186. #define WCD934X_IIR_INP_MUX(id) \
  187. {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
  188. {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
  189. {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
  190. {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
  191. {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
  192. {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
  193. {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
  194. {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
  195. {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
  196. {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
  197. {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
  198. {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
  199. {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
  200. {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
  201. {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
  202. {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
  203. {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
  204. {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
  205. {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
  206. {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
  207. {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
  208. {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
  209. {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
  210. {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
  211. {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
  212. {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
  213. {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
  214. {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
  215. {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
  216. {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
  217. {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
  218. {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
  219. {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
  220. {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
  221. {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
  222. {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
  223. {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
  224. {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
  225. {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
  226. {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
  227. {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
  228. {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
  229. {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
  230. {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
  231. {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
  232. {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
  233. {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
  234. {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
  235. {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
  236. {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
  237. {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
  238. {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
  239. {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
  240. {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
  241. {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
  242. {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
  243. {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
  244. {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
  245. {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
  246. {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
  247. {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
  248. {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
  249. {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
  250. {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
  251. {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
  252. {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
  253. {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
  254. {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
  255. {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
  256. {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
  257. {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
  258. {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
  259. #define WCD934X_SLIM_TX_AIF_PATH(id) \
  260. {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
  261. {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
  262. {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
  263. {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
  264. enum {
  265. MIC_BIAS_1 = 1,
  266. MIC_BIAS_2,
  267. MIC_BIAS_3,
  268. MIC_BIAS_4
  269. };
  270. enum {
  271. SIDO_SOURCE_INTERNAL,
  272. SIDO_SOURCE_RCO_BG,
  273. };
  274. enum {
  275. INTERP_EAR = 0,
  276. INTERP_HPHL,
  277. INTERP_HPHR,
  278. INTERP_LO1,
  279. INTERP_LO2,
  280. INTERP_LO3_NA, /* LO3 not avalible in Tavil */
  281. INTERP_LO4_NA,
  282. INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
  283. INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
  284. INTERP_MAX,
  285. };
  286. enum {
  287. WCD934X_RX0 = 0,
  288. WCD934X_RX1,
  289. WCD934X_RX2,
  290. WCD934X_RX3,
  291. WCD934X_RX4,
  292. WCD934X_RX5,
  293. WCD934X_RX6,
  294. WCD934X_RX7,
  295. WCD934X_RX8,
  296. WCD934X_RX9,
  297. WCD934X_RX10,
  298. WCD934X_RX11,
  299. WCD934X_RX12,
  300. WCD934X_RX_MAX,
  301. };
  302. enum {
  303. WCD934X_TX0 = 0,
  304. WCD934X_TX1,
  305. WCD934X_TX2,
  306. WCD934X_TX3,
  307. WCD934X_TX4,
  308. WCD934X_TX5,
  309. WCD934X_TX6,
  310. WCD934X_TX7,
  311. WCD934X_TX8,
  312. WCD934X_TX9,
  313. WCD934X_TX10,
  314. WCD934X_TX11,
  315. WCD934X_TX12,
  316. WCD934X_TX13,
  317. WCD934X_TX14,
  318. WCD934X_TX15,
  319. WCD934X_TX_MAX,
  320. };
  321. struct wcd934x_slim_ch {
  322. u32 ch_num;
  323. u16 port;
  324. u16 shift;
  325. struct list_head list;
  326. };
  327. static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
  328. WCD934X_SLIM_TX_CH(0),
  329. WCD934X_SLIM_TX_CH(1),
  330. WCD934X_SLIM_TX_CH(2),
  331. WCD934X_SLIM_TX_CH(3),
  332. WCD934X_SLIM_TX_CH(4),
  333. WCD934X_SLIM_TX_CH(5),
  334. WCD934X_SLIM_TX_CH(6),
  335. WCD934X_SLIM_TX_CH(7),
  336. WCD934X_SLIM_TX_CH(8),
  337. WCD934X_SLIM_TX_CH(9),
  338. WCD934X_SLIM_TX_CH(10),
  339. WCD934X_SLIM_TX_CH(11),
  340. WCD934X_SLIM_TX_CH(12),
  341. WCD934X_SLIM_TX_CH(13),
  342. WCD934X_SLIM_TX_CH(14),
  343. WCD934X_SLIM_TX_CH(15),
  344. };
  345. static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
  346. WCD934X_SLIM_RX_CH(0), /* 16 */
  347. WCD934X_SLIM_RX_CH(1), /* 17 */
  348. WCD934X_SLIM_RX_CH(2),
  349. WCD934X_SLIM_RX_CH(3),
  350. WCD934X_SLIM_RX_CH(4),
  351. WCD934X_SLIM_RX_CH(5),
  352. WCD934X_SLIM_RX_CH(6),
  353. WCD934X_SLIM_RX_CH(7),
  354. WCD934X_SLIM_RX_CH(8),
  355. WCD934X_SLIM_RX_CH(9),
  356. WCD934X_SLIM_RX_CH(10),
  357. WCD934X_SLIM_RX_CH(11),
  358. WCD934X_SLIM_RX_CH(12),
  359. };
  360. /* Codec supports 2 IIR filters */
  361. enum {
  362. IIR0 = 0,
  363. IIR1,
  364. IIR_MAX,
  365. };
  366. /* Each IIR has 5 Filter Stages */
  367. enum {
  368. BAND1 = 0,
  369. BAND2,
  370. BAND3,
  371. BAND4,
  372. BAND5,
  373. BAND_MAX,
  374. };
  375. enum {
  376. COMPANDER_1, /* HPH_L */
  377. COMPANDER_2, /* HPH_R */
  378. COMPANDER_3, /* LO1_DIFF */
  379. COMPANDER_4, /* LO2_DIFF */
  380. COMPANDER_5, /* LO3_SE - not used in Tavil */
  381. COMPANDER_6, /* LO4_SE - not used in Tavil */
  382. COMPANDER_7, /* SWR SPK CH1 */
  383. COMPANDER_8, /* SWR SPK CH2 */
  384. COMPANDER_MAX,
  385. };
  386. enum {
  387. AIF1_PB = 0,
  388. AIF1_CAP,
  389. AIF2_PB,
  390. AIF2_CAP,
  391. AIF3_PB,
  392. AIF3_CAP,
  393. AIF4_PB,
  394. AIF4_VIFEED,
  395. AIF4_MAD_TX,
  396. NUM_CODEC_DAIS,
  397. };
  398. enum {
  399. INTn_1_INP_SEL_ZERO = 0,
  400. INTn_1_INP_SEL_DEC0,
  401. INTn_1_INP_SEL_DEC1,
  402. INTn_1_INP_SEL_IIR0,
  403. INTn_1_INP_SEL_IIR1,
  404. INTn_1_INP_SEL_RX0,
  405. INTn_1_INP_SEL_RX1,
  406. INTn_1_INP_SEL_RX2,
  407. INTn_1_INP_SEL_RX3,
  408. INTn_1_INP_SEL_RX4,
  409. INTn_1_INP_SEL_RX5,
  410. INTn_1_INP_SEL_RX6,
  411. INTn_1_INP_SEL_RX7,
  412. };
  413. enum {
  414. INTn_2_INP_SEL_ZERO = 0,
  415. INTn_2_INP_SEL_RX0,
  416. INTn_2_INP_SEL_RX1,
  417. INTn_2_INP_SEL_RX2,
  418. INTn_2_INP_SEL_RX3,
  419. INTn_2_INP_SEL_RX4,
  420. INTn_2_INP_SEL_RX5,
  421. INTn_2_INP_SEL_RX6,
  422. INTn_2_INP_SEL_RX7,
  423. INTn_2_INP_SEL_PROXIMITY,
  424. };
  425. enum {
  426. INTERP_MAIN_PATH,
  427. INTERP_MIX_PATH,
  428. };
  429. struct interp_sample_rate {
  430. int sample_rate;
  431. int rate_val;
  432. };
  433. static struct interp_sample_rate sr_val_tbl[] = {
  434. {8000, 0x0},
  435. {16000, 0x1},
  436. {32000, 0x3},
  437. {48000, 0x4},
  438. {96000, 0x5},
  439. {192000, 0x6},
  440. {384000, 0x7},
  441. {44100, 0x9},
  442. {88200, 0xA},
  443. {176400, 0xB},
  444. {352800, 0xC},
  445. };
  446. struct wcd_slim_codec_dai_data {
  447. struct list_head slim_ch_list;
  448. struct slim_stream_config sconfig;
  449. struct slim_stream_runtime *sruntime;
  450. };
  451. static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
  452. {
  453. .name = "WCD9335-IFC-DEV",
  454. .range_min = 0x0,
  455. .range_max = 0xffff,
  456. .selector_reg = 0x800,
  457. .selector_mask = 0xfff,
  458. .selector_shift = 0,
  459. .window_start = 0x800,
  460. .window_len = 0x400,
  461. },
  462. };
  463. static struct regmap_config wcd934x_ifc_regmap_config = {
  464. .reg_bits = 16,
  465. .val_bits = 8,
  466. .max_register = 0xffff,
  467. .ranges = wcd934x_ifc_ranges,
  468. .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
  469. };
  470. struct wcd934x_codec {
  471. struct device *dev;
  472. struct clk_hw hw;
  473. struct clk *extclk;
  474. struct regmap *regmap;
  475. struct regmap *if_regmap;
  476. struct slim_device *sdev;
  477. struct slim_device *sidev;
  478. struct wcd_clsh_ctrl *clsh_ctrl;
  479. struct snd_soc_component *component;
  480. struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
  481. struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
  482. struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
  483. int rate;
  484. u32 version;
  485. u32 hph_mode;
  486. int num_rx_port;
  487. int num_tx_port;
  488. u32 tx_port_value[WCD934X_TX_MAX];
  489. u32 rx_port_value[WCD934X_RX_MAX];
  490. int sido_input_src;
  491. int dmic_0_1_clk_cnt;
  492. int dmic_2_3_clk_cnt;
  493. int dmic_4_5_clk_cnt;
  494. int dmic_sample_rate;
  495. int comp_enabled[COMPANDER_MAX];
  496. int sysclk_users;
  497. struct mutex sysclk_mutex;
  498. };
  499. #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
  500. struct wcd_iir_filter_ctl {
  501. unsigned int iir_idx;
  502. unsigned int band_idx;
  503. struct soc_bytes_ext bytes_ext;
  504. };
  505. static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
  506. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  507. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  508. static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
  509. /* Cutoff frequency for high pass filter */
  510. static const char * const cf_text[] = {
  511. "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
  512. };
  513. static const char * const rx_cf_text[] = {
  514. "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
  515. "CF_NEG_3DB_0P48HZ"
  516. };
  517. static const char * const rx_hph_mode_mux_text[] = {
  518. "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
  519. "Class-H Hi-Fi Low Power"
  520. };
  521. static const char *const slim_rx_mux_text[] = {
  522. "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
  523. };
  524. static const char * const rx_int0_7_mix_mux_text[] = {
  525. "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
  526. "RX6", "RX7", "PROXIMITY"
  527. };
  528. static const char * const rx_int_mix_mux_text[] = {
  529. "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
  530. "RX6", "RX7"
  531. };
  532. static const char * const rx_prim_mix_text[] = {
  533. "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
  534. "RX3", "RX4", "RX5", "RX6", "RX7"
  535. };
  536. static const char * const rx_sidetone_mix_text[] = {
  537. "ZERO", "SRC0", "SRC1", "SRC_SUM"
  538. };
  539. static const char * const iir_inp_mux_text[] = {
  540. "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
  541. "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
  542. };
  543. static const char * const rx_int_dem_inp_mux_text[] = {
  544. "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
  545. };
  546. static const char * const rx_int0_1_interp_mux_text[] = {
  547. "ZERO", "RX INT0_1 MIX1",
  548. };
  549. static const char * const rx_int1_1_interp_mux_text[] = {
  550. "ZERO", "RX INT1_1 MIX1",
  551. };
  552. static const char * const rx_int2_1_interp_mux_text[] = {
  553. "ZERO", "RX INT2_1 MIX1",
  554. };
  555. static const char * const rx_int3_1_interp_mux_text[] = {
  556. "ZERO", "RX INT3_1 MIX1",
  557. };
  558. static const char * const rx_int4_1_interp_mux_text[] = {
  559. "ZERO", "RX INT4_1 MIX1",
  560. };
  561. static const char * const rx_int7_1_interp_mux_text[] = {
  562. "ZERO", "RX INT7_1 MIX1",
  563. };
  564. static const char * const rx_int8_1_interp_mux_text[] = {
  565. "ZERO", "RX INT8_1 MIX1",
  566. };
  567. static const char * const rx_int0_2_interp_mux_text[] = {
  568. "ZERO", "RX INT0_2 MUX",
  569. };
  570. static const char * const rx_int1_2_interp_mux_text[] = {
  571. "ZERO", "RX INT1_2 MUX",
  572. };
  573. static const char * const rx_int2_2_interp_mux_text[] = {
  574. "ZERO", "RX INT2_2 MUX",
  575. };
  576. static const char * const rx_int3_2_interp_mux_text[] = {
  577. "ZERO", "RX INT3_2 MUX",
  578. };
  579. static const char * const rx_int4_2_interp_mux_text[] = {
  580. "ZERO", "RX INT4_2 MUX",
  581. };
  582. static const char * const rx_int7_2_interp_mux_text[] = {
  583. "ZERO", "RX INT7_2 MUX",
  584. };
  585. static const char * const rx_int8_2_interp_mux_text[] = {
  586. "ZERO", "RX INT8_2 MUX",
  587. };
  588. static const char * const dmic_mux_text[] = {
  589. "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
  590. };
  591. static const char * const amic_mux_text[] = {
  592. "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
  593. };
  594. static const char * const amic4_5_sel_text[] = {
  595. "AMIC4", "AMIC5"
  596. };
  597. static const char * const adc_mux_text[] = {
  598. "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
  599. };
  600. static const char * const cdc_if_tx0_mux_text[] = {
  601. "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
  602. };
  603. static const char * const cdc_if_tx1_mux_text[] = {
  604. "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
  605. };
  606. static const char * const cdc_if_tx2_mux_text[] = {
  607. "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
  608. };
  609. static const char * const cdc_if_tx3_mux_text[] = {
  610. "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
  611. };
  612. static const char * const cdc_if_tx4_mux_text[] = {
  613. "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
  614. };
  615. static const char * const cdc_if_tx5_mux_text[] = {
  616. "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
  617. };
  618. static const char * const cdc_if_tx6_mux_text[] = {
  619. "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
  620. };
  621. static const char * const cdc_if_tx7_mux_text[] = {
  622. "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
  623. };
  624. static const char * const cdc_if_tx8_mux_text[] = {
  625. "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
  626. };
  627. static const char * const cdc_if_tx9_mux_text[] = {
  628. "ZERO", "DEC7", "DEC7_192"
  629. };
  630. static const char * const cdc_if_tx10_mux_text[] = {
  631. "ZERO", "DEC6", "DEC6_192"
  632. };
  633. static const char * const cdc_if_tx11_mux_text[] = {
  634. "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
  635. };
  636. static const char * const cdc_if_tx11_inp1_mux_text[] = {
  637. "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
  638. "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
  639. };
  640. static const char * const cdc_if_tx13_mux_text[] = {
  641. "CDC_DEC_5", "MAD_BRDCST"
  642. };
  643. static const char * const cdc_if_tx13_inp1_mux_text[] = {
  644. "ZERO", "DEC5", "DEC5_192"
  645. };
  646. static const struct soc_enum cf_dec0_enum =
  647. SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
  648. static const struct soc_enum cf_dec1_enum =
  649. SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
  650. static const struct soc_enum cf_dec2_enum =
  651. SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
  652. static const struct soc_enum cf_dec3_enum =
  653. SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
  654. static const struct soc_enum cf_dec4_enum =
  655. SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
  656. static const struct soc_enum cf_dec5_enum =
  657. SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
  658. static const struct soc_enum cf_dec6_enum =
  659. SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
  660. static const struct soc_enum cf_dec7_enum =
  661. SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
  662. static const struct soc_enum cf_dec8_enum =
  663. SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
  664. static const struct soc_enum cf_int0_1_enum =
  665. SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
  666. static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
  667. rx_cf_text);
  668. static const struct soc_enum cf_int1_1_enum =
  669. SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
  670. static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
  671. rx_cf_text);
  672. static const struct soc_enum cf_int2_1_enum =
  673. SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
  674. static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
  675. rx_cf_text);
  676. static const struct soc_enum cf_int3_1_enum =
  677. SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
  678. static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
  679. rx_cf_text);
  680. static const struct soc_enum cf_int4_1_enum =
  681. SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
  682. static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
  683. rx_cf_text);
  684. static const struct soc_enum cf_int7_1_enum =
  685. SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
  686. static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
  687. rx_cf_text);
  688. static const struct soc_enum cf_int8_1_enum =
  689. SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
  690. static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
  691. rx_cf_text);
  692. static const struct soc_enum rx_hph_mode_mux_enum =
  693. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  694. rx_hph_mode_mux_text);
  695. static const struct soc_enum slim_rx_mux_enum =
  696. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
  697. static const struct soc_enum rx_int0_2_mux_chain_enum =
  698. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
  699. rx_int0_7_mix_mux_text);
  700. static const struct soc_enum rx_int1_2_mux_chain_enum =
  701. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
  702. rx_int_mix_mux_text);
  703. static const struct soc_enum rx_int2_2_mux_chain_enum =
  704. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
  705. rx_int_mix_mux_text);
  706. static const struct soc_enum rx_int3_2_mux_chain_enum =
  707. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
  708. rx_int_mix_mux_text);
  709. static const struct soc_enum rx_int4_2_mux_chain_enum =
  710. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
  711. rx_int_mix_mux_text);
  712. static const struct soc_enum rx_int7_2_mux_chain_enum =
  713. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
  714. rx_int0_7_mix_mux_text);
  715. static const struct soc_enum rx_int8_2_mux_chain_enum =
  716. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
  717. rx_int_mix_mux_text);
  718. static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
  719. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
  720. rx_prim_mix_text);
  721. static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
  722. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
  723. rx_prim_mix_text);
  724. static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
  725. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
  726. rx_prim_mix_text);
  727. static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
  728. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
  729. rx_prim_mix_text);
  730. static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
  731. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
  732. rx_prim_mix_text);
  733. static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
  734. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
  735. rx_prim_mix_text);
  736. static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
  737. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
  738. rx_prim_mix_text);
  739. static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
  740. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
  741. rx_prim_mix_text);
  742. static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
  743. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
  744. rx_prim_mix_text);
  745. static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
  746. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
  747. rx_prim_mix_text);
  748. static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
  749. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
  750. rx_prim_mix_text);
  751. static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
  752. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
  753. rx_prim_mix_text);
  754. static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
  755. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
  756. rx_prim_mix_text);
  757. static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
  758. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
  759. rx_prim_mix_text);
  760. static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
  761. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
  762. rx_prim_mix_text);
  763. static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
  764. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
  765. rx_prim_mix_text);
  766. static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
  767. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
  768. rx_prim_mix_text);
  769. static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
  770. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
  771. rx_prim_mix_text);
  772. static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
  773. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
  774. rx_prim_mix_text);
  775. static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
  776. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
  777. rx_prim_mix_text);
  778. static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
  779. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
  780. rx_prim_mix_text);
  781. static const struct soc_enum rx_int0_mix2_inp_mux_enum =
  782. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
  783. rx_sidetone_mix_text);
  784. static const struct soc_enum rx_int1_mix2_inp_mux_enum =
  785. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
  786. rx_sidetone_mix_text);
  787. static const struct soc_enum rx_int2_mix2_inp_mux_enum =
  788. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
  789. rx_sidetone_mix_text);
  790. static const struct soc_enum rx_int3_mix2_inp_mux_enum =
  791. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
  792. rx_sidetone_mix_text);
  793. static const struct soc_enum rx_int4_mix2_inp_mux_enum =
  794. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
  795. rx_sidetone_mix_text);
  796. static const struct soc_enum rx_int7_mix2_inp_mux_enum =
  797. SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
  798. rx_sidetone_mix_text);
  799. static const struct soc_enum iir0_inp0_mux_enum =
  800. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
  801. 0, 18, iir_inp_mux_text);
  802. static const struct soc_enum iir0_inp1_mux_enum =
  803. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
  804. 0, 18, iir_inp_mux_text);
  805. static const struct soc_enum iir0_inp2_mux_enum =
  806. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
  807. 0, 18, iir_inp_mux_text);
  808. static const struct soc_enum iir0_inp3_mux_enum =
  809. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
  810. 0, 18, iir_inp_mux_text);
  811. static const struct soc_enum iir1_inp0_mux_enum =
  812. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
  813. 0, 18, iir_inp_mux_text);
  814. static const struct soc_enum iir1_inp1_mux_enum =
  815. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
  816. 0, 18, iir_inp_mux_text);
  817. static const struct soc_enum iir1_inp2_mux_enum =
  818. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
  819. 0, 18, iir_inp_mux_text);
  820. static const struct soc_enum iir1_inp3_mux_enum =
  821. SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
  822. 0, 18, iir_inp_mux_text);
  823. static const struct soc_enum rx_int0_dem_inp_mux_enum =
  824. SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
  825. ARRAY_SIZE(rx_int_dem_inp_mux_text),
  826. rx_int_dem_inp_mux_text);
  827. static const struct soc_enum rx_int1_dem_inp_mux_enum =
  828. SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
  829. ARRAY_SIZE(rx_int_dem_inp_mux_text),
  830. rx_int_dem_inp_mux_text);
  831. static const struct soc_enum rx_int2_dem_inp_mux_enum =
  832. SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
  833. ARRAY_SIZE(rx_int_dem_inp_mux_text),
  834. rx_int_dem_inp_mux_text);
  835. static const struct soc_enum tx_adc_mux0_enum =
  836. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
  837. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  838. static const struct soc_enum tx_adc_mux1_enum =
  839. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
  840. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  841. static const struct soc_enum tx_adc_mux2_enum =
  842. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
  843. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  844. static const struct soc_enum tx_adc_mux3_enum =
  845. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
  846. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  847. static const struct soc_enum tx_adc_mux4_enum =
  848. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
  849. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  850. static const struct soc_enum tx_adc_mux5_enum =
  851. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
  852. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  853. static const struct soc_enum tx_adc_mux6_enum =
  854. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
  855. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  856. static const struct soc_enum tx_adc_mux7_enum =
  857. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
  858. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  859. static const struct soc_enum tx_adc_mux8_enum =
  860. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
  861. ARRAY_SIZE(adc_mux_text), adc_mux_text);
  862. static const struct soc_enum rx_int0_1_interp_mux_enum =
  863. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
  864. rx_int0_1_interp_mux_text);
  865. static const struct soc_enum rx_int1_1_interp_mux_enum =
  866. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
  867. rx_int1_1_interp_mux_text);
  868. static const struct soc_enum rx_int2_1_interp_mux_enum =
  869. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
  870. rx_int2_1_interp_mux_text);
  871. static const struct soc_enum rx_int3_1_interp_mux_enum =
  872. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
  873. static const struct soc_enum rx_int4_1_interp_mux_enum =
  874. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
  875. static const struct soc_enum rx_int7_1_interp_mux_enum =
  876. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
  877. static const struct soc_enum rx_int8_1_interp_mux_enum =
  878. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
  879. static const struct soc_enum rx_int0_2_interp_mux_enum =
  880. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
  881. static const struct soc_enum rx_int1_2_interp_mux_enum =
  882. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
  883. static const struct soc_enum rx_int2_2_interp_mux_enum =
  884. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
  885. static const struct soc_enum rx_int3_2_interp_mux_enum =
  886. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
  887. static const struct soc_enum rx_int4_2_interp_mux_enum =
  888. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
  889. static const struct soc_enum rx_int7_2_interp_mux_enum =
  890. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
  891. static const struct soc_enum rx_int8_2_interp_mux_enum =
  892. SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
  893. static const struct soc_enum tx_dmic_mux0_enum =
  894. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
  895. dmic_mux_text);
  896. static const struct soc_enum tx_dmic_mux1_enum =
  897. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
  898. dmic_mux_text);
  899. static const struct soc_enum tx_dmic_mux2_enum =
  900. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
  901. dmic_mux_text);
  902. static const struct soc_enum tx_dmic_mux3_enum =
  903. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
  904. dmic_mux_text);
  905. static const struct soc_enum tx_dmic_mux4_enum =
  906. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
  907. dmic_mux_text);
  908. static const struct soc_enum tx_dmic_mux5_enum =
  909. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
  910. dmic_mux_text);
  911. static const struct soc_enum tx_dmic_mux6_enum =
  912. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
  913. dmic_mux_text);
  914. static const struct soc_enum tx_dmic_mux7_enum =
  915. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
  916. dmic_mux_text);
  917. static const struct soc_enum tx_dmic_mux8_enum =
  918. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
  919. dmic_mux_text);
  920. static const struct soc_enum tx_amic_mux0_enum =
  921. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
  922. amic_mux_text);
  923. static const struct soc_enum tx_amic_mux1_enum =
  924. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
  925. amic_mux_text);
  926. static const struct soc_enum tx_amic_mux2_enum =
  927. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
  928. amic_mux_text);
  929. static const struct soc_enum tx_amic_mux3_enum =
  930. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
  931. amic_mux_text);
  932. static const struct soc_enum tx_amic_mux4_enum =
  933. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
  934. amic_mux_text);
  935. static const struct soc_enum tx_amic_mux5_enum =
  936. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
  937. amic_mux_text);
  938. static const struct soc_enum tx_amic_mux6_enum =
  939. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
  940. amic_mux_text);
  941. static const struct soc_enum tx_amic_mux7_enum =
  942. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
  943. amic_mux_text);
  944. static const struct soc_enum tx_amic_mux8_enum =
  945. SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
  946. amic_mux_text);
  947. static const struct soc_enum tx_amic4_5_enum =
  948. SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
  949. static const struct soc_enum cdc_if_tx0_mux_enum =
  950. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
  951. ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
  952. static const struct soc_enum cdc_if_tx1_mux_enum =
  953. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
  954. ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
  955. static const struct soc_enum cdc_if_tx2_mux_enum =
  956. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
  957. ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
  958. static const struct soc_enum cdc_if_tx3_mux_enum =
  959. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
  960. ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
  961. static const struct soc_enum cdc_if_tx4_mux_enum =
  962. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
  963. ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
  964. static const struct soc_enum cdc_if_tx5_mux_enum =
  965. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
  966. ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
  967. static const struct soc_enum cdc_if_tx6_mux_enum =
  968. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
  969. ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
  970. static const struct soc_enum cdc_if_tx7_mux_enum =
  971. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
  972. ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
  973. static const struct soc_enum cdc_if_tx8_mux_enum =
  974. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
  975. ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
  976. static const struct soc_enum cdc_if_tx9_mux_enum =
  977. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
  978. ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
  979. static const struct soc_enum cdc_if_tx10_mux_enum =
  980. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
  981. ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
  982. static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
  983. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
  984. ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
  985. cdc_if_tx11_inp1_mux_text);
  986. static const struct soc_enum cdc_if_tx11_mux_enum =
  987. SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
  988. ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
  989. static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
  990. SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
  991. ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
  992. cdc_if_tx13_inp1_mux_text);
  993. static const struct soc_enum cdc_if_tx13_mux_enum =
  994. SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
  995. ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
  996. static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
  997. {
  998. if (sido_src == wcd->sido_input_src)
  999. return 0;
  1000. if (sido_src == SIDO_SOURCE_RCO_BG) {
  1001. regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
  1002. WCD934X_ANA_RCO_BG_EN_MASK,
  1003. WCD934X_ANA_RCO_BG_ENABLE);
  1004. usleep_range(100, 110);
  1005. }
  1006. wcd->sido_input_src = sido_src;
  1007. return 0;
  1008. }
  1009. static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
  1010. {
  1011. mutex_lock(&wcd->sysclk_mutex);
  1012. if (++wcd->sysclk_users != 1) {
  1013. mutex_unlock(&wcd->sysclk_mutex);
  1014. return 0;
  1015. }
  1016. mutex_unlock(&wcd->sysclk_mutex);
  1017. regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
  1018. WCD934X_ANA_BIAS_EN_MASK,
  1019. WCD934X_ANA_BIAS_EN);
  1020. regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
  1021. WCD934X_ANA_PRECHRG_EN_MASK,
  1022. WCD934X_ANA_PRECHRG_EN);
  1023. /*
  1024. * 1ms delay is required after pre-charge is enabled
  1025. * as per HW requirement
  1026. */
  1027. usleep_range(1000, 1100);
  1028. regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
  1029. WCD934X_ANA_PRECHRG_EN_MASK, 0);
  1030. regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
  1031. WCD934X_ANA_PRECHRG_MODE_MASK, 0);
  1032. /*
  1033. * In data clock contrl register is changed
  1034. * to CLK_SYS_MCLK_PRG
  1035. */
  1036. regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
  1037. WCD934X_EXT_CLK_BUF_EN_MASK,
  1038. WCD934X_EXT_CLK_BUF_EN);
  1039. regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
  1040. WCD934X_EXT_CLK_DIV_RATIO_MASK,
  1041. WCD934X_EXT_CLK_DIV_BY_2);
  1042. regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
  1043. WCD934X_MCLK_SRC_MASK,
  1044. WCD934X_MCLK_SRC_EXT_CLK);
  1045. regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
  1046. WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
  1047. regmap_update_bits(wcd->regmap,
  1048. WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
  1049. WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
  1050. WCD934X_CDC_FS_MCLK_CNT_ENABLE);
  1051. regmap_update_bits(wcd->regmap,
  1052. WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
  1053. WCD934X_MCLK_EN_MASK,
  1054. WCD934X_MCLK_EN);
  1055. regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
  1056. WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
  1057. /*
  1058. * 10us sleep is required after clock is enabled
  1059. * as per HW requirement
  1060. */
  1061. usleep_range(10, 15);
  1062. wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
  1063. return 0;
  1064. }
  1065. static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
  1066. {
  1067. mutex_lock(&wcd->sysclk_mutex);
  1068. if (--wcd->sysclk_users != 0) {
  1069. mutex_unlock(&wcd->sysclk_mutex);
  1070. return 0;
  1071. }
  1072. mutex_unlock(&wcd->sysclk_mutex);
  1073. regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
  1074. WCD934X_EXT_CLK_BUF_EN_MASK |
  1075. WCD934X_MCLK_EN_MASK, 0x0);
  1076. regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
  1077. WCD934X_ANA_BIAS_EN_MASK, 0);
  1078. regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
  1079. WCD934X_ANA_PRECHRG_EN_MASK, 0);
  1080. return 0;
  1081. }
  1082. static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
  1083. {
  1084. int ret = 0;
  1085. if (enable) {
  1086. ret = clk_prepare_enable(wcd->extclk);
  1087. if (ret) {
  1088. dev_err(wcd->dev, "%s: ext clk enable failed\n",
  1089. __func__);
  1090. return ret;
  1091. }
  1092. ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
  1093. } else {
  1094. int val;
  1095. regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
  1096. &val);
  1097. /* Don't disable clock if soundwire using it.*/
  1098. if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
  1099. return 0;
  1100. wcd934x_disable_ana_bias_and_syclk(wcd);
  1101. clk_disable_unprepare(wcd->extclk);
  1102. }
  1103. return ret;
  1104. }
  1105. static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
  1106. struct snd_kcontrol *kc, int event)
  1107. {
  1108. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  1109. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  1110. switch (event) {
  1111. case SND_SOC_DAPM_PRE_PMU:
  1112. return __wcd934x_cdc_mclk_enable(wcd, true);
  1113. case SND_SOC_DAPM_POST_PMD:
  1114. return __wcd934x_cdc_mclk_enable(wcd, false);
  1115. }
  1116. return 0;
  1117. }
  1118. static int wcd934x_get_version(struct wcd934x_codec *wcd)
  1119. {
  1120. int val1, val2, ver, ret;
  1121. struct regmap *regmap;
  1122. u16 id_minor;
  1123. u32 version_mask = 0;
  1124. regmap = wcd->regmap;
  1125. ver = 0;
  1126. ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
  1127. (u8 *)&id_minor, sizeof(u16));
  1128. if (ret)
  1129. return ret;
  1130. regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
  1131. regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
  1132. version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
  1133. version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
  1134. switch (version_mask) {
  1135. case DSD_DISABLED | SLNQ_DISABLED:
  1136. if (id_minor == 0)
  1137. ver = WCD_VERSION_WCD9340_1_0;
  1138. else if (id_minor == 0x01)
  1139. ver = WCD_VERSION_WCD9340_1_1;
  1140. break;
  1141. case SLNQ_DISABLED:
  1142. if (id_minor == 0)
  1143. ver = WCD_VERSION_WCD9341_1_0;
  1144. else if (id_minor == 0x01)
  1145. ver = WCD_VERSION_WCD9341_1_1;
  1146. break;
  1147. }
  1148. wcd->version = ver;
  1149. dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
  1150. return 0;
  1151. }
  1152. static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
  1153. {
  1154. int rc, val;
  1155. __wcd934x_cdc_mclk_enable(wcd, true);
  1156. regmap_update_bits(wcd->regmap,
  1157. WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
  1158. WCD934X_EFUSE_SENSE_STATE_MASK,
  1159. WCD934X_EFUSE_SENSE_STATE_DEF);
  1160. regmap_update_bits(wcd->regmap,
  1161. WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
  1162. WCD934X_EFUSE_SENSE_EN_MASK,
  1163. WCD934X_EFUSE_SENSE_ENABLE);
  1164. /*
  1165. * 5ms sleep required after enabling efuse control
  1166. * before checking the status.
  1167. */
  1168. usleep_range(5000, 5500);
  1169. wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
  1170. rc = regmap_read(wcd->regmap,
  1171. WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
  1172. if (rc || (!(val & 0x01)))
  1173. WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
  1174. __func__, val, rc);
  1175. __wcd934x_cdc_mclk_enable(wcd, false);
  1176. }
  1177. static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
  1178. {
  1179. if (enable) {
  1180. __wcd934x_cdc_mclk_enable(wcd, true);
  1181. regmap_update_bits(wcd->regmap,
  1182. WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
  1183. WCD934X_CDC_SWR_CLK_EN_MASK,
  1184. WCD934X_CDC_SWR_CLK_ENABLE);
  1185. } else {
  1186. regmap_update_bits(wcd->regmap,
  1187. WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
  1188. WCD934X_CDC_SWR_CLK_EN_MASK, 0);
  1189. __wcd934x_cdc_mclk_enable(wcd, false);
  1190. }
  1191. return 0;
  1192. }
  1193. static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
  1194. u8 rate_val, u32 rate)
  1195. {
  1196. struct snd_soc_component *comp = dai->component;
  1197. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  1198. struct wcd934x_slim_ch *ch;
  1199. u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
  1200. int inp, j;
  1201. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
  1202. inp = ch->shift + INTn_1_INP_SEL_RX0;
  1203. /*
  1204. * Loop through all interpolator MUX inputs and find out
  1205. * to which interpolator input, the slim rx port
  1206. * is connected
  1207. */
  1208. for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
  1209. /* Interpolators 5 and 6 are not aviliable in Tavil */
  1210. if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
  1211. continue;
  1212. cfg0 = snd_soc_component_read(comp,
  1213. WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
  1214. cfg1 = snd_soc_component_read(comp,
  1215. WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
  1216. inp0_sel = cfg0 &
  1217. WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1218. inp1_sel = (cfg0 >> 4) &
  1219. WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1220. inp2_sel = (cfg1 >> 4) &
  1221. WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1222. if ((inp0_sel == inp) || (inp1_sel == inp) ||
  1223. (inp2_sel == inp)) {
  1224. /* rate is in Hz */
  1225. /*
  1226. * Ear and speaker primary path does not support
  1227. * native sample rates
  1228. */
  1229. if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
  1230. j == INTERP_SPKR2) && rate == 44100)
  1231. dev_err(wcd->dev,
  1232. "Cannot set 44.1KHz on INT%d\n",
  1233. j);
  1234. else
  1235. snd_soc_component_update_bits(comp,
  1236. WCD934X_CDC_RX_PATH_CTL(j),
  1237. WCD934X_CDC_MIX_PCM_RATE_MASK,
  1238. rate_val);
  1239. }
  1240. }
  1241. }
  1242. return 0;
  1243. }
  1244. static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
  1245. int rate_val, u32 rate)
  1246. {
  1247. struct snd_soc_component *component = dai->component;
  1248. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  1249. struct wcd934x_slim_ch *ch;
  1250. int val, j;
  1251. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
  1252. for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
  1253. /* Interpolators 5 and 6 are not aviliable in Tavil */
  1254. if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
  1255. continue;
  1256. val = snd_soc_component_read(component,
  1257. WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
  1258. WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
  1259. if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
  1260. /*
  1261. * Ear mix path supports only 48, 96, 192,
  1262. * 384KHz only
  1263. */
  1264. if ((j == INTERP_EAR) &&
  1265. (rate_val < 0x4 ||
  1266. rate_val > 0x7)) {
  1267. dev_err(component->dev,
  1268. "Invalid rate for AIF_PB DAI(%d)\n",
  1269. dai->id);
  1270. return -EINVAL;
  1271. }
  1272. snd_soc_component_update_bits(component,
  1273. WCD934X_CDC_RX_PATH_MIX_CTL(j),
  1274. WCD934X_CDC_MIX_PCM_RATE_MASK,
  1275. rate_val);
  1276. }
  1277. }
  1278. }
  1279. return 0;
  1280. }
  1281. static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
  1282. u32 sample_rate)
  1283. {
  1284. int rate_val = 0;
  1285. int i, ret;
  1286. for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
  1287. if (sample_rate == sr_val_tbl[i].sample_rate) {
  1288. rate_val = sr_val_tbl[i].rate_val;
  1289. break;
  1290. }
  1291. }
  1292. if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
  1293. dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
  1294. return -EINVAL;
  1295. }
  1296. ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
  1297. sample_rate);
  1298. if (ret)
  1299. return ret;
  1300. ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
  1301. sample_rate);
  1302. if (ret)
  1303. return ret;
  1304. return ret;
  1305. }
  1306. static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
  1307. u8 rate_val, u32 rate)
  1308. {
  1309. struct snd_soc_component *comp = dai->component;
  1310. struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
  1311. u8 shift = 0, shift_val = 0, tx_mux_sel;
  1312. struct wcd934x_slim_ch *ch;
  1313. int tx_port, tx_port_reg;
  1314. int decimator = -1;
  1315. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
  1316. tx_port = ch->port;
  1317. /* Find the SB TX MUX input - which decimator is connected */
  1318. switch (tx_port) {
  1319. case 0 ... 3:
  1320. tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
  1321. shift = (tx_port << 1);
  1322. shift_val = 0x03;
  1323. break;
  1324. case 4 ... 7:
  1325. tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
  1326. shift = ((tx_port - 4) << 1);
  1327. shift_val = 0x03;
  1328. break;
  1329. case 8 ... 10:
  1330. tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
  1331. shift = ((tx_port - 8) << 1);
  1332. shift_val = 0x03;
  1333. break;
  1334. case 11:
  1335. tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
  1336. shift = 0;
  1337. shift_val = 0x0F;
  1338. break;
  1339. case 13:
  1340. tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
  1341. shift = 4;
  1342. shift_val = 0x03;
  1343. break;
  1344. default:
  1345. dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
  1346. tx_port, dai->id);
  1347. return -EINVAL;
  1348. }
  1349. tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
  1350. (shift_val << shift);
  1351. tx_mux_sel = tx_mux_sel >> shift;
  1352. switch (tx_port) {
  1353. case 0 ... 8:
  1354. if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
  1355. decimator = tx_port;
  1356. break;
  1357. case 9 ... 10:
  1358. if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
  1359. decimator = ((tx_port == 9) ? 7 : 6);
  1360. break;
  1361. case 11:
  1362. if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
  1363. decimator = tx_mux_sel - 1;
  1364. break;
  1365. case 13:
  1366. if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
  1367. decimator = 5;
  1368. break;
  1369. default:
  1370. dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
  1371. tx_port);
  1372. return -EINVAL;
  1373. }
  1374. snd_soc_component_update_bits(comp,
  1375. WCD934X_CDC_TX_PATH_CTL(decimator),
  1376. WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
  1377. rate_val);
  1378. }
  1379. return 0;
  1380. }
  1381. static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
  1382. struct wcd_slim_codec_dai_data *dai_data,
  1383. int direction)
  1384. {
  1385. struct list_head *slim_ch_list = &dai_data->slim_ch_list;
  1386. struct slim_stream_config *cfg = &dai_data->sconfig;
  1387. struct wcd934x_slim_ch *ch;
  1388. u16 payload = 0;
  1389. int ret, i;
  1390. cfg->ch_count = 0;
  1391. cfg->direction = direction;
  1392. cfg->port_mask = 0;
  1393. /* Configure slave interface device */
  1394. list_for_each_entry(ch, slim_ch_list, list) {
  1395. cfg->ch_count++;
  1396. payload |= 1 << ch->shift;
  1397. cfg->port_mask |= BIT(ch->port);
  1398. }
  1399. cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
  1400. if (!cfg->chs)
  1401. return -ENOMEM;
  1402. i = 0;
  1403. list_for_each_entry(ch, slim_ch_list, list) {
  1404. cfg->chs[i++] = ch->ch_num;
  1405. if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
  1406. /* write to interface device */
  1407. ret = regmap_write(wcd->if_regmap,
  1408. WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
  1409. payload);
  1410. if (ret < 0)
  1411. goto err;
  1412. /* configure the slave port for water mark and enable*/
  1413. ret = regmap_write(wcd->if_regmap,
  1414. WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
  1415. WCD934X_SLIM_WATER_MARK_VAL);
  1416. if (ret < 0)
  1417. goto err;
  1418. } else {
  1419. ret = regmap_write(wcd->if_regmap,
  1420. WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
  1421. payload & 0x00FF);
  1422. if (ret < 0)
  1423. goto err;
  1424. /* ports 8,9 */
  1425. ret = regmap_write(wcd->if_regmap,
  1426. WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
  1427. (payload & 0xFF00) >> 8);
  1428. if (ret < 0)
  1429. goto err;
  1430. /* configure the slave port for water mark and enable*/
  1431. ret = regmap_write(wcd->if_regmap,
  1432. WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
  1433. WCD934X_SLIM_WATER_MARK_VAL);
  1434. if (ret < 0)
  1435. goto err;
  1436. }
  1437. }
  1438. dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
  1439. return 0;
  1440. err:
  1441. dev_err(wcd->dev, "Error Setting slim hw params\n");
  1442. kfree(cfg->chs);
  1443. cfg->chs = NULL;
  1444. return ret;
  1445. }
  1446. static int wcd934x_hw_params(struct snd_pcm_substream *substream,
  1447. struct snd_pcm_hw_params *params,
  1448. struct snd_soc_dai *dai)
  1449. {
  1450. struct wcd934x_codec *wcd;
  1451. int ret, tx_fs_rate = 0;
  1452. wcd = snd_soc_component_get_drvdata(dai->component);
  1453. switch (substream->stream) {
  1454. case SNDRV_PCM_STREAM_PLAYBACK:
  1455. ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
  1456. if (ret) {
  1457. dev_err(wcd->dev, "cannot set sample rate: %u\n",
  1458. params_rate(params));
  1459. return ret;
  1460. }
  1461. switch (params_width(params)) {
  1462. case 16 ... 24:
  1463. wcd->dai[dai->id].sconfig.bps = params_width(params);
  1464. break;
  1465. default:
  1466. dev_err(wcd->dev, "Invalid format 0x%x\n",
  1467. params_width(params));
  1468. return -EINVAL;
  1469. }
  1470. break;
  1471. case SNDRV_PCM_STREAM_CAPTURE:
  1472. switch (params_rate(params)) {
  1473. case 8000:
  1474. tx_fs_rate = 0;
  1475. break;
  1476. case 16000:
  1477. tx_fs_rate = 1;
  1478. break;
  1479. case 32000:
  1480. tx_fs_rate = 3;
  1481. break;
  1482. case 48000:
  1483. tx_fs_rate = 4;
  1484. break;
  1485. case 96000:
  1486. tx_fs_rate = 5;
  1487. break;
  1488. case 192000:
  1489. tx_fs_rate = 6;
  1490. break;
  1491. case 384000:
  1492. tx_fs_rate = 7;
  1493. break;
  1494. default:
  1495. dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
  1496. params_rate(params));
  1497. return -EINVAL;
  1498. }
  1499. ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
  1500. params_rate(params));
  1501. if (ret < 0) {
  1502. dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
  1503. return ret;
  1504. }
  1505. switch (params_width(params)) {
  1506. case 16 ... 32:
  1507. wcd->dai[dai->id].sconfig.bps = params_width(params);
  1508. break;
  1509. default:
  1510. dev_err(wcd->dev, "Invalid format 0x%x\n",
  1511. params_width(params));
  1512. return -EINVAL;
  1513. }
  1514. break;
  1515. default:
  1516. dev_err(wcd->dev, "Invalid stream type %d\n",
  1517. substream->stream);
  1518. return -EINVAL;
  1519. }
  1520. wcd->dai[dai->id].sconfig.rate = params_rate(params);
  1521. return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
  1522. }
  1523. static int wcd934x_hw_free(struct snd_pcm_substream *substream,
  1524. struct snd_soc_dai *dai)
  1525. {
  1526. struct wcd_slim_codec_dai_data *dai_data;
  1527. struct wcd934x_codec *wcd;
  1528. wcd = snd_soc_component_get_drvdata(dai->component);
  1529. dai_data = &wcd->dai[dai->id];
  1530. kfree(dai_data->sconfig.chs);
  1531. return 0;
  1532. }
  1533. static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
  1534. struct snd_soc_dai *dai)
  1535. {
  1536. struct wcd_slim_codec_dai_data *dai_data;
  1537. struct wcd934x_codec *wcd;
  1538. struct slim_stream_config *cfg;
  1539. wcd = snd_soc_component_get_drvdata(dai->component);
  1540. dai_data = &wcd->dai[dai->id];
  1541. switch (cmd) {
  1542. case SNDRV_PCM_TRIGGER_START:
  1543. case SNDRV_PCM_TRIGGER_RESUME:
  1544. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1545. cfg = &dai_data->sconfig;
  1546. slim_stream_prepare(dai_data->sruntime, cfg);
  1547. slim_stream_enable(dai_data->sruntime);
  1548. break;
  1549. case SNDRV_PCM_TRIGGER_STOP:
  1550. case SNDRV_PCM_TRIGGER_SUSPEND:
  1551. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1552. slim_stream_unprepare(dai_data->sruntime);
  1553. slim_stream_disable(dai_data->sruntime);
  1554. break;
  1555. default:
  1556. break;
  1557. }
  1558. return 0;
  1559. }
  1560. static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
  1561. unsigned int tx_num, unsigned int *tx_slot,
  1562. unsigned int rx_num, unsigned int *rx_slot)
  1563. {
  1564. struct wcd934x_codec *wcd;
  1565. int i;
  1566. wcd = snd_soc_component_get_drvdata(dai->component);
  1567. if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
  1568. dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
  1569. tx_num, rx_num);
  1570. return -EINVAL;
  1571. }
  1572. if (!tx_slot || !rx_slot) {
  1573. dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
  1574. tx_slot, rx_slot);
  1575. return -EINVAL;
  1576. }
  1577. wcd->num_rx_port = rx_num;
  1578. for (i = 0; i < rx_num; i++) {
  1579. wcd->rx_chs[i].ch_num = rx_slot[i];
  1580. INIT_LIST_HEAD(&wcd->rx_chs[i].list);
  1581. }
  1582. wcd->num_tx_port = tx_num;
  1583. for (i = 0; i < tx_num; i++) {
  1584. wcd->tx_chs[i].ch_num = tx_slot[i];
  1585. INIT_LIST_HEAD(&wcd->tx_chs[i].list);
  1586. }
  1587. return 0;
  1588. }
  1589. static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
  1590. unsigned int *tx_num, unsigned int *tx_slot,
  1591. unsigned int *rx_num, unsigned int *rx_slot)
  1592. {
  1593. struct wcd934x_slim_ch *ch;
  1594. struct wcd934x_codec *wcd;
  1595. int i = 0;
  1596. wcd = snd_soc_component_get_drvdata(dai->component);
  1597. switch (dai->id) {
  1598. case AIF1_PB:
  1599. case AIF2_PB:
  1600. case AIF3_PB:
  1601. case AIF4_PB:
  1602. if (!rx_slot || !rx_num) {
  1603. dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
  1604. rx_slot, rx_num);
  1605. return -EINVAL;
  1606. }
  1607. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
  1608. rx_slot[i++] = ch->ch_num;
  1609. *rx_num = i;
  1610. break;
  1611. case AIF1_CAP:
  1612. case AIF2_CAP:
  1613. case AIF3_CAP:
  1614. if (!tx_slot || !tx_num) {
  1615. dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
  1616. tx_slot, tx_num);
  1617. return -EINVAL;
  1618. }
  1619. list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
  1620. tx_slot[i++] = ch->ch_num;
  1621. *tx_num = i;
  1622. break;
  1623. default:
  1624. dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
  1625. break;
  1626. }
  1627. return 0;
  1628. }
  1629. static struct snd_soc_dai_ops wcd934x_dai_ops = {
  1630. .hw_params = wcd934x_hw_params,
  1631. .hw_free = wcd934x_hw_free,
  1632. .trigger = wcd934x_trigger,
  1633. .set_channel_map = wcd934x_set_channel_map,
  1634. .get_channel_map = wcd934x_get_channel_map,
  1635. };
  1636. static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
  1637. [0] = {
  1638. .name = "wcd934x_rx1",
  1639. .id = AIF1_PB,
  1640. .playback = {
  1641. .stream_name = "AIF1 Playback",
  1642. .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
  1643. .formats = WCD934X_FORMATS_S16_S24_LE,
  1644. .rate_max = 192000,
  1645. .rate_min = 8000,
  1646. .channels_min = 1,
  1647. .channels_max = 2,
  1648. },
  1649. .ops = &wcd934x_dai_ops,
  1650. },
  1651. [1] = {
  1652. .name = "wcd934x_tx1",
  1653. .id = AIF1_CAP,
  1654. .capture = {
  1655. .stream_name = "AIF1 Capture",
  1656. .rates = WCD934X_RATES_MASK,
  1657. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1658. .rate_min = 8000,
  1659. .rate_max = 192000,
  1660. .channels_min = 1,
  1661. .channels_max = 4,
  1662. },
  1663. .ops = &wcd934x_dai_ops,
  1664. },
  1665. [2] = {
  1666. .name = "wcd934x_rx2",
  1667. .id = AIF2_PB,
  1668. .playback = {
  1669. .stream_name = "AIF2 Playback",
  1670. .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
  1671. .formats = WCD934X_FORMATS_S16_S24_LE,
  1672. .rate_min = 8000,
  1673. .rate_max = 192000,
  1674. .channels_min = 1,
  1675. .channels_max = 2,
  1676. },
  1677. .ops = &wcd934x_dai_ops,
  1678. },
  1679. [3] = {
  1680. .name = "wcd934x_tx2",
  1681. .id = AIF2_CAP,
  1682. .capture = {
  1683. .stream_name = "AIF2 Capture",
  1684. .rates = WCD934X_RATES_MASK,
  1685. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1686. .rate_min = 8000,
  1687. .rate_max = 192000,
  1688. .channels_min = 1,
  1689. .channels_max = 4,
  1690. },
  1691. .ops = &wcd934x_dai_ops,
  1692. },
  1693. [4] = {
  1694. .name = "wcd934x_rx3",
  1695. .id = AIF3_PB,
  1696. .playback = {
  1697. .stream_name = "AIF3 Playback",
  1698. .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
  1699. .formats = WCD934X_FORMATS_S16_S24_LE,
  1700. .rate_min = 8000,
  1701. .rate_max = 192000,
  1702. .channels_min = 1,
  1703. .channels_max = 2,
  1704. },
  1705. .ops = &wcd934x_dai_ops,
  1706. },
  1707. [5] = {
  1708. .name = "wcd934x_tx3",
  1709. .id = AIF3_CAP,
  1710. .capture = {
  1711. .stream_name = "AIF3 Capture",
  1712. .rates = WCD934X_RATES_MASK,
  1713. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1714. .rate_min = 8000,
  1715. .rate_max = 192000,
  1716. .channels_min = 1,
  1717. .channels_max = 4,
  1718. },
  1719. .ops = &wcd934x_dai_ops,
  1720. },
  1721. [6] = {
  1722. .name = "wcd934x_rx4",
  1723. .id = AIF4_PB,
  1724. .playback = {
  1725. .stream_name = "AIF4 Playback",
  1726. .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
  1727. .formats = WCD934X_FORMATS_S16_S24_LE,
  1728. .rate_min = 8000,
  1729. .rate_max = 192000,
  1730. .channels_min = 1,
  1731. .channels_max = 2,
  1732. },
  1733. .ops = &wcd934x_dai_ops,
  1734. },
  1735. };
  1736. static int swclk_gate_enable(struct clk_hw *hw)
  1737. {
  1738. return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
  1739. }
  1740. static void swclk_gate_disable(struct clk_hw *hw)
  1741. {
  1742. wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
  1743. }
  1744. static int swclk_gate_is_enabled(struct clk_hw *hw)
  1745. {
  1746. struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
  1747. int ret, val;
  1748. regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
  1749. ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
  1750. return ret;
  1751. }
  1752. static unsigned long swclk_recalc_rate(struct clk_hw *hw,
  1753. unsigned long parent_rate)
  1754. {
  1755. return parent_rate / 2;
  1756. }
  1757. static const struct clk_ops swclk_gate_ops = {
  1758. .prepare = swclk_gate_enable,
  1759. .unprepare = swclk_gate_disable,
  1760. .is_enabled = swclk_gate_is_enabled,
  1761. .recalc_rate = swclk_recalc_rate,
  1762. };
  1763. static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
  1764. {
  1765. struct clk *parent = wcd->extclk;
  1766. struct device *dev = wcd->dev;
  1767. struct device_node *np = dev->parent->of_node;
  1768. const char *parent_clk_name = NULL;
  1769. const char *clk_name = "mclk";
  1770. struct clk_hw *hw;
  1771. struct clk_init_data init;
  1772. int ret;
  1773. if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
  1774. return NULL;
  1775. parent_clk_name = __clk_get_name(parent);
  1776. of_property_read_string(np, "clock-output-names", &clk_name);
  1777. init.name = clk_name;
  1778. init.ops = &swclk_gate_ops;
  1779. init.flags = 0;
  1780. init.parent_names = &parent_clk_name;
  1781. init.num_parents = 1;
  1782. wcd->hw.init = &init;
  1783. hw = &wcd->hw;
  1784. ret = clk_hw_register(wcd->dev->parent, hw);
  1785. if (ret)
  1786. return ERR_PTR(ret);
  1787. of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
  1788. return NULL;
  1789. }
  1790. static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
  1791. {
  1792. int mv;
  1793. if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
  1794. dev_err(dev, "%s value not found, using default\n", micbias);
  1795. mv = WCD934X_DEF_MICBIAS_MV;
  1796. } else {
  1797. /* convert it to milli volts */
  1798. mv = mv/1000;
  1799. }
  1800. if (mv < 1000 || mv > 2850) {
  1801. dev_err(dev, "%s value not in valid range, using default\n",
  1802. micbias);
  1803. mv = WCD934X_DEF_MICBIAS_MV;
  1804. }
  1805. return (mv - 1000) / 50;
  1806. }
  1807. static int wcd934x_init_dmic(struct snd_soc_component *comp)
  1808. {
  1809. int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
  1810. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  1811. u32 def_dmic_rate, dmic_clk_drv;
  1812. vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
  1813. "qcom,micbias1-microvolt");
  1814. vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
  1815. "qcom,micbias2-microvolt");
  1816. vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
  1817. "qcom,micbias3-microvolt");
  1818. vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
  1819. "qcom,micbias4-microvolt");
  1820. snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
  1821. WCD934X_MICB_VAL_MASK, vout_ctl_1);
  1822. snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
  1823. WCD934X_MICB_VAL_MASK, vout_ctl_2);
  1824. snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
  1825. WCD934X_MICB_VAL_MASK, vout_ctl_3);
  1826. snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
  1827. WCD934X_MICB_VAL_MASK, vout_ctl_4);
  1828. if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
  1829. def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
  1830. else
  1831. def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
  1832. wcd->dmic_sample_rate = def_dmic_rate;
  1833. dmic_clk_drv = 0;
  1834. snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
  1835. 0x0C, dmic_clk_drv << 2);
  1836. return 0;
  1837. }
  1838. static void wcd934x_hw_init(struct wcd934x_codec *wcd)
  1839. {
  1840. struct regmap *rm = wcd->regmap;
  1841. /* set SPKR rate to FS_2P4_3P072 */
  1842. regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
  1843. regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
  1844. /* Take DMICs out of reset */
  1845. regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
  1846. }
  1847. static int wcd934x_comp_init(struct snd_soc_component *component)
  1848. {
  1849. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  1850. wcd934x_hw_init(wcd);
  1851. wcd934x_enable_efuse_sensing(wcd);
  1852. wcd934x_get_version(wcd);
  1853. return 0;
  1854. }
  1855. static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
  1856. {
  1857. struct wcd934x_codec *wcd = data;
  1858. unsigned long status = 0;
  1859. int i, j, port_id;
  1860. unsigned int val, int_val = 0;
  1861. irqreturn_t ret = IRQ_NONE;
  1862. bool tx;
  1863. unsigned short reg = 0;
  1864. for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
  1865. i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
  1866. regmap_read(wcd->if_regmap, i, &val);
  1867. status |= ((u32)val << (8 * j));
  1868. }
  1869. for_each_set_bit(j, &status, 32) {
  1870. tx = false;
  1871. port_id = j;
  1872. if (j >= 16) {
  1873. tx = true;
  1874. port_id = j - 16;
  1875. }
  1876. regmap_read(wcd->if_regmap,
  1877. WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
  1878. if (val) {
  1879. if (!tx)
  1880. reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
  1881. (port_id / 8);
  1882. else
  1883. reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
  1884. (port_id / 8);
  1885. regmap_read(wcd->if_regmap, reg, &int_val);
  1886. }
  1887. if (val & WCD934X_SLIM_IRQ_OVERFLOW)
  1888. dev_err_ratelimited(wcd->dev,
  1889. "overflow error on %s port %d, value %x\n",
  1890. (tx ? "TX" : "RX"), port_id, val);
  1891. if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
  1892. dev_err_ratelimited(wcd->dev,
  1893. "underflow error on %s port %d, value %x\n",
  1894. (tx ? "TX" : "RX"), port_id, val);
  1895. if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
  1896. (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
  1897. if (!tx)
  1898. reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
  1899. (port_id / 8);
  1900. else
  1901. reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
  1902. (port_id / 8);
  1903. regmap_read(
  1904. wcd->if_regmap, reg, &int_val);
  1905. if (int_val & (1 << (port_id % 8))) {
  1906. int_val = int_val ^ (1 << (port_id % 8));
  1907. regmap_write(wcd->if_regmap,
  1908. reg, int_val);
  1909. }
  1910. }
  1911. if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
  1912. dev_err_ratelimited(wcd->dev,
  1913. "Port Closed %s port %d, value %x\n",
  1914. (tx ? "TX" : "RX"), port_id, val);
  1915. regmap_write(wcd->if_regmap,
  1916. WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
  1917. BIT(j % 8));
  1918. ret = IRQ_HANDLED;
  1919. }
  1920. return ret;
  1921. }
  1922. static int wcd934x_comp_probe(struct snd_soc_component *component)
  1923. {
  1924. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  1925. int i;
  1926. snd_soc_component_init_regmap(component, wcd->regmap);
  1927. wcd->component = component;
  1928. /* Class-H Init*/
  1929. wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
  1930. if (IS_ERR(wcd->clsh_ctrl))
  1931. return PTR_ERR(wcd->clsh_ctrl);
  1932. /* Default HPH Mode to Class-H Low HiFi */
  1933. wcd->hph_mode = CLS_H_LOHIFI;
  1934. wcd934x_comp_init(component);
  1935. for (i = 0; i < NUM_CODEC_DAIS; i++)
  1936. INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
  1937. wcd934x_init_dmic(component);
  1938. return 0;
  1939. }
  1940. static void wcd934x_comp_remove(struct snd_soc_component *comp)
  1941. {
  1942. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  1943. wcd_clsh_ctrl_free(wcd->clsh_ctrl);
  1944. }
  1945. static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
  1946. int clk_id, int source,
  1947. unsigned int freq, int dir)
  1948. {
  1949. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  1950. int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
  1951. wcd->rate = freq;
  1952. if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
  1953. val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
  1954. snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
  1955. WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
  1956. val);
  1957. return clk_set_rate(wcd->extclk, freq);
  1958. }
  1959. static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
  1960. int iir_idx, int band_idx, int coeff_idx)
  1961. {
  1962. u32 value = 0;
  1963. int reg, b2_reg;
  1964. /* Address does not automatically update if reading */
  1965. reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
  1966. b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
  1967. snd_soc_component_write(component, reg,
  1968. ((band_idx * BAND_MAX + coeff_idx) *
  1969. sizeof(uint32_t)) & 0x7F);
  1970. value |= snd_soc_component_read(component, b2_reg);
  1971. snd_soc_component_write(component, reg,
  1972. ((band_idx * BAND_MAX + coeff_idx)
  1973. * sizeof(uint32_t) + 1) & 0x7F);
  1974. value |= (snd_soc_component_read(component, b2_reg) << 8);
  1975. snd_soc_component_write(component, reg,
  1976. ((band_idx * BAND_MAX + coeff_idx)
  1977. * sizeof(uint32_t) + 2) & 0x7F);
  1978. value |= (snd_soc_component_read(component, b2_reg) << 16);
  1979. snd_soc_component_write(component, reg,
  1980. ((band_idx * BAND_MAX + coeff_idx)
  1981. * sizeof(uint32_t) + 3) & 0x7F);
  1982. /* Mask bits top 2 bits since they are reserved */
  1983. value |= (snd_soc_component_read(component, b2_reg) << 24);
  1984. return value;
  1985. }
  1986. static void set_iir_band_coeff(struct snd_soc_component *component,
  1987. int iir_idx, int band_idx, uint32_t value)
  1988. {
  1989. int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
  1990. snd_soc_component_write(component, reg, (value & 0xFF));
  1991. snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
  1992. snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
  1993. /* Mask top 2 bits, 7-8 are reserved */
  1994. snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
  1995. }
  1996. static int wcd934x_put_iir_band_audio_mixer(
  1997. struct snd_kcontrol *kcontrol,
  1998. struct snd_ctl_elem_value *ucontrol)
  1999. {
  2000. struct snd_soc_component *component =
  2001. snd_soc_kcontrol_component(kcontrol);
  2002. struct wcd_iir_filter_ctl *ctl =
  2003. (struct wcd_iir_filter_ctl *)kcontrol->private_value;
  2004. struct soc_bytes_ext *params = &ctl->bytes_ext;
  2005. int iir_idx = ctl->iir_idx;
  2006. int band_idx = ctl->band_idx;
  2007. u32 coeff[BAND_MAX];
  2008. int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
  2009. memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
  2010. /* Mask top bit it is reserved */
  2011. /* Updates addr automatically for each B2 write */
  2012. snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
  2013. sizeof(uint32_t)) & 0x7F);
  2014. set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
  2015. set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
  2016. set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
  2017. set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
  2018. set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
  2019. return 0;
  2020. }
  2021. static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
  2022. struct snd_ctl_elem_value *ucontrol)
  2023. {
  2024. struct snd_soc_component *component =
  2025. snd_soc_kcontrol_component(kcontrol);
  2026. struct wcd_iir_filter_ctl *ctl =
  2027. (struct wcd_iir_filter_ctl *)kcontrol->private_value;
  2028. struct soc_bytes_ext *params = &ctl->bytes_ext;
  2029. int iir_idx = ctl->iir_idx;
  2030. int band_idx = ctl->band_idx;
  2031. u32 coeff[BAND_MAX];
  2032. coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
  2033. coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
  2034. coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
  2035. coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
  2036. coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
  2037. memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
  2038. return 0;
  2039. }
  2040. static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
  2041. struct snd_ctl_elem_info *ucontrol)
  2042. {
  2043. struct wcd_iir_filter_ctl *ctl =
  2044. (struct wcd_iir_filter_ctl *)kcontrol->private_value;
  2045. struct soc_bytes_ext *params = &ctl->bytes_ext;
  2046. ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  2047. ucontrol->count = params->max;
  2048. return 0;
  2049. }
  2050. static int wcd934x_compander_get(struct snd_kcontrol *kc,
  2051. struct snd_ctl_elem_value *ucontrol)
  2052. {
  2053. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  2054. int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
  2055. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  2056. ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
  2057. return 0;
  2058. }
  2059. static int wcd934x_compander_set(struct snd_kcontrol *kc,
  2060. struct snd_ctl_elem_value *ucontrol)
  2061. {
  2062. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  2063. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  2064. int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
  2065. int value = ucontrol->value.integer.value[0];
  2066. int sel;
  2067. if (wcd->comp_enabled[comp] == value)
  2068. return 0;
  2069. wcd->comp_enabled[comp] = value;
  2070. sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
  2071. WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
  2072. /* Any specific register configuration for compander */
  2073. switch (comp) {
  2074. case COMPANDER_1:
  2075. /* Set Gain Source Select based on compander enable/disable */
  2076. snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
  2077. WCD934X_HPH_GAIN_SRC_SEL_MASK,
  2078. sel);
  2079. break;
  2080. case COMPANDER_2:
  2081. snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
  2082. WCD934X_HPH_GAIN_SRC_SEL_MASK,
  2083. sel);
  2084. break;
  2085. case COMPANDER_3:
  2086. case COMPANDER_4:
  2087. case COMPANDER_7:
  2088. case COMPANDER_8:
  2089. break;
  2090. default:
  2091. return 0;
  2092. }
  2093. return 1;
  2094. }
  2095. static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
  2096. struct snd_ctl_elem_value *ucontrol)
  2097. {
  2098. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  2099. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  2100. ucontrol->value.enumerated.item[0] = wcd->hph_mode;
  2101. return 0;
  2102. }
  2103. static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
  2104. struct snd_ctl_elem_value *ucontrol)
  2105. {
  2106. struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
  2107. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  2108. u32 mode_val;
  2109. mode_val = ucontrol->value.enumerated.item[0];
  2110. if (mode_val == wcd->hph_mode)
  2111. return 0;
  2112. if (mode_val == 0) {
  2113. dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
  2114. mode_val = CLS_H_LOHIFI;
  2115. }
  2116. wcd->hph_mode = mode_val;
  2117. return 1;
  2118. }
  2119. static int slim_rx_mux_get(struct snd_kcontrol *kc,
  2120. struct snd_ctl_elem_value *ucontrol)
  2121. {
  2122. struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
  2123. struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
  2124. struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
  2125. ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
  2126. return 0;
  2127. }
  2128. static int slim_rx_mux_to_dai_id(int mux)
  2129. {
  2130. int aif_id;
  2131. switch (mux) {
  2132. case 1:
  2133. aif_id = AIF1_PB;
  2134. break;
  2135. case 2:
  2136. aif_id = AIF2_PB;
  2137. break;
  2138. case 3:
  2139. aif_id = AIF3_PB;
  2140. break;
  2141. case 4:
  2142. aif_id = AIF4_PB;
  2143. break;
  2144. default:
  2145. aif_id = -1;
  2146. break;
  2147. }
  2148. return aif_id;
  2149. }
  2150. static int slim_rx_mux_put(struct snd_kcontrol *kc,
  2151. struct snd_ctl_elem_value *ucontrol)
  2152. {
  2153. struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
  2154. struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
  2155. struct soc_enum *e = (struct soc_enum *)kc->private_value;
  2156. struct snd_soc_dapm_update *update = NULL;
  2157. struct wcd934x_slim_ch *ch, *c;
  2158. u32 port_id = w->shift;
  2159. bool found = false;
  2160. int mux_idx;
  2161. int prev_mux_idx = wcd->rx_port_value[port_id];
  2162. int aif_id;
  2163. mux_idx = ucontrol->value.enumerated.item[0];
  2164. if (mux_idx == prev_mux_idx)
  2165. return 0;
  2166. switch(mux_idx) {
  2167. case 0:
  2168. aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
  2169. if (aif_id < 0)
  2170. return 0;
  2171. list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
  2172. if (ch->port == port_id + WCD934X_RX_START) {
  2173. found = true;
  2174. list_del_init(&ch->list);
  2175. break;
  2176. }
  2177. }
  2178. if (!found)
  2179. return 0;
  2180. break;
  2181. case 1 ... 4:
  2182. aif_id = slim_rx_mux_to_dai_id(mux_idx);
  2183. if (aif_id < 0)
  2184. return 0;
  2185. if (list_empty(&wcd->rx_chs[port_id].list)) {
  2186. list_add_tail(&wcd->rx_chs[port_id].list,
  2187. &wcd->dai[aif_id].slim_ch_list);
  2188. } else {
  2189. dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
  2190. return 0;
  2191. }
  2192. break;
  2193. default:
  2194. dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
  2195. goto err;
  2196. }
  2197. wcd->rx_port_value[port_id] = mux_idx;
  2198. snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
  2199. e, update);
  2200. return 1;
  2201. err:
  2202. return -EINVAL;
  2203. }
  2204. static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
  2205. struct snd_ctl_elem_value *ucontrol)
  2206. {
  2207. struct soc_enum *e = (struct soc_enum *)kc->private_value;
  2208. struct snd_soc_component *component;
  2209. int reg, val, ret;
  2210. component = snd_soc_dapm_kcontrol_component(kc);
  2211. val = ucontrol->value.enumerated.item[0];
  2212. if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
  2213. reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
  2214. else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
  2215. reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
  2216. else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
  2217. reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
  2218. else
  2219. return -EINVAL;
  2220. /* Set Look Ahead Delay */
  2221. if (val)
  2222. snd_soc_component_update_bits(component, reg,
  2223. WCD934X_RX_DLY_ZN_EN_MASK,
  2224. WCD934X_RX_DLY_ZN_ENABLE);
  2225. else
  2226. snd_soc_component_update_bits(component, reg,
  2227. WCD934X_RX_DLY_ZN_EN_MASK,
  2228. WCD934X_RX_DLY_ZN_DISABLE);
  2229. ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
  2230. return ret;
  2231. }
  2232. static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
  2233. struct snd_ctl_elem_value *ucontrol)
  2234. {
  2235. struct snd_soc_component *comp;
  2236. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  2237. unsigned int val;
  2238. u16 mic_sel_reg = 0;
  2239. u8 mic_sel;
  2240. comp = snd_soc_dapm_kcontrol_component(kcontrol);
  2241. val = ucontrol->value.enumerated.item[0];
  2242. if (val > e->items - 1)
  2243. return -EINVAL;
  2244. switch (e->reg) {
  2245. case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
  2246. if (e->shift_l == 0)
  2247. mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
  2248. else if (e->shift_l == 2)
  2249. mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
  2250. else if (e->shift_l == 4)
  2251. mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
  2252. break;
  2253. case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
  2254. if (e->shift_l == 0)
  2255. mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
  2256. else if (e->shift_l == 2)
  2257. mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
  2258. break;
  2259. case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
  2260. if (e->shift_l == 0)
  2261. mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
  2262. else if (e->shift_l == 2)
  2263. mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
  2264. break;
  2265. case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
  2266. if (e->shift_l == 0)
  2267. mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
  2268. else if (e->shift_l == 2)
  2269. mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
  2270. break;
  2271. default:
  2272. dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
  2273. __func__, e->reg);
  2274. return -EINVAL;
  2275. }
  2276. /* ADC: 0, DMIC: 1 */
  2277. mic_sel = val ? 0x0 : 0x1;
  2278. if (mic_sel_reg)
  2279. snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
  2280. mic_sel << 7);
  2281. return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  2282. }
  2283. static const struct snd_kcontrol_new rx_int0_2_mux =
  2284. SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
  2285. static const struct snd_kcontrol_new rx_int1_2_mux =
  2286. SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
  2287. static const struct snd_kcontrol_new rx_int2_2_mux =
  2288. SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
  2289. static const struct snd_kcontrol_new rx_int3_2_mux =
  2290. SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
  2291. static const struct snd_kcontrol_new rx_int4_2_mux =
  2292. SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
  2293. static const struct snd_kcontrol_new rx_int7_2_mux =
  2294. SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
  2295. static const struct snd_kcontrol_new rx_int8_2_mux =
  2296. SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
  2297. static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
  2298. SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
  2299. static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
  2300. SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
  2301. static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
  2302. SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
  2303. static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
  2304. SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
  2305. static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
  2306. SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
  2307. static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
  2308. SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
  2309. static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
  2310. SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
  2311. static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
  2312. SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
  2313. static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
  2314. SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
  2315. static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
  2316. SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
  2317. static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
  2318. SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
  2319. static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
  2320. SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
  2321. static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
  2322. SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
  2323. static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
  2324. SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
  2325. static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
  2326. SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
  2327. static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
  2328. SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
  2329. static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
  2330. SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
  2331. static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
  2332. SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
  2333. static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
  2334. SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
  2335. static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
  2336. SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
  2337. static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
  2338. SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
  2339. static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
  2340. SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
  2341. static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
  2342. SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
  2343. static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
  2344. SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
  2345. static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
  2346. SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
  2347. static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
  2348. SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
  2349. static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
  2350. SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
  2351. static const struct snd_kcontrol_new iir0_inp0_mux =
  2352. SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
  2353. static const struct snd_kcontrol_new iir0_inp1_mux =
  2354. SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
  2355. static const struct snd_kcontrol_new iir0_inp2_mux =
  2356. SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
  2357. static const struct snd_kcontrol_new iir0_inp3_mux =
  2358. SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
  2359. static const struct snd_kcontrol_new iir1_inp0_mux =
  2360. SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
  2361. static const struct snd_kcontrol_new iir1_inp1_mux =
  2362. SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
  2363. static const struct snd_kcontrol_new iir1_inp2_mux =
  2364. SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
  2365. static const struct snd_kcontrol_new iir1_inp3_mux =
  2366. SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
  2367. static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
  2368. SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
  2369. slim_rx_mux_get, slim_rx_mux_put),
  2370. SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
  2371. slim_rx_mux_get, slim_rx_mux_put),
  2372. SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
  2373. slim_rx_mux_get, slim_rx_mux_put),
  2374. SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
  2375. slim_rx_mux_get, slim_rx_mux_put),
  2376. SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
  2377. slim_rx_mux_get, slim_rx_mux_put),
  2378. SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
  2379. slim_rx_mux_get, slim_rx_mux_put),
  2380. SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
  2381. slim_rx_mux_get, slim_rx_mux_put),
  2382. SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
  2383. slim_rx_mux_get, slim_rx_mux_put),
  2384. };
  2385. static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
  2386. SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
  2387. };
  2388. static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
  2389. SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
  2390. };
  2391. static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
  2392. SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
  2393. };
  2394. static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
  2395. SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
  2396. };
  2397. static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
  2398. SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
  2399. snd_soc_dapm_get_enum_double,
  2400. wcd934x_int_dem_inp_mux_put);
  2401. static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
  2402. SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
  2403. snd_soc_dapm_get_enum_double,
  2404. wcd934x_int_dem_inp_mux_put);
  2405. static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
  2406. SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
  2407. snd_soc_dapm_get_enum_double,
  2408. wcd934x_int_dem_inp_mux_put);
  2409. static const struct snd_kcontrol_new rx_int0_1_interp_mux =
  2410. SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
  2411. static const struct snd_kcontrol_new rx_int1_1_interp_mux =
  2412. SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
  2413. static const struct snd_kcontrol_new rx_int2_1_interp_mux =
  2414. SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
  2415. static const struct snd_kcontrol_new rx_int3_1_interp_mux =
  2416. SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
  2417. static const struct snd_kcontrol_new rx_int4_1_interp_mux =
  2418. SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
  2419. static const struct snd_kcontrol_new rx_int7_1_interp_mux =
  2420. SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
  2421. static const struct snd_kcontrol_new rx_int8_1_interp_mux =
  2422. SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
  2423. static const struct snd_kcontrol_new rx_int0_2_interp_mux =
  2424. SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
  2425. static const struct snd_kcontrol_new rx_int1_2_interp_mux =
  2426. SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
  2427. static const struct snd_kcontrol_new rx_int2_2_interp_mux =
  2428. SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
  2429. static const struct snd_kcontrol_new rx_int3_2_interp_mux =
  2430. SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
  2431. static const struct snd_kcontrol_new rx_int4_2_interp_mux =
  2432. SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
  2433. static const struct snd_kcontrol_new rx_int7_2_interp_mux =
  2434. SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
  2435. static const struct snd_kcontrol_new rx_int8_2_interp_mux =
  2436. SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
  2437. static const struct snd_kcontrol_new tx_dmic_mux0 =
  2438. SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
  2439. static const struct snd_kcontrol_new tx_dmic_mux1 =
  2440. SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
  2441. static const struct snd_kcontrol_new tx_dmic_mux2 =
  2442. SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
  2443. static const struct snd_kcontrol_new tx_dmic_mux3 =
  2444. SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
  2445. static const struct snd_kcontrol_new tx_dmic_mux4 =
  2446. SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
  2447. static const struct snd_kcontrol_new tx_dmic_mux5 =
  2448. SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
  2449. static const struct snd_kcontrol_new tx_dmic_mux6 =
  2450. SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
  2451. static const struct snd_kcontrol_new tx_dmic_mux7 =
  2452. SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
  2453. static const struct snd_kcontrol_new tx_dmic_mux8 =
  2454. SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
  2455. static const struct snd_kcontrol_new tx_amic_mux0 =
  2456. SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
  2457. static const struct snd_kcontrol_new tx_amic_mux1 =
  2458. SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
  2459. static const struct snd_kcontrol_new tx_amic_mux2 =
  2460. SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
  2461. static const struct snd_kcontrol_new tx_amic_mux3 =
  2462. SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
  2463. static const struct snd_kcontrol_new tx_amic_mux4 =
  2464. SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
  2465. static const struct snd_kcontrol_new tx_amic_mux5 =
  2466. SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
  2467. static const struct snd_kcontrol_new tx_amic_mux6 =
  2468. SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
  2469. static const struct snd_kcontrol_new tx_amic_mux7 =
  2470. SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
  2471. static const struct snd_kcontrol_new tx_amic_mux8 =
  2472. SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
  2473. static const struct snd_kcontrol_new tx_amic4_5 =
  2474. SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
  2475. static const struct snd_kcontrol_new tx_adc_mux0_mux =
  2476. SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
  2477. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2478. static const struct snd_kcontrol_new tx_adc_mux1_mux =
  2479. SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
  2480. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2481. static const struct snd_kcontrol_new tx_adc_mux2_mux =
  2482. SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
  2483. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2484. static const struct snd_kcontrol_new tx_adc_mux3_mux =
  2485. SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
  2486. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2487. static const struct snd_kcontrol_new tx_adc_mux4_mux =
  2488. SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
  2489. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2490. static const struct snd_kcontrol_new tx_adc_mux5_mux =
  2491. SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
  2492. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2493. static const struct snd_kcontrol_new tx_adc_mux6_mux =
  2494. SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
  2495. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2496. static const struct snd_kcontrol_new tx_adc_mux7_mux =
  2497. SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
  2498. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2499. static const struct snd_kcontrol_new tx_adc_mux8_mux =
  2500. SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
  2501. snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
  2502. static const struct snd_kcontrol_new cdc_if_tx0_mux =
  2503. SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
  2504. static const struct snd_kcontrol_new cdc_if_tx1_mux =
  2505. SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
  2506. static const struct snd_kcontrol_new cdc_if_tx2_mux =
  2507. SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
  2508. static const struct snd_kcontrol_new cdc_if_tx3_mux =
  2509. SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
  2510. static const struct snd_kcontrol_new cdc_if_tx4_mux =
  2511. SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
  2512. static const struct snd_kcontrol_new cdc_if_tx5_mux =
  2513. SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
  2514. static const struct snd_kcontrol_new cdc_if_tx6_mux =
  2515. SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
  2516. static const struct snd_kcontrol_new cdc_if_tx7_mux =
  2517. SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
  2518. static const struct snd_kcontrol_new cdc_if_tx8_mux =
  2519. SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
  2520. static const struct snd_kcontrol_new cdc_if_tx9_mux =
  2521. SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
  2522. static const struct snd_kcontrol_new cdc_if_tx10_mux =
  2523. SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
  2524. static const struct snd_kcontrol_new cdc_if_tx11_mux =
  2525. SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
  2526. static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
  2527. SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
  2528. static const struct snd_kcontrol_new cdc_if_tx13_mux =
  2529. SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
  2530. static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
  2531. SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
  2532. static int slim_tx_mixer_get(struct snd_kcontrol *kc,
  2533. struct snd_ctl_elem_value *ucontrol)
  2534. {
  2535. struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
  2536. struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
  2537. struct soc_mixer_control *mixer =
  2538. (struct soc_mixer_control *)kc->private_value;
  2539. int port_id = mixer->shift;
  2540. ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
  2541. return 0;
  2542. }
  2543. static int slim_tx_mixer_put(struct snd_kcontrol *kc,
  2544. struct snd_ctl_elem_value *ucontrol)
  2545. {
  2546. struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
  2547. struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
  2548. struct snd_soc_dapm_update *update = NULL;
  2549. struct soc_mixer_control *mixer =
  2550. (struct soc_mixer_control *)kc->private_value;
  2551. int enable = ucontrol->value.integer.value[0];
  2552. struct wcd934x_slim_ch *ch, *c;
  2553. int dai_id = widget->shift;
  2554. int port_id = mixer->shift;
  2555. /* only add to the list if value not set */
  2556. if (enable == wcd->tx_port_value[port_id])
  2557. return 0;
  2558. if (enable) {
  2559. if (list_empty(&wcd->tx_chs[port_id].list)) {
  2560. list_add_tail(&wcd->tx_chs[port_id].list,
  2561. &wcd->dai[dai_id].slim_ch_list);
  2562. } else {
  2563. dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
  2564. return 0;
  2565. }
  2566. } else {
  2567. bool found = false;
  2568. list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
  2569. if (ch->port == port_id) {
  2570. found = true;
  2571. list_del_init(&wcd->tx_chs[port_id].list);
  2572. break;
  2573. }
  2574. }
  2575. if (!found)
  2576. return 0;
  2577. }
  2578. wcd->tx_port_value[port_id] = enable;
  2579. snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
  2580. return 1;
  2581. }
  2582. static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
  2583. SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
  2584. slim_tx_mixer_get, slim_tx_mixer_put),
  2585. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
  2586. slim_tx_mixer_get, slim_tx_mixer_put),
  2587. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
  2588. slim_tx_mixer_get, slim_tx_mixer_put),
  2589. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
  2590. slim_tx_mixer_get, slim_tx_mixer_put),
  2591. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
  2592. slim_tx_mixer_get, slim_tx_mixer_put),
  2593. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
  2594. slim_tx_mixer_get, slim_tx_mixer_put),
  2595. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
  2596. slim_tx_mixer_get, slim_tx_mixer_put),
  2597. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
  2598. slim_tx_mixer_get, slim_tx_mixer_put),
  2599. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
  2600. slim_tx_mixer_get, slim_tx_mixer_put),
  2601. SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
  2602. slim_tx_mixer_get, slim_tx_mixer_put),
  2603. SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
  2604. slim_tx_mixer_get, slim_tx_mixer_put),
  2605. SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
  2606. slim_tx_mixer_get, slim_tx_mixer_put),
  2607. SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
  2608. slim_tx_mixer_get, slim_tx_mixer_put),
  2609. };
  2610. static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
  2611. SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
  2612. slim_tx_mixer_get, slim_tx_mixer_put),
  2613. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
  2614. slim_tx_mixer_get, slim_tx_mixer_put),
  2615. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
  2616. slim_tx_mixer_get, slim_tx_mixer_put),
  2617. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
  2618. slim_tx_mixer_get, slim_tx_mixer_put),
  2619. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
  2620. slim_tx_mixer_get, slim_tx_mixer_put),
  2621. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
  2622. slim_tx_mixer_get, slim_tx_mixer_put),
  2623. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
  2624. slim_tx_mixer_get, slim_tx_mixer_put),
  2625. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
  2626. slim_tx_mixer_get, slim_tx_mixer_put),
  2627. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
  2628. slim_tx_mixer_get, slim_tx_mixer_put),
  2629. SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
  2630. slim_tx_mixer_get, slim_tx_mixer_put),
  2631. SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
  2632. slim_tx_mixer_get, slim_tx_mixer_put),
  2633. SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
  2634. slim_tx_mixer_get, slim_tx_mixer_put),
  2635. SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
  2636. slim_tx_mixer_get, slim_tx_mixer_put),
  2637. };
  2638. static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
  2639. SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
  2640. slim_tx_mixer_get, slim_tx_mixer_put),
  2641. SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
  2642. slim_tx_mixer_get, slim_tx_mixer_put),
  2643. SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
  2644. slim_tx_mixer_get, slim_tx_mixer_put),
  2645. SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
  2646. slim_tx_mixer_get, slim_tx_mixer_put),
  2647. SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
  2648. slim_tx_mixer_get, slim_tx_mixer_put),
  2649. SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
  2650. slim_tx_mixer_get, slim_tx_mixer_put),
  2651. SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
  2652. slim_tx_mixer_get, slim_tx_mixer_put),
  2653. SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
  2654. slim_tx_mixer_get, slim_tx_mixer_put),
  2655. SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
  2656. slim_tx_mixer_get, slim_tx_mixer_put),
  2657. SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
  2658. slim_tx_mixer_get, slim_tx_mixer_put),
  2659. SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
  2660. slim_tx_mixer_get, slim_tx_mixer_put),
  2661. SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
  2662. slim_tx_mixer_get, slim_tx_mixer_put),
  2663. SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
  2664. slim_tx_mixer_get, slim_tx_mixer_put),
  2665. };
  2666. static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
  2667. /* Gain Controls */
  2668. SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
  2669. SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
  2670. SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
  2671. SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
  2672. 3, 16, 1, line_gain),
  2673. SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
  2674. 3, 16, 1, line_gain),
  2675. SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
  2676. SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
  2677. SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
  2678. SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
  2679. SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
  2680. -84, 40, digital_gain), /* -84dB min - 40dB max */
  2681. SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
  2682. -84, 40, digital_gain),
  2683. SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
  2684. -84, 40, digital_gain),
  2685. SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
  2686. -84, 40, digital_gain),
  2687. SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
  2688. -84, 40, digital_gain),
  2689. SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
  2690. -84, 40, digital_gain),
  2691. SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
  2692. -84, 40, digital_gain),
  2693. SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
  2694. WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
  2695. -84, 40, digital_gain),
  2696. SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
  2697. WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
  2698. -84, 40, digital_gain),
  2699. SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
  2700. WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
  2701. -84, 40, digital_gain),
  2702. SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
  2703. WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
  2704. -84, 40, digital_gain),
  2705. SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
  2706. WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
  2707. -84, 40, digital_gain),
  2708. SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
  2709. WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
  2710. -84, 40, digital_gain),
  2711. SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
  2712. WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
  2713. -84, 40, digital_gain),
  2714. SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
  2715. -84, 40, digital_gain),
  2716. SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
  2717. -84, 40, digital_gain),
  2718. SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
  2719. -84, 40, digital_gain),
  2720. SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
  2721. -84, 40, digital_gain),
  2722. SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
  2723. -84, 40, digital_gain),
  2724. SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
  2725. -84, 40, digital_gain),
  2726. SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
  2727. -84, 40, digital_gain),
  2728. SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
  2729. -84, 40, digital_gain),
  2730. SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
  2731. -84, 40, digital_gain),
  2732. SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
  2733. WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
  2734. digital_gain),
  2735. SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
  2736. WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
  2737. digital_gain),
  2738. SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
  2739. WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
  2740. digital_gain),
  2741. SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
  2742. WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
  2743. digital_gain),
  2744. SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
  2745. WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
  2746. digital_gain),
  2747. SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
  2748. WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
  2749. digital_gain),
  2750. SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
  2751. WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
  2752. digital_gain),
  2753. SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
  2754. WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
  2755. digital_gain),
  2756. SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
  2757. SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
  2758. SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
  2759. SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
  2760. SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
  2761. SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
  2762. SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
  2763. SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
  2764. SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
  2765. SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
  2766. SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
  2767. SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
  2768. SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
  2769. SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
  2770. SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
  2771. SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
  2772. SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
  2773. SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
  2774. SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
  2775. SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
  2776. SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
  2777. SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
  2778. SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
  2779. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2780. wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
  2781. SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
  2782. 0, 1, 0),
  2783. SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
  2784. 1, 1, 0),
  2785. SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
  2786. 2, 1, 0),
  2787. SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
  2788. 3, 1, 0),
  2789. SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
  2790. 4, 1, 0),
  2791. SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
  2792. 0, 1, 0),
  2793. SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
  2794. 1, 1, 0),
  2795. SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
  2796. 2, 1, 0),
  2797. SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
  2798. 3, 1, 0),
  2799. SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
  2800. 4, 1, 0),
  2801. WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
  2802. WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
  2803. WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
  2804. WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
  2805. WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
  2806. WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
  2807. WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
  2808. WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
  2809. WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
  2810. WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
  2811. SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
  2812. wcd934x_compander_get, wcd934x_compander_set),
  2813. SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
  2814. wcd934x_compander_get, wcd934x_compander_set),
  2815. SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
  2816. wcd934x_compander_get, wcd934x_compander_set),
  2817. SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
  2818. wcd934x_compander_get, wcd934x_compander_set),
  2819. SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
  2820. wcd934x_compander_get, wcd934x_compander_set),
  2821. SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
  2822. wcd934x_compander_get, wcd934x_compander_set),
  2823. };
  2824. static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
  2825. struct snd_soc_component *component)
  2826. {
  2827. int port_num = 0;
  2828. unsigned short reg = 0;
  2829. unsigned int val = 0;
  2830. struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
  2831. struct wcd934x_slim_ch *ch;
  2832. list_for_each_entry(ch, &dai->slim_ch_list, list) {
  2833. if (ch->port >= WCD934X_RX_START) {
  2834. port_num = ch->port - WCD934X_RX_START;
  2835. reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
  2836. } else {
  2837. port_num = ch->port;
  2838. reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
  2839. }
  2840. regmap_read(wcd->if_regmap, reg, &val);
  2841. if (!(val & BIT(port_num % 8)))
  2842. regmap_write(wcd->if_regmap, reg,
  2843. val | BIT(port_num % 8));
  2844. }
  2845. }
  2846. static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
  2847. struct snd_kcontrol *kc, int event)
  2848. {
  2849. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2850. struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
  2851. struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
  2852. switch (event) {
  2853. case SND_SOC_DAPM_POST_PMU:
  2854. wcd934x_codec_enable_int_port(dai, comp);
  2855. break;
  2856. }
  2857. return 0;
  2858. }
  2859. static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
  2860. u16 interp_idx, int event)
  2861. {
  2862. u16 hd2_scale_reg;
  2863. u16 hd2_enable_reg = 0;
  2864. switch (interp_idx) {
  2865. case INTERP_HPHL:
  2866. hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
  2867. hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
  2868. break;
  2869. case INTERP_HPHR:
  2870. hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
  2871. hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
  2872. break;
  2873. default:
  2874. return;
  2875. }
  2876. if (SND_SOC_DAPM_EVENT_ON(event)) {
  2877. snd_soc_component_update_bits(component, hd2_scale_reg,
  2878. WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
  2879. WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
  2880. snd_soc_component_update_bits(component, hd2_enable_reg,
  2881. WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
  2882. WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
  2883. }
  2884. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  2885. snd_soc_component_update_bits(component, hd2_enable_reg,
  2886. WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
  2887. WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
  2888. snd_soc_component_update_bits(component, hd2_scale_reg,
  2889. WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
  2890. WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
  2891. }
  2892. }
  2893. static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
  2894. u16 interp_idx, int event)
  2895. {
  2896. u8 hph_dly_mask;
  2897. u16 hph_lut_bypass_reg = 0;
  2898. switch (interp_idx) {
  2899. case INTERP_HPHL:
  2900. hph_dly_mask = 1;
  2901. hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
  2902. break;
  2903. case INTERP_HPHR:
  2904. hph_dly_mask = 2;
  2905. hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
  2906. break;
  2907. default:
  2908. return;
  2909. }
  2910. if (SND_SOC_DAPM_EVENT_ON(event)) {
  2911. snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
  2912. hph_dly_mask, 0x0);
  2913. snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
  2914. WCD934X_HPH_LUT_BYPASS_MASK,
  2915. WCD934X_HPH_LUT_BYPASS_ENABLE);
  2916. }
  2917. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  2918. snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
  2919. hph_dly_mask, hph_dly_mask);
  2920. snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
  2921. WCD934X_HPH_LUT_BYPASS_MASK,
  2922. WCD934X_HPH_LUT_BYPASS_DISABLE);
  2923. }
  2924. }
  2925. static int wcd934x_config_compander(struct snd_soc_component *comp,
  2926. int interp_n, int event)
  2927. {
  2928. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  2929. int compander;
  2930. u16 comp_ctl0_reg, rx_path_cfg0_reg;
  2931. /* EAR does not have compander */
  2932. if (!interp_n)
  2933. return 0;
  2934. compander = interp_n - 1;
  2935. if (!wcd->comp_enabled[compander])
  2936. return 0;
  2937. comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
  2938. rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
  2939. switch (event) {
  2940. case SND_SOC_DAPM_PRE_PMU:
  2941. /* Enable Compander Clock */
  2942. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2943. WCD934X_COMP_CLK_EN_MASK,
  2944. WCD934X_COMP_CLK_ENABLE);
  2945. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2946. WCD934X_COMP_SOFT_RST_MASK,
  2947. WCD934X_COMP_SOFT_RST_ENABLE);
  2948. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2949. WCD934X_COMP_SOFT_RST_MASK,
  2950. WCD934X_COMP_SOFT_RST_DISABLE);
  2951. snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
  2952. WCD934X_HPH_CMP_EN_MASK,
  2953. WCD934X_HPH_CMP_ENABLE);
  2954. break;
  2955. case SND_SOC_DAPM_POST_PMD:
  2956. snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
  2957. WCD934X_HPH_CMP_EN_MASK,
  2958. WCD934X_HPH_CMP_DISABLE);
  2959. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2960. WCD934X_COMP_HALT_MASK,
  2961. WCD934X_COMP_HALT);
  2962. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2963. WCD934X_COMP_SOFT_RST_MASK,
  2964. WCD934X_COMP_SOFT_RST_ENABLE);
  2965. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2966. WCD934X_COMP_SOFT_RST_MASK,
  2967. WCD934X_COMP_SOFT_RST_DISABLE);
  2968. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2969. WCD934X_COMP_CLK_EN_MASK, 0x0);
  2970. snd_soc_component_update_bits(comp, comp_ctl0_reg,
  2971. WCD934X_COMP_SOFT_RST_MASK, 0x0);
  2972. break;
  2973. }
  2974. return 0;
  2975. }
  2976. static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
  2977. struct snd_kcontrol *kc, int event)
  2978. {
  2979. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  2980. int interp_idx = w->shift;
  2981. u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
  2982. switch (event) {
  2983. case SND_SOC_DAPM_PRE_PMU:
  2984. /* Clk enable */
  2985. snd_soc_component_update_bits(comp, main_reg,
  2986. WCD934X_RX_CLK_EN_MASK,
  2987. WCD934X_RX_CLK_ENABLE);
  2988. wcd934x_codec_hd2_control(comp, interp_idx, event);
  2989. wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
  2990. wcd934x_config_compander(comp, interp_idx, event);
  2991. break;
  2992. case SND_SOC_DAPM_POST_PMD:
  2993. wcd934x_config_compander(comp, interp_idx, event);
  2994. wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
  2995. wcd934x_codec_hd2_control(comp, interp_idx, event);
  2996. /* Clk Disable */
  2997. snd_soc_component_update_bits(comp, main_reg,
  2998. WCD934X_RX_CLK_EN_MASK, 0);
  2999. /* Reset enable and disable */
  3000. snd_soc_component_update_bits(comp, main_reg,
  3001. WCD934X_RX_RESET_MASK,
  3002. WCD934X_RX_RESET_ENABLE);
  3003. snd_soc_component_update_bits(comp, main_reg,
  3004. WCD934X_RX_RESET_MASK,
  3005. WCD934X_RX_RESET_DISABLE);
  3006. /* Reset rate to 48K*/
  3007. snd_soc_component_update_bits(comp, main_reg,
  3008. WCD934X_RX_PCM_RATE_MASK,
  3009. WCD934X_RX_PCM_RATE_F_48K);
  3010. break;
  3011. }
  3012. return 0;
  3013. }
  3014. static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
  3015. struct snd_kcontrol *kc, int event)
  3016. {
  3017. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3018. int offset_val = 0;
  3019. u16 gain_reg, mix_reg;
  3020. int val = 0;
  3021. gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
  3022. (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
  3023. mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
  3024. (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
  3025. switch (event) {
  3026. case SND_SOC_DAPM_PRE_PMU:
  3027. /* Clk enable */
  3028. snd_soc_component_update_bits(comp, mix_reg,
  3029. WCD934X_CDC_RX_MIX_CLK_EN_MASK,
  3030. WCD934X_CDC_RX_MIX_CLK_ENABLE);
  3031. break;
  3032. case SND_SOC_DAPM_POST_PMU:
  3033. val = snd_soc_component_read(comp, gain_reg);
  3034. val += offset_val;
  3035. snd_soc_component_write(comp, gain_reg, val);
  3036. break;
  3037. }
  3038. return 0;
  3039. }
  3040. static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
  3041. struct snd_kcontrol *kcontrol, int event)
  3042. {
  3043. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3044. int reg = w->reg;
  3045. switch (event) {
  3046. case SND_SOC_DAPM_POST_PMU:
  3047. /* B1 GAIN */
  3048. snd_soc_component_write(comp, reg,
  3049. snd_soc_component_read(comp, reg));
  3050. /* B2 GAIN */
  3051. reg++;
  3052. snd_soc_component_write(comp, reg,
  3053. snd_soc_component_read(comp, reg));
  3054. /* B3 GAIN */
  3055. reg++;
  3056. snd_soc_component_write(comp, reg,
  3057. snd_soc_component_read(comp, reg));
  3058. /* B4 GAIN */
  3059. reg++;
  3060. snd_soc_component_write(comp, reg,
  3061. snd_soc_component_read(comp, reg));
  3062. /* B5 GAIN */
  3063. reg++;
  3064. snd_soc_component_write(comp, reg,
  3065. snd_soc_component_read(comp, reg));
  3066. break;
  3067. default:
  3068. break;
  3069. }
  3070. return 0;
  3071. }
  3072. static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
  3073. struct snd_kcontrol *kcontrol,
  3074. int event)
  3075. {
  3076. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3077. u16 gain_reg;
  3078. gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
  3079. WCD934X_RX_PATH_CTL_OFFSET);
  3080. switch (event) {
  3081. case SND_SOC_DAPM_POST_PMU:
  3082. snd_soc_component_write(comp, gain_reg,
  3083. snd_soc_component_read(comp, gain_reg));
  3084. break;
  3085. }
  3086. return 0;
  3087. }
  3088. static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  3089. struct snd_kcontrol *kc, int event)
  3090. {
  3091. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3092. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  3093. switch (event) {
  3094. case SND_SOC_DAPM_PRE_PMU:
  3095. /* Disable AutoChop timer during power up */
  3096. snd_soc_component_update_bits(comp,
  3097. WCD934X_HPH_NEW_INT_HPH_TIMER1,
  3098. WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
  3099. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3100. WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
  3101. break;
  3102. case SND_SOC_DAPM_POST_PMD:
  3103. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3104. WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
  3105. break;
  3106. }
  3107. return 0;
  3108. }
  3109. static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  3110. struct snd_kcontrol *kcontrol,
  3111. int event)
  3112. {
  3113. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3114. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  3115. int hph_mode = wcd->hph_mode;
  3116. u8 dem_inp;
  3117. switch (event) {
  3118. case SND_SOC_DAPM_PRE_PMU:
  3119. /* Read DEM INP Select */
  3120. dem_inp = snd_soc_component_read(comp,
  3121. WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
  3122. if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
  3123. (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
  3124. return -EINVAL;
  3125. }
  3126. if (hph_mode != CLS_H_LP)
  3127. /* Ripple freq control enable */
  3128. snd_soc_component_update_bits(comp,
  3129. WCD934X_SIDO_NEW_VOUT_D_FREQ2,
  3130. WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
  3131. WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
  3132. /* Disable AutoChop timer during power up */
  3133. snd_soc_component_update_bits(comp,
  3134. WCD934X_HPH_NEW_INT_HPH_TIMER1,
  3135. WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
  3136. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3137. WCD_CLSH_STATE_HPHL, hph_mode);
  3138. break;
  3139. case SND_SOC_DAPM_POST_PMD:
  3140. /* 1000us required as per HW requirement */
  3141. usleep_range(1000, 1100);
  3142. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3143. WCD_CLSH_STATE_HPHL, hph_mode);
  3144. if (hph_mode != CLS_H_LP)
  3145. /* Ripple freq control disable */
  3146. snd_soc_component_update_bits(comp,
  3147. WCD934X_SIDO_NEW_VOUT_D_FREQ2,
  3148. WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
  3149. break;
  3150. default:
  3151. break;
  3152. }
  3153. return 0;
  3154. }
  3155. static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  3156. struct snd_kcontrol *kcontrol,
  3157. int event)
  3158. {
  3159. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3160. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  3161. int hph_mode = wcd->hph_mode;
  3162. u8 dem_inp;
  3163. switch (event) {
  3164. case SND_SOC_DAPM_PRE_PMU:
  3165. dem_inp = snd_soc_component_read(comp,
  3166. WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
  3167. if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
  3168. (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
  3169. return -EINVAL;
  3170. }
  3171. if (hph_mode != CLS_H_LP)
  3172. /* Ripple freq control enable */
  3173. snd_soc_component_update_bits(comp,
  3174. WCD934X_SIDO_NEW_VOUT_D_FREQ2,
  3175. WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
  3176. WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
  3177. /* Disable AutoChop timer during power up */
  3178. snd_soc_component_update_bits(comp,
  3179. WCD934X_HPH_NEW_INT_HPH_TIMER1,
  3180. WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
  3181. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3182. WCD_CLSH_STATE_HPHR,
  3183. hph_mode);
  3184. break;
  3185. case SND_SOC_DAPM_POST_PMD:
  3186. /* 1000us required as per HW requirement */
  3187. usleep_range(1000, 1100);
  3188. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3189. WCD_CLSH_STATE_HPHR, hph_mode);
  3190. if (hph_mode != CLS_H_LP)
  3191. /* Ripple freq control disable */
  3192. snd_soc_component_update_bits(comp,
  3193. WCD934X_SIDO_NEW_VOUT_D_FREQ2,
  3194. WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
  3195. break;
  3196. default:
  3197. break;
  3198. }
  3199. return 0;
  3200. }
  3201. static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
  3202. struct snd_kcontrol *kc, int event)
  3203. {
  3204. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3205. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  3206. switch (event) {
  3207. case SND_SOC_DAPM_PRE_PMU:
  3208. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
  3209. WCD_CLSH_STATE_LO, CLS_AB);
  3210. break;
  3211. case SND_SOC_DAPM_POST_PMD:
  3212. wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
  3213. WCD_CLSH_STATE_LO, CLS_AB);
  3214. break;
  3215. }
  3216. return 0;
  3217. }
  3218. static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  3219. struct snd_kcontrol *kcontrol,
  3220. int event)
  3221. {
  3222. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3223. switch (event) {
  3224. case SND_SOC_DAPM_POST_PMU:
  3225. /*
  3226. * 7ms sleep is required after PA is enabled as per
  3227. * HW requirement. If compander is disabled, then
  3228. * 20ms delay is needed.
  3229. */
  3230. usleep_range(20000, 20100);
  3231. snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
  3232. WCD934X_HPH_OCP_DET_MASK,
  3233. WCD934X_HPH_OCP_DET_ENABLE);
  3234. /* Remove Mute on primary path */
  3235. snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
  3236. WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
  3237. 0);
  3238. /* Enable GM3 boost */
  3239. snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
  3240. WCD934X_HPH_GM3_BOOST_EN_MASK,
  3241. WCD934X_HPH_GM3_BOOST_ENABLE);
  3242. /* Enable AutoChop timer at the end of power up */
  3243. snd_soc_component_update_bits(comp,
  3244. WCD934X_HPH_NEW_INT_HPH_TIMER1,
  3245. WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
  3246. WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
  3247. /* Remove mix path mute */
  3248. snd_soc_component_update_bits(comp,
  3249. WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
  3250. WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
  3251. break;
  3252. case SND_SOC_DAPM_PRE_PMD:
  3253. /* Enable DSD Mute before PA disable */
  3254. snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
  3255. WCD934X_HPH_OCP_DET_MASK,
  3256. WCD934X_HPH_OCP_DET_DISABLE);
  3257. snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
  3258. WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
  3259. WCD934X_RX_PATH_PGA_MUTE_ENABLE);
  3260. snd_soc_component_update_bits(comp,
  3261. WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
  3262. WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
  3263. WCD934X_RX_PATH_PGA_MUTE_ENABLE);
  3264. break;
  3265. case SND_SOC_DAPM_POST_PMD:
  3266. /*
  3267. * 5ms sleep is required after PA disable. If compander is
  3268. * disabled, then 20ms delay is needed after PA disable.
  3269. */
  3270. usleep_range(20000, 20100);
  3271. break;
  3272. }
  3273. return 0;
  3274. }
  3275. static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  3276. struct snd_kcontrol *kcontrol,
  3277. int event)
  3278. {
  3279. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3280. switch (event) {
  3281. case SND_SOC_DAPM_POST_PMU:
  3282. /*
  3283. * 7ms sleep is required after PA is enabled as per
  3284. * HW requirement. If compander is disabled, then
  3285. * 20ms delay is needed.
  3286. */
  3287. usleep_range(20000, 20100);
  3288. snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
  3289. WCD934X_HPH_OCP_DET_MASK,
  3290. WCD934X_HPH_OCP_DET_ENABLE);
  3291. /* Remove mute */
  3292. snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
  3293. WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
  3294. 0);
  3295. /* Enable GM3 boost */
  3296. snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
  3297. WCD934X_HPH_GM3_BOOST_EN_MASK,
  3298. WCD934X_HPH_GM3_BOOST_ENABLE);
  3299. /* Enable AutoChop timer at the end of power up */
  3300. snd_soc_component_update_bits(comp,
  3301. WCD934X_HPH_NEW_INT_HPH_TIMER1,
  3302. WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
  3303. WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
  3304. /* Remove mix path mute if it is enabled */
  3305. if ((snd_soc_component_read(comp,
  3306. WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
  3307. snd_soc_component_update_bits(comp,
  3308. WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
  3309. WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
  3310. WCD934X_CDC_RX_PGA_MUTE_DISABLE);
  3311. break;
  3312. case SND_SOC_DAPM_PRE_PMD:
  3313. snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
  3314. WCD934X_HPH_OCP_DET_MASK,
  3315. WCD934X_HPH_OCP_DET_DISABLE);
  3316. snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
  3317. WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
  3318. WCD934X_RX_PATH_PGA_MUTE_ENABLE);
  3319. snd_soc_component_update_bits(comp,
  3320. WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
  3321. WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
  3322. WCD934X_CDC_RX_PGA_MUTE_ENABLE);
  3323. break;
  3324. case SND_SOC_DAPM_POST_PMD:
  3325. /*
  3326. * 5ms sleep is required after PA disable. If compander is
  3327. * disabled, then 20ms delay is needed after PA disable.
  3328. */
  3329. usleep_range(20000, 20100);
  3330. break;
  3331. }
  3332. return 0;
  3333. }
  3334. static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
  3335. unsigned int dmic,
  3336. struct wcd934x_codec *wcd)
  3337. {
  3338. u8 tx_stream_fs;
  3339. u8 adc_mux_index = 0, adc_mux_sel = 0;
  3340. bool dec_found = false;
  3341. u16 adc_mux_ctl_reg, tx_fs_reg;
  3342. u32 dmic_fs;
  3343. while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
  3344. if (adc_mux_index < 4) {
  3345. adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  3346. (adc_mux_index * 2);
  3347. } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
  3348. adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
  3349. adc_mux_index - 4;
  3350. } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
  3351. ++adc_mux_index;
  3352. continue;
  3353. }
  3354. adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
  3355. & 0xF8) >> 3) - 1;
  3356. if (adc_mux_sel == dmic) {
  3357. dec_found = true;
  3358. break;
  3359. }
  3360. ++adc_mux_index;
  3361. }
  3362. if (dec_found && adc_mux_index <= 8) {
  3363. tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
  3364. tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
  3365. if (tx_stream_fs <= 4) {
  3366. if (wcd->dmic_sample_rate <=
  3367. WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
  3368. dmic_fs = wcd->dmic_sample_rate;
  3369. else
  3370. dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
  3371. } else
  3372. dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
  3373. } else {
  3374. dmic_fs = wcd->dmic_sample_rate;
  3375. }
  3376. return dmic_fs;
  3377. }
  3378. static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
  3379. u32 mclk_rate, u32 dmic_clk_rate)
  3380. {
  3381. u32 div_factor;
  3382. u8 dmic_ctl_val;
  3383. /* Default value to return in case of error */
  3384. if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
  3385. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
  3386. else
  3387. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
  3388. if (dmic_clk_rate == 0) {
  3389. dev_err(comp->dev,
  3390. "%s: dmic_sample_rate cannot be 0\n",
  3391. __func__);
  3392. goto done;
  3393. }
  3394. div_factor = mclk_rate / dmic_clk_rate;
  3395. switch (div_factor) {
  3396. case 2:
  3397. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
  3398. break;
  3399. case 3:
  3400. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
  3401. break;
  3402. case 4:
  3403. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
  3404. break;
  3405. case 6:
  3406. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
  3407. break;
  3408. case 8:
  3409. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
  3410. break;
  3411. case 16:
  3412. dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
  3413. break;
  3414. default:
  3415. dev_err(comp->dev,
  3416. "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
  3417. __func__, div_factor, mclk_rate, dmic_clk_rate);
  3418. break;
  3419. }
  3420. done:
  3421. return dmic_ctl_val;
  3422. }
  3423. static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  3424. struct snd_kcontrol *kcontrol, int event)
  3425. {
  3426. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3427. struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
  3428. u8 dmic_clk_en = 0x01;
  3429. u16 dmic_clk_reg;
  3430. s32 *dmic_clk_cnt;
  3431. u8 dmic_rate_val, dmic_rate_shift = 1;
  3432. unsigned int dmic;
  3433. u32 dmic_sample_rate;
  3434. int ret;
  3435. char *wname;
  3436. wname = strpbrk(w->name, "012345");
  3437. if (!wname) {
  3438. dev_err(comp->dev, "%s: widget not found\n", __func__);
  3439. return -EINVAL;
  3440. }
  3441. ret = kstrtouint(wname, 10, &dmic);
  3442. if (ret < 0) {
  3443. dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
  3444. __func__);
  3445. return -EINVAL;
  3446. }
  3447. switch (dmic) {
  3448. case 0:
  3449. case 1:
  3450. dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
  3451. dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
  3452. break;
  3453. case 2:
  3454. case 3:
  3455. dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
  3456. dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
  3457. break;
  3458. case 4:
  3459. case 5:
  3460. dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
  3461. dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
  3462. break;
  3463. default:
  3464. dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
  3465. __func__);
  3466. return -EINVAL;
  3467. }
  3468. switch (event) {
  3469. case SND_SOC_DAPM_PRE_PMU:
  3470. dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
  3471. wcd);
  3472. dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
  3473. dmic_sample_rate);
  3474. (*dmic_clk_cnt)++;
  3475. if (*dmic_clk_cnt == 1) {
  3476. dmic_rate_val = dmic_rate_val << dmic_rate_shift;
  3477. snd_soc_component_update_bits(comp, dmic_clk_reg,
  3478. WCD934X_DMIC_RATE_MASK,
  3479. dmic_rate_val);
  3480. snd_soc_component_update_bits(comp, dmic_clk_reg,
  3481. dmic_clk_en, dmic_clk_en);
  3482. }
  3483. break;
  3484. case SND_SOC_DAPM_POST_PMD:
  3485. (*dmic_clk_cnt)--;
  3486. if (*dmic_clk_cnt == 0)
  3487. snd_soc_component_update_bits(comp, dmic_clk_reg,
  3488. dmic_clk_en, 0);
  3489. break;
  3490. }
  3491. return 0;
  3492. }
  3493. static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
  3494. int adc_mux_n)
  3495. {
  3496. u16 mask, shift, adc_mux_in_reg;
  3497. u16 amic_mux_sel_reg;
  3498. bool is_amic;
  3499. if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
  3500. adc_mux_n == WCD934X_INVALID_ADC_MUX)
  3501. return 0;
  3502. if (adc_mux_n < 3) {
  3503. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  3504. adc_mux_n;
  3505. mask = 0x03;
  3506. shift = 0;
  3507. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  3508. 2 * adc_mux_n;
  3509. } else if (adc_mux_n < 4) {
  3510. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
  3511. mask = 0x03;
  3512. shift = 0;
  3513. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
  3514. 2 * adc_mux_n;
  3515. } else if (adc_mux_n < 7) {
  3516. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  3517. (adc_mux_n - 4);
  3518. mask = 0x0C;
  3519. shift = 2;
  3520. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
  3521. adc_mux_n - 4;
  3522. } else if (adc_mux_n < 8) {
  3523. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
  3524. mask = 0x0C;
  3525. shift = 2;
  3526. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
  3527. adc_mux_n - 4;
  3528. } else if (adc_mux_n < 12) {
  3529. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
  3530. ((adc_mux_n == 8) ? (adc_mux_n - 8) :
  3531. (adc_mux_n - 9));
  3532. mask = 0x30;
  3533. shift = 4;
  3534. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
  3535. adc_mux_n - 4;
  3536. } else if (adc_mux_n < 13) {
  3537. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
  3538. mask = 0x30;
  3539. shift = 4;
  3540. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
  3541. adc_mux_n - 4;
  3542. } else {
  3543. adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
  3544. mask = 0xC0;
  3545. shift = 6;
  3546. amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
  3547. adc_mux_n - 4;
  3548. }
  3549. is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
  3550. & mask) >> shift) == 1);
  3551. if (!is_amic)
  3552. return 0;
  3553. return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
  3554. }
  3555. static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
  3556. int amic)
  3557. {
  3558. u16 pwr_level_reg = 0;
  3559. switch (amic) {
  3560. case 1:
  3561. case 2:
  3562. pwr_level_reg = WCD934X_ANA_AMIC1;
  3563. break;
  3564. case 3:
  3565. case 4:
  3566. pwr_level_reg = WCD934X_ANA_AMIC3;
  3567. break;
  3568. default:
  3569. break;
  3570. }
  3571. return pwr_level_reg;
  3572. }
  3573. static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
  3574. struct snd_kcontrol *kcontrol, int event)
  3575. {
  3576. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3577. unsigned int decimator;
  3578. char *dec_adc_mux_name = NULL;
  3579. char *widget_name = NULL;
  3580. char *wname;
  3581. int ret = 0, amic_n;
  3582. u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
  3583. u16 tx_gain_ctl_reg;
  3584. char *dec;
  3585. u8 hpf_coff_freq;
  3586. widget_name = kstrndup(w->name, 15, GFP_KERNEL);
  3587. if (!widget_name)
  3588. return -ENOMEM;
  3589. wname = widget_name;
  3590. dec_adc_mux_name = strsep(&widget_name, " ");
  3591. if (!dec_adc_mux_name) {
  3592. dev_err(comp->dev, "%s: Invalid decimator = %s\n",
  3593. __func__, w->name);
  3594. ret = -EINVAL;
  3595. goto out;
  3596. }
  3597. dec_adc_mux_name = widget_name;
  3598. dec = strpbrk(dec_adc_mux_name, "012345678");
  3599. if (!dec) {
  3600. dev_err(comp->dev, "%s: decimator index not found\n",
  3601. __func__);
  3602. ret = -EINVAL;
  3603. goto out;
  3604. }
  3605. ret = kstrtouint(dec, 10, &decimator);
  3606. if (ret < 0) {
  3607. dev_err(comp->dev, "%s: Invalid decimator = %s\n",
  3608. __func__, wname);
  3609. ret = -EINVAL;
  3610. goto out;
  3611. }
  3612. tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
  3613. hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
  3614. dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
  3615. tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
  3616. switch (event) {
  3617. case SND_SOC_DAPM_PRE_PMU:
  3618. amic_n = wcd934x_codec_find_amic_input(comp, decimator);
  3619. if (amic_n)
  3620. pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
  3621. amic_n);
  3622. if (!pwr_level_reg)
  3623. break;
  3624. switch ((snd_soc_component_read(comp, pwr_level_reg) &
  3625. WCD934X_AMIC_PWR_LVL_MASK) >>
  3626. WCD934X_AMIC_PWR_LVL_SHIFT) {
  3627. case WCD934X_AMIC_PWR_LEVEL_LP:
  3628. snd_soc_component_update_bits(comp, dec_cfg_reg,
  3629. WCD934X_DEC_PWR_LVL_MASK,
  3630. WCD934X_DEC_PWR_LVL_LP);
  3631. break;
  3632. case WCD934X_AMIC_PWR_LEVEL_HP:
  3633. snd_soc_component_update_bits(comp, dec_cfg_reg,
  3634. WCD934X_DEC_PWR_LVL_MASK,
  3635. WCD934X_DEC_PWR_LVL_HP);
  3636. break;
  3637. case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
  3638. case WCD934X_AMIC_PWR_LEVEL_HYBRID:
  3639. default:
  3640. snd_soc_component_update_bits(comp, dec_cfg_reg,
  3641. WCD934X_DEC_PWR_LVL_MASK,
  3642. WCD934X_DEC_PWR_LVL_DF);
  3643. break;
  3644. }
  3645. break;
  3646. case SND_SOC_DAPM_POST_PMU:
  3647. hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
  3648. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  3649. if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
  3650. snd_soc_component_update_bits(comp, dec_cfg_reg,
  3651. TX_HPF_CUT_OFF_FREQ_MASK,
  3652. CF_MIN_3DB_150HZ << 5);
  3653. snd_soc_component_update_bits(comp, hpf_gate_reg,
  3654. WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
  3655. WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
  3656. /*
  3657. * Minimum 1 clk cycle delay is required as per
  3658. * HW spec.
  3659. */
  3660. usleep_range(1000, 1010);
  3661. snd_soc_component_update_bits(comp, hpf_gate_reg,
  3662. WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
  3663. 0);
  3664. }
  3665. /* apply gain after decimator is enabled */
  3666. snd_soc_component_write(comp, tx_gain_ctl_reg,
  3667. snd_soc_component_read(comp,
  3668. tx_gain_ctl_reg));
  3669. break;
  3670. case SND_SOC_DAPM_PRE_PMD:
  3671. hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
  3672. TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
  3673. if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
  3674. snd_soc_component_update_bits(comp, dec_cfg_reg,
  3675. TX_HPF_CUT_OFF_FREQ_MASK,
  3676. hpf_coff_freq << 5);
  3677. snd_soc_component_update_bits(comp, hpf_gate_reg,
  3678. WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
  3679. WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
  3680. /*
  3681. * Minimum 1 clk cycle delay is required as per
  3682. * HW spec.
  3683. */
  3684. usleep_range(1000, 1010);
  3685. snd_soc_component_update_bits(comp, hpf_gate_reg,
  3686. WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
  3687. 0);
  3688. }
  3689. break;
  3690. case SND_SOC_DAPM_POST_PMD:
  3691. snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
  3692. 0x10, 0x00);
  3693. snd_soc_component_update_bits(comp, dec_cfg_reg,
  3694. WCD934X_DEC_PWR_LVL_MASK,
  3695. WCD934X_DEC_PWR_LVL_DF);
  3696. break;
  3697. }
  3698. out:
  3699. kfree(wname);
  3700. return ret;
  3701. }
  3702. static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
  3703. u16 amic_reg, bool set)
  3704. {
  3705. u8 mask = 0x20;
  3706. u8 val;
  3707. if (amic_reg == WCD934X_ANA_AMIC1 ||
  3708. amic_reg == WCD934X_ANA_AMIC3)
  3709. mask = 0x40;
  3710. val = set ? mask : 0x00;
  3711. switch (amic_reg) {
  3712. case WCD934X_ANA_AMIC1:
  3713. case WCD934X_ANA_AMIC2:
  3714. snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
  3715. mask, val);
  3716. break;
  3717. case WCD934X_ANA_AMIC3:
  3718. case WCD934X_ANA_AMIC4:
  3719. snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
  3720. mask, val);
  3721. break;
  3722. default:
  3723. break;
  3724. }
  3725. }
  3726. static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  3727. struct snd_kcontrol *kcontrol, int event)
  3728. {
  3729. struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
  3730. switch (event) {
  3731. case SND_SOC_DAPM_PRE_PMU:
  3732. wcd934x_codec_set_tx_hold(comp, w->reg, true);
  3733. break;
  3734. default:
  3735. break;
  3736. }
  3737. return 0;
  3738. }
  3739. static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
  3740. /* Analog Outputs */
  3741. SND_SOC_DAPM_OUTPUT("EAR"),
  3742. SND_SOC_DAPM_OUTPUT("HPHL"),
  3743. SND_SOC_DAPM_OUTPUT("HPHR"),
  3744. SND_SOC_DAPM_OUTPUT("LINEOUT1"),
  3745. SND_SOC_DAPM_OUTPUT("LINEOUT2"),
  3746. SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
  3747. SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
  3748. SND_SOC_DAPM_OUTPUT("ANC EAR"),
  3749. SND_SOC_DAPM_OUTPUT("ANC HPHL"),
  3750. SND_SOC_DAPM_OUTPUT("ANC HPHR"),
  3751. SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
  3752. SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
  3753. SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
  3754. SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
  3755. AIF1_PB, 0, wcd934x_codec_enable_slim,
  3756. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3757. SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
  3758. AIF2_PB, 0, wcd934x_codec_enable_slim,
  3759. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3760. SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
  3761. AIF3_PB, 0, wcd934x_codec_enable_slim,
  3762. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3763. SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
  3764. AIF4_PB, 0, wcd934x_codec_enable_slim,
  3765. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  3766. SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
  3767. &slim_rx_mux[WCD934X_RX0]),
  3768. SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
  3769. &slim_rx_mux[WCD934X_RX1]),
  3770. SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
  3771. &slim_rx_mux[WCD934X_RX2]),
  3772. SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
  3773. &slim_rx_mux[WCD934X_RX3]),
  3774. SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
  3775. &slim_rx_mux[WCD934X_RX4]),
  3776. SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
  3777. &slim_rx_mux[WCD934X_RX5]),
  3778. SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
  3779. &slim_rx_mux[WCD934X_RX6]),
  3780. SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
  3781. &slim_rx_mux[WCD934X_RX7]),
  3782. SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
  3783. SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3784. SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3785. SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3786. SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
  3787. SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
  3788. SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
  3789. SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
  3790. SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
  3791. &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
  3792. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3793. SND_SOC_DAPM_POST_PMD),
  3794. SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
  3795. &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
  3796. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3797. SND_SOC_DAPM_POST_PMD),
  3798. SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
  3799. &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
  3800. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3801. SND_SOC_DAPM_POST_PMD),
  3802. SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
  3803. &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
  3804. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3805. SND_SOC_DAPM_POST_PMD),
  3806. SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
  3807. &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
  3808. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3809. SND_SOC_DAPM_POST_PMD),
  3810. SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
  3811. &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
  3812. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3813. SND_SOC_DAPM_POST_PMD),
  3814. SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
  3815. &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
  3816. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3817. SND_SOC_DAPM_POST_PMD),
  3818. SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3819. &rx_int0_1_mix_inp0_mux),
  3820. SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3821. &rx_int0_1_mix_inp1_mux),
  3822. SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3823. &rx_int0_1_mix_inp2_mux),
  3824. SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3825. &rx_int1_1_mix_inp0_mux),
  3826. SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3827. &rx_int1_1_mix_inp1_mux),
  3828. SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3829. &rx_int1_1_mix_inp2_mux),
  3830. SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3831. &rx_int2_1_mix_inp0_mux),
  3832. SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3833. &rx_int2_1_mix_inp1_mux),
  3834. SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3835. &rx_int2_1_mix_inp2_mux),
  3836. SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3837. &rx_int3_1_mix_inp0_mux),
  3838. SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3839. &rx_int3_1_mix_inp1_mux),
  3840. SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3841. &rx_int3_1_mix_inp2_mux),
  3842. SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3843. &rx_int4_1_mix_inp0_mux),
  3844. SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3845. &rx_int4_1_mix_inp1_mux),
  3846. SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3847. &rx_int4_1_mix_inp2_mux),
  3848. SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3849. &rx_int7_1_mix_inp0_mux),
  3850. SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3851. &rx_int7_1_mix_inp1_mux),
  3852. SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3853. &rx_int7_1_mix_inp2_mux),
  3854. SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
  3855. &rx_int8_1_mix_inp0_mux),
  3856. SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
  3857. &rx_int8_1_mix_inp1_mux),
  3858. SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
  3859. &rx_int8_1_mix_inp2_mux),
  3860. SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3861. SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3862. SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3863. SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
  3864. rx_int1_asrc_switch,
  3865. ARRAY_SIZE(rx_int1_asrc_switch)),
  3866. SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3867. SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
  3868. rx_int2_asrc_switch,
  3869. ARRAY_SIZE(rx_int2_asrc_switch)),
  3870. SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3871. SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
  3872. rx_int3_asrc_switch,
  3873. ARRAY_SIZE(rx_int3_asrc_switch)),
  3874. SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3875. SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
  3876. rx_int4_asrc_switch,
  3877. ARRAY_SIZE(rx_int4_asrc_switch)),
  3878. SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3879. SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3880. SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  3881. SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
  3882. SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3883. SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3884. SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3885. SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3886. SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3887. SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3888. SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3889. SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3890. SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  3891. SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  3892. SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
  3893. NULL, 0, NULL, 0),
  3894. SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
  3895. NULL, 0, NULL, 0),
  3896. SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
  3897. 0, &rx_int0_mix2_inp_mux, NULL,
  3898. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3899. SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
  3900. 0, &rx_int1_mix2_inp_mux, NULL,
  3901. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3902. SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
  3903. 0, &rx_int2_mix2_inp_mux, NULL,
  3904. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3905. SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
  3906. 0, &rx_int3_mix2_inp_mux, NULL,
  3907. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3908. SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
  3909. 0, &rx_int4_mix2_inp_mux, NULL,
  3910. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3911. SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
  3912. 0, &rx_int7_mix2_inp_mux, NULL,
  3913. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3914. SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
  3915. SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
  3916. SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
  3917. SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
  3918. SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
  3919. SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
  3920. SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
  3921. SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
  3922. SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
  3923. 0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
  3924. SND_SOC_DAPM_POST_PMU),
  3925. SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
  3926. 1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
  3927. SND_SOC_DAPM_POST_PMU),
  3928. SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
  3929. 4, 0, NULL, 0),
  3930. SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
  3931. 4, 0, NULL, 0),
  3932. SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
  3933. &rx_int0_dem_inp_mux),
  3934. SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
  3935. &rx_int1_dem_inp_mux),
  3936. SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
  3937. &rx_int2_dem_inp_mux),
  3938. SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
  3939. &rx_int0_1_interp_mux,
  3940. wcd934x_codec_enable_main_path,
  3941. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3942. SND_SOC_DAPM_POST_PMD),
  3943. SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
  3944. &rx_int1_1_interp_mux,
  3945. wcd934x_codec_enable_main_path,
  3946. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3947. SND_SOC_DAPM_POST_PMD),
  3948. SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
  3949. &rx_int2_1_interp_mux,
  3950. wcd934x_codec_enable_main_path,
  3951. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3952. SND_SOC_DAPM_POST_PMD),
  3953. SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
  3954. &rx_int3_1_interp_mux,
  3955. wcd934x_codec_enable_main_path,
  3956. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3957. SND_SOC_DAPM_POST_PMD),
  3958. SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
  3959. &rx_int4_1_interp_mux,
  3960. wcd934x_codec_enable_main_path,
  3961. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3962. SND_SOC_DAPM_POST_PMD),
  3963. SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
  3964. &rx_int7_1_interp_mux,
  3965. wcd934x_codec_enable_main_path,
  3966. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3967. SND_SOC_DAPM_POST_PMD),
  3968. SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
  3969. &rx_int8_1_interp_mux,
  3970. wcd934x_codec_enable_main_path,
  3971. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3972. SND_SOC_DAPM_POST_PMD),
  3973. SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
  3974. &rx_int0_2_interp_mux),
  3975. SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
  3976. &rx_int1_2_interp_mux),
  3977. SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
  3978. &rx_int2_2_interp_mux),
  3979. SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
  3980. &rx_int3_2_interp_mux),
  3981. SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
  3982. &rx_int4_2_interp_mux),
  3983. SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
  3984. &rx_int7_2_interp_mux),
  3985. SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
  3986. &rx_int8_2_interp_mux),
  3987. SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
  3988. 0, 0, wcd934x_codec_ear_dac_event,
  3989. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3990. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3991. SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
  3992. 5, 0, wcd934x_codec_hphl_dac_event,
  3993. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3994. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3995. SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
  3996. 4, 0, wcd934x_codec_hphr_dac_event,
  3997. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3998. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3999. SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
  4000. 0, 0, wcd934x_codec_lineout_dac_event,
  4001. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4002. SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
  4003. 0, 0, wcd934x_codec_lineout_dac_event,
  4004. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4005. SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
  4006. SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
  4007. wcd934x_codec_enable_hphl_pa,
  4008. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4009. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4010. SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
  4011. wcd934x_codec_enable_hphr_pa,
  4012. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4013. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4014. SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
  4015. NULL, 0),
  4016. SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
  4017. NULL, 0),
  4018. SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
  4019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4020. SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
  4021. 0, 0, NULL, 0),
  4022. SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
  4023. 0, 0, NULL, 0),
  4024. SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
  4025. 0, 0, NULL, 0),
  4026. SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
  4027. 0, 0, NULL, 0),
  4028. SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
  4029. wcd934x_codec_enable_interp_clk,
  4030. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4031. SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
  4032. wcd934x_codec_enable_interp_clk,
  4033. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4034. SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
  4035. wcd934x_codec_enable_interp_clk,
  4036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4037. SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
  4038. wcd934x_codec_enable_interp_clk,
  4039. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4040. SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
  4041. wcd934x_codec_enable_interp_clk,
  4042. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4043. SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
  4044. wcd934x_codec_enable_interp_clk,
  4045. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4046. SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
  4047. wcd934x_codec_enable_interp_clk,
  4048. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4049. SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
  4050. 0, 0, NULL, 0),
  4051. SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
  4052. 0, 0, NULL, 0),
  4053. SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
  4054. 0, 0, NULL, 0),
  4055. SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
  4056. 0, 0, NULL, 0),
  4057. SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
  4058. 0, 0, NULL, 0),
  4059. SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
  4060. 0, 0, NULL, 0),
  4061. SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
  4062. 0, 0, NULL, 0),
  4063. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  4064. wcd934x_codec_enable_mclk,
  4065. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4066. /* TX */
  4067. SND_SOC_DAPM_INPUT("AMIC1"),
  4068. SND_SOC_DAPM_INPUT("AMIC2"),
  4069. SND_SOC_DAPM_INPUT("AMIC3"),
  4070. SND_SOC_DAPM_INPUT("AMIC4"),
  4071. SND_SOC_DAPM_INPUT("AMIC5"),
  4072. SND_SOC_DAPM_INPUT("DMIC0 Pin"),
  4073. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  4074. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  4075. SND_SOC_DAPM_INPUT("DMIC3 Pin"),
  4076. SND_SOC_DAPM_INPUT("DMIC4 Pin"),
  4077. SND_SOC_DAPM_INPUT("DMIC5 Pin"),
  4078. SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
  4079. AIF1_CAP, 0, wcd934x_codec_enable_slim,
  4080. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4081. SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
  4082. AIF2_CAP, 0, wcd934x_codec_enable_slim,
  4083. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4084. SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
  4085. AIF3_CAP, 0, wcd934x_codec_enable_slim,
  4086. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4087. SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
  4088. SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
  4089. SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
  4090. SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
  4091. SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
  4092. SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
  4093. SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
  4094. SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
  4095. SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
  4096. SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
  4097. SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
  4098. SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
  4099. SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
  4100. /* Digital Mic Inputs */
  4101. SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
  4102. wcd934x_codec_enable_dmic,
  4103. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4104. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  4105. wcd934x_codec_enable_dmic,
  4106. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4107. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
  4108. wcd934x_codec_enable_dmic,
  4109. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4110. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
  4111. wcd934x_codec_enable_dmic,
  4112. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4113. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
  4114. wcd934x_codec_enable_dmic,
  4115. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4116. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
  4117. wcd934x_codec_enable_dmic,
  4118. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4119. SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
  4120. SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
  4121. SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
  4122. SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
  4123. SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
  4124. SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
  4125. SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
  4126. SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
  4127. SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
  4128. SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
  4129. SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
  4130. SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
  4131. SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
  4132. SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
  4133. SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
  4134. SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
  4135. SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
  4136. SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
  4137. SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
  4138. &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
  4139. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4140. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4141. SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
  4142. &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
  4143. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4144. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4145. SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
  4146. &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
  4147. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4148. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4149. SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
  4150. &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
  4151. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4152. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4153. SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
  4154. &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
  4155. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4156. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4157. SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
  4158. &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
  4159. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4160. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4161. SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
  4162. &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
  4163. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4164. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4165. SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
  4166. &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
  4167. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4168. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4169. SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
  4170. &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
  4171. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  4172. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  4173. SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
  4174. wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4175. SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
  4176. wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4177. SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
  4178. wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4179. SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
  4180. wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
  4181. SND_SOC_DAPM_SUPPLY("MIC BIAS1", WCD934X_ANA_MICB1, 6, 0, NULL,
  4182. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4183. SND_SOC_DAPM_SUPPLY("MIC BIAS2", WCD934X_ANA_MICB2, 6, 0, NULL,
  4184. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4185. SND_SOC_DAPM_SUPPLY("MIC BIAS3", WCD934X_ANA_MICB3, 6, 0, NULL,
  4186. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4187. SND_SOC_DAPM_SUPPLY("MIC BIAS4", WCD934X_ANA_MICB4, 6, 0, NULL,
  4188. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  4189. SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
  4190. SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
  4191. &cdc_if_tx0_mux),
  4192. SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
  4193. &cdc_if_tx1_mux),
  4194. SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
  4195. &cdc_if_tx2_mux),
  4196. SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
  4197. &cdc_if_tx3_mux),
  4198. SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
  4199. &cdc_if_tx4_mux),
  4200. SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
  4201. &cdc_if_tx5_mux),
  4202. SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
  4203. &cdc_if_tx6_mux),
  4204. SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
  4205. &cdc_if_tx7_mux),
  4206. SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
  4207. &cdc_if_tx8_mux),
  4208. SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
  4209. &cdc_if_tx9_mux),
  4210. SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
  4211. &cdc_if_tx10_mux),
  4212. SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
  4213. &cdc_if_tx11_mux),
  4214. SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
  4215. &cdc_if_tx11_inp1_mux),
  4216. SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
  4217. &cdc_if_tx13_mux),
  4218. SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
  4219. &cdc_if_tx13_inp1_mux),
  4220. SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
  4221. aif1_slim_cap_mixer,
  4222. ARRAY_SIZE(aif1_slim_cap_mixer)),
  4223. SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
  4224. aif2_slim_cap_mixer,
  4225. ARRAY_SIZE(aif2_slim_cap_mixer)),
  4226. SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
  4227. aif3_slim_cap_mixer,
  4228. ARRAY_SIZE(aif3_slim_cap_mixer)),
  4229. };
  4230. static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
  4231. /* RX0-RX7 */
  4232. WCD934X_SLIM_RX_AIF_PATH(0),
  4233. WCD934X_SLIM_RX_AIF_PATH(1),
  4234. WCD934X_SLIM_RX_AIF_PATH(2),
  4235. WCD934X_SLIM_RX_AIF_PATH(3),
  4236. WCD934X_SLIM_RX_AIF_PATH(4),
  4237. WCD934X_SLIM_RX_AIF_PATH(5),
  4238. WCD934X_SLIM_RX_AIF_PATH(6),
  4239. WCD934X_SLIM_RX_AIF_PATH(7),
  4240. /* RX0 Ear out */
  4241. WCD934X_INTERPOLATOR_PATH(0),
  4242. WCD934X_INTERPOLATOR_MIX2(0),
  4243. {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
  4244. {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
  4245. {"RX INT0 DAC", NULL, "RX_BIAS"},
  4246. {"EAR PA", NULL, "RX INT0 DAC"},
  4247. {"EAR", NULL, "EAR PA"},
  4248. /* RX1 Headphone left */
  4249. WCD934X_INTERPOLATOR_PATH(1),
  4250. WCD934X_INTERPOLATOR_MIX2(1),
  4251. {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
  4252. {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
  4253. {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
  4254. {"RX INT1 DAC", NULL, "RX_BIAS"},
  4255. {"HPHL PA", NULL, "RX INT1 DAC"},
  4256. {"HPHL", NULL, "HPHL PA"},
  4257. /* RX2 Headphone right */
  4258. WCD934X_INTERPOLATOR_PATH(2),
  4259. WCD934X_INTERPOLATOR_MIX2(2),
  4260. {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
  4261. {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
  4262. {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
  4263. {"RX INT2 DAC", NULL, "RX_BIAS"},
  4264. {"HPHR PA", NULL, "RX INT2 DAC"},
  4265. {"HPHR", NULL, "HPHR PA"},
  4266. /* RX3 HIFi LineOut1 */
  4267. WCD934X_INTERPOLATOR_PATH(3),
  4268. WCD934X_INTERPOLATOR_MIX2(3),
  4269. {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
  4270. {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
  4271. {"RX INT3 DAC", NULL, "RX_BIAS"},
  4272. {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
  4273. {"LINEOUT1", NULL, "LINEOUT1 PA"},
  4274. /* RX4 HIFi LineOut2 */
  4275. WCD934X_INTERPOLATOR_PATH(4),
  4276. WCD934X_INTERPOLATOR_MIX2(4),
  4277. {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
  4278. {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
  4279. {"RX INT4 DAC", NULL, "RX_BIAS"},
  4280. {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
  4281. {"LINEOUT2", NULL, "LINEOUT2 PA"},
  4282. /* RX7 Speaker Left Out PA */
  4283. WCD934X_INTERPOLATOR_PATH(7),
  4284. WCD934X_INTERPOLATOR_MIX2(7),
  4285. {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
  4286. {"RX INT7 CHAIN", NULL, "RX_BIAS"},
  4287. {"RX INT7 CHAIN", NULL, "SBOOST0"},
  4288. {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
  4289. {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
  4290. /* RX8 Speaker Right Out PA */
  4291. WCD934X_INTERPOLATOR_PATH(8),
  4292. {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
  4293. {"RX INT8 CHAIN", NULL, "RX_BIAS"},
  4294. {"RX INT8 CHAIN", NULL, "SBOOST1"},
  4295. {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
  4296. {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
  4297. /* Tx */
  4298. {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
  4299. {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
  4300. {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
  4301. WCD934X_SLIM_TX_AIF_PATH(0),
  4302. WCD934X_SLIM_TX_AIF_PATH(1),
  4303. WCD934X_SLIM_TX_AIF_PATH(2),
  4304. WCD934X_SLIM_TX_AIF_PATH(3),
  4305. WCD934X_SLIM_TX_AIF_PATH(4),
  4306. WCD934X_SLIM_TX_AIF_PATH(5),
  4307. WCD934X_SLIM_TX_AIF_PATH(6),
  4308. WCD934X_SLIM_TX_AIF_PATH(7),
  4309. WCD934X_SLIM_TX_AIF_PATH(8),
  4310. WCD934X_ADC_MUX(0),
  4311. WCD934X_ADC_MUX(1),
  4312. WCD934X_ADC_MUX(2),
  4313. WCD934X_ADC_MUX(3),
  4314. WCD934X_ADC_MUX(4),
  4315. WCD934X_ADC_MUX(5),
  4316. WCD934X_ADC_MUX(6),
  4317. WCD934X_ADC_MUX(7),
  4318. WCD934X_ADC_MUX(8),
  4319. {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
  4320. {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
  4321. {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
  4322. {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
  4323. {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
  4324. {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
  4325. {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
  4326. {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
  4327. {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
  4328. {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
  4329. {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
  4330. { "DMIC0", NULL, "DMIC0 Pin" },
  4331. { "DMIC1", NULL, "DMIC1 Pin" },
  4332. { "DMIC2", NULL, "DMIC2 Pin" },
  4333. { "DMIC3", NULL, "DMIC3 Pin" },
  4334. { "DMIC4", NULL, "DMIC4 Pin" },
  4335. { "DMIC5", NULL, "DMIC5 Pin" },
  4336. {"ADC1", NULL, "AMIC1"},
  4337. {"ADC2", NULL, "AMIC2"},
  4338. {"ADC3", NULL, "AMIC3"},
  4339. {"ADC4", NULL, "AMIC4_5 SEL"},
  4340. WCD934X_IIR_INP_MUX(0),
  4341. WCD934X_IIR_INP_MUX(1),
  4342. {"SRC0", NULL, "IIR0"},
  4343. {"SRC1", NULL, "IIR1"},
  4344. };
  4345. static const struct snd_soc_component_driver wcd934x_component_drv = {
  4346. .probe = wcd934x_comp_probe,
  4347. .remove = wcd934x_comp_remove,
  4348. .set_sysclk = wcd934x_comp_set_sysclk,
  4349. .controls = wcd934x_snd_controls,
  4350. .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
  4351. .dapm_widgets = wcd934x_dapm_widgets,
  4352. .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
  4353. .dapm_routes = wcd934x_audio_map,
  4354. .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
  4355. };
  4356. static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
  4357. {
  4358. struct device *dev = &wcd->sdev->dev;
  4359. struct device_node *ifc_dev_np;
  4360. ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
  4361. if (!ifc_dev_np) {
  4362. dev_err(dev, "No Interface device found\n");
  4363. return -EINVAL;
  4364. }
  4365. wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
  4366. of_node_put(ifc_dev_np);
  4367. if (!wcd->sidev) {
  4368. dev_err(dev, "Unable to get SLIM Interface device\n");
  4369. return -EINVAL;
  4370. }
  4371. slim_get_logical_addr(wcd->sidev);
  4372. wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
  4373. &wcd934x_ifc_regmap_config);
  4374. if (IS_ERR(wcd->if_regmap)) {
  4375. dev_err(dev, "Failed to allocate ifc register map\n");
  4376. return PTR_ERR(wcd->if_regmap);
  4377. }
  4378. of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
  4379. &wcd->dmic_sample_rate);
  4380. return 0;
  4381. }
  4382. static int wcd934x_codec_probe(struct platform_device *pdev)
  4383. {
  4384. struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
  4385. struct wcd934x_codec *wcd;
  4386. struct device *dev = &pdev->dev;
  4387. int ret, irq;
  4388. wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
  4389. if (!wcd)
  4390. return -ENOMEM;
  4391. wcd->dev = dev;
  4392. wcd->regmap = data->regmap;
  4393. wcd->extclk = data->extclk;
  4394. wcd->sdev = to_slim_device(data->dev);
  4395. mutex_init(&wcd->sysclk_mutex);
  4396. ret = wcd934x_codec_parse_data(wcd);
  4397. if (ret) {
  4398. dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
  4399. return ret;
  4400. }
  4401. /* set default rate 9P6MHz */
  4402. regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
  4403. WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
  4404. WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
  4405. memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
  4406. memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
  4407. irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
  4408. if (irq < 0) {
  4409. dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
  4410. return irq;
  4411. }
  4412. ret = devm_request_threaded_irq(dev, irq, NULL,
  4413. wcd934x_slim_irq_handler,
  4414. IRQF_TRIGGER_RISING,
  4415. "slim", wcd);
  4416. if (ret) {
  4417. dev_err(dev, "Failed to request slimbus irq\n");
  4418. return ret;
  4419. }
  4420. wcd934x_register_mclk_output(wcd);
  4421. platform_set_drvdata(pdev, wcd);
  4422. return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
  4423. wcd934x_slim_dais,
  4424. ARRAY_SIZE(wcd934x_slim_dais));
  4425. }
  4426. static const struct platform_device_id wcd934x_driver_id[] = {
  4427. {
  4428. .name = "wcd934x-codec",
  4429. },
  4430. {},
  4431. };
  4432. MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
  4433. static struct platform_driver wcd934x_codec_driver = {
  4434. .probe = &wcd934x_codec_probe,
  4435. .id_table = wcd934x_driver_id,
  4436. .driver = {
  4437. .name = "wcd934x-codec",
  4438. }
  4439. };
  4440. MODULE_ALIAS("platform:wcd934x-codec");
  4441. module_platform_driver(wcd934x_codec_driver);
  4442. MODULE_DESCRIPTION("WCD934x codec driver");
  4443. MODULE_LICENSE("GPL v2");